Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	15		T29	14		T138	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T29	11		T117	16		T208	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	1		T8	17		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1274	1			T2	2		T5	1		T21	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	1		T11	14		T93	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	1		T10	1		T93	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T26	4		T174	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T6	1		T30	1		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	1		T119	1		T136	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T122	1		T123	1		T14	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	2		T173	11		T119	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T12	2		T207	1		T156	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T119	11		T120	5		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T165	1		T233	1		T209	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T30	1		T13	1		T126	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T6	1		T139	15		T128	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	1		T11	2		T144	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	1		T29	15		T117	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T231	2		T232	2		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T232	16		T234	1		T235	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14456	1			T3	7		T7	183		T9	307
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	4		T29	11		T138	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T29	10		T117	13		T208	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T123	4		T156	13		T244	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1319	1			T5	14		T21	34		T30	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T11	10		T140	8		T211	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	10		T181	5		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T26	2		T63	8		T245	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T6	6		T30	18		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T119	7		T127	9		T153	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T123	19		T90	17		T219	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	1		T119	3		T161	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	1		T179	2		T246	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T119	7		T126	14		T129	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T165	8		T209	13		T157	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T30	10		T126	7		T220	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	13		T128	14		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	11		T144	16		T210	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	11		T29	11		T205	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T155	5		T20	2		T248	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T232	11		T249	11		T239	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T156	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T228	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T10	1		T229	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T214	6		T230	2		T229	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	15		T29	14		T138	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T29	11		T117	16		T208	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	1		T11	2		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T30	1		T207	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	17		T11	14		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T93	15		T125	1		T27	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T9	1		T93	15		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T1	1		T10	1		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T7	1		T136	5		T139	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	1		T30	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	2		T173	11		T119	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	2		T207	1		T156	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T119	11		T122	1		T126	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T209	13		T158	1		T179	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	1		T126	12		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T6	1		T165	1		T139	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T6	1		T11	2		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1328	1			T2	2		T5	1		T21	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T10	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T214	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	4		T29	11		T138	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T29	10		T117	13		T208	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T123	17		T156	13		T250	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T30	7		T207	9		T241	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T11	10		T140	8		T211	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T125	7		T27	1		T181	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T153	12		T63	8		T237	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T10	10		T15	1		T243	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T127	9		T26	2		T153	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	6		T30	18		T123	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	1		T119	10		T161	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	1		T149	2		T251	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T119	7		T126	22		T129	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T209	13		T179	2		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T126	14		T231	13		T163	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T6	13		T165	8		T125	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	11		T30	10		T144	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1302	1			T5	14		T21	34		T29	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

auto[0]

3962

1

T3

1

T5

14

T6

30