Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22980

1

T1

2

T2

2

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19609

1

T1

1

T2

2

T3

7

auto[ADC_CTRL_FILTER_COND_OUT]

3371

1

T1

1

T3

3

T6

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17458

1

T3

10

T6

12

T7

183

auto[1]

5522

1

T1

2

T2

2

T5

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19269

1

T1

2

T2

2

T3

9

auto[1]

3711

1

T3

1

T8

16

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T215	17		T221	10		-	-
values[0]	39	1			T11	2		T252	15		T253	1
values[1]	646	1			T10	12		T30	11		T130	10
values[2]	690	1			T3	3		T132	1		T233	1
values[3]	702	1			T6	12		T7	1		T29	47
values[4]	724	1			T1	1		T9	19		T10	11
values[5]	2808	1			T1	1		T2	2		T5	15
values[6]	734	1			T117	29		T139	15		T207	11
values[7]	662	1			T8	17		T29	25		T93	3
values[8]	693	1			T9	1		T12	3		T119	18
values[9]	827	1			T6	21		T173	11		T119	19
minimum	14428	1			T3	7		T7	183		T9	307

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	752	1			T30	11		T121	1		T25	3
values[1]	703	1			T3	3		T7	1		T10	12
values[2]	712	1			T1	1		T6	12		T11	2
values[3]	2978	1			T2	2		T5	15		T9	19
values[4]	603	1			T1	1		T11	24		T93	12
values[5]	724	1			T117	29		T120	5		T161	10
values[6]	696	1			T8	17		T29	25		T93	3
values[7]	577	1			T12	3		T137	1		T138	15
values[8]	669	1			T6	21		T9	1		T173	11
values[9]	113	1			T119	8		T123	5		T126	28
minimum	14453	1			T3	7		T7	183		T9	307

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

3962

1

T3

1

T5

14

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T30	11		T140	11		T127	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T121	1		T25	3		T247	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T132	1		T233	1		T208	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	2		T7	1		T10	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	1		T6	12		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T29	11		T30	19		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1661	1			T2	2		T5	15		T21	37
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	5		T10	11		T144	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	11		T165	9		T90	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	1		T93	1		T207	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T120	1		T161	10		T124	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T117	14		T139	1		T207	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T93	1		T119	8		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	1		T29	12		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T137	1		T123	14		T126	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	2		T138	13		T23	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T6	7		T9	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	14		T173	1		T119	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T119	8		T126	23		T176	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T123	5		T92	1		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14350	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T11	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T153	5		T241	9		T213	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T214	5		T254	3		T255	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T208	14		T256	3		T216	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	1		T93	14		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	1		T136	4		T209	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T29	10		T152	1		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T29	14		T143	32		T159	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	14		T144	15		T126	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	13		T90	18		T214	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T93	11		T211	10		T156	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T120	4		T124	8		T63	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T117	15		T139	14		T157	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T93	2		T119	10		T206	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T8	16		T29	13		T90	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T126	4		T129	7		T181	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	1		T138	2		T67	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T139	13		T16	2		T219	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T173	10		T119	7		T206	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T126	5		T176	7		T257	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T92	9		T210	4		T163	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T11	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T215	9		T221	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T252	15		T258	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T11	1		T253	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T30	11		T127	23		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	12		T130	1		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T132	1		T233	1		T140	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	2		T156	13		T14	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	12		T29	12		T161	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T7	1		T29	11		T30	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T11	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	5		T10	11		T93	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1627	1			T2	2		T5	15		T11	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	1		T211	11		T26	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T124	9		T259	1		T260	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T117	14		T139	1		T207	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T93	1		T122	1		T161	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T8	1		T29	12		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	1		T119	8		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	2		T138	13		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T6	7		T119	8		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T6	14		T173	1		T119	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T215	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T258	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T11	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T241	9		T67	2		T261	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T130	9		T214	5		T255	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T153	17		T213	5		T256	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	1		T156	13		T128	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T29	14		T208	14		T27	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T29	10		T93	14		T152	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	1		T136	4		T209	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T9	14		T93	11		T144	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	956	1			T11	13		T143	32		T159	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T211	10		T26	2		T63	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T124	8		T167	7		T262	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T117	15		T139	14		T156	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T93	2		T206	6		T128	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T8	16		T29	13		T90	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T119	10		T129	7		T174	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	1		T138	2		T206	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T139	13		T126	9		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T173	10		T119	7		T152	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T30	1		T140	1		T127	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T121	1		T25	3		T247	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T132	1		T233	1		T208	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T3	2		T7	1		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	1		T6	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	11		T30	1		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T2	2		T5	1		T21	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	15		T10	1		T144	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	14		T165	1		T90	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	1		T93	12		T207	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T120	5		T161	1		T124	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T117	16		T139	15		T207	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T93	3		T119	11		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	17		T29	14		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T137	1		T123	1		T126	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	2		T138	3		T23	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T6	1		T9	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T6	1		T173	11		T119	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T119	1		T126	6		T176	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T123	1		T92	10		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14430	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T11	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T30	10		T140	10		T127	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T247	10		T214	2		T254	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T208	6		T256	1		T18	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	1		T10	11		T30	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	11		T161	15		T140	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T29	10		T30	18		T161	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T5	14		T21	34		T29	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	4		T10	10		T144	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	10		T165	8		T90	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T207	9		T211	10		T156	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T161	9		T124	8		T63	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T117	13		T125	7		T157	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T119	7		T128	10		T181	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T29	11		T90	9		T243	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T123	13		T126	7		T129	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	1		T138	12		T255	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T6	6		T125	10		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	13		T119	3		T123	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T119	7		T126	22		T176	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T123	4		T210	4		T219	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T127	9		T263	12		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T215	9		T221	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T252	1		T258	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T11	2		T253	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T30	1		T127	2		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	1		T130	10		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T132	1		T233	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	2		T156	14		T14	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	1		T29	15		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	1		T29	11		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	1		T11	2		T136	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	15		T10	1		T93	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T2	2		T5	1		T11	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T1	1		T211	11		T26	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T124	9		T259	1		T260	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T117	16		T139	15		T207	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T93	3		T122	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	17		T29	14		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	1		T119	11		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	2		T138	3		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	1		T119	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T6	1		T173	11		T119	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T215	8		T221	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T252	14		T258	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T30	10		T127	21		T241	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	11		T214	2		T255	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T140	10		T153	19		T256	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	1		T156	12		T128	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T6	11		T29	11		T161	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T29	10		T30	25		T161	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T140	8		T209	13		T142	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T9	4		T10	10		T144	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T5	14		T11	10		T21	34
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T211	10		T26	2		T264	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T124	8		T155	2		T265	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T117	13		T207	9		T125	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T161	9		T128	10		T63	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T29	11		T90	9		T250	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T119	7		T123	13		T129	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	1		T138	12		T255	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	6		T119	7		T125	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	13		T119	3		T123	23

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

auto[0]

3962

1

T3

1

T5

14

T6

30