Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22980

1

T1

2

T2

2

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19576

1

T1

1

T2

2

T3

7

auto[ADC_CTRL_FILTER_COND_OUT]

3404

1

T1

1

T3

3

T6

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17116

1

T1

1

T3

8

T6

19

auto[1]

5864

1

T1

1

T2

2

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19269

1

T1

2

T2

2

T3

9

auto[1]

3711

1

T3

1

T8

16

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	332	1			T3	2		T7	3		T9	19
values[0]	46	1			T69	1		T266	1		T267	25
values[1]	709	1			T10	11		T29	26		T136	5
values[2]	2836	1			T2	2		T5	15		T6	12
values[3]	834	1			T6	7		T8	17		T9	1
values[4]	527	1			T3	3		T6	14		T30	11
values[5]	637	1			T1	1		T7	1		T30	19
values[6]	530	1			T1	1		T122	1		T25	3
values[7]	635	1			T9	19		T10	12		T119	11
values[8]	785	1			T29	21		T93	3		T137	1
values[9]	986	1			T173	11		T119	8		T130	10
minimum	14123	1			T3	5		T7	180		T9	288

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	924	1			T6	12		T10	11		T29	26
values[1]	2802	1			T2	2		T5	15		T9	1
values[2]	774	1			T6	7		T8	17		T11	2
values[3]	610	1			T3	3		T6	14		T11	24
values[4]	701	1			T1	1		T7	1		T30	19
values[5]	498	1			T1	1		T119	11		T122	1
values[6]	620	1			T9	19		T10	12		T29	21
values[7]	668	1			T173	11		T13	1		T144	32
values[8]	780	1			T119	8		T130	10		T122	1
values[9]	174	1			T23	7		T268	1		T266	1
minimum	14429	1			T3	7		T7	183		T9	307

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

3962

1

T3

1

T5

14

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T10	11		T29	12		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	12		T209	14		T175	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1559	1			T2	2		T5	15		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	2		T30	8		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T8	1		T29	12		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	7		T11	1		T30	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	11		T117	1		T119	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	2		T6	14		T165	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	1		T7	1		T30	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T127	13		T147	1		T259	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T25	3		T264	15		T80	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	1		T119	4		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T10	12		T29	11		T93	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	5		T120	1		T123	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T13	1		T84	1		T181	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T173	1		T144	17		T211	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T233	1		T14	2		T206	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T119	8		T130	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T261	14		T238	1		T269	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T23	1		T268	1		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T270	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T29	14		T206	10		T157	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T209	12		T227	13		T254	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	922	1			T11	1		T143	32		T159	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	1		T136	4		T174	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	16		T29	13		T93	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	1		T90	18		T216	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	13		T119	10		T139	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T3	1		T124	8		T222	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T16	2		T216	12		T63	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T147	15		T148	2		T231	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T172	4		T242	14		T271	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T119	7		T156	12		T213	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T29	10		T93	2		T208	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T9	14		T120	4		T153	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T84	5		T181	5		T250	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T173	10		T144	15		T211	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T128	10		T66	8		T18	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T130	9		T138	2		T156	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T261	12		T238	5		T164	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T23	6		T236	5		T272	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T3	2		T7	3		T9	19
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T138	13		T273	3		T274	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T266	1		T275	4		T276	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T69	1		T267	12		T270	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T10	11		T29	12		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T136	1		T132	1		T209	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1553	1			T2	2		T5	15		T21	37
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T6	12		T12	2		T30	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	1		T9	1		T11	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	7		T11	1		T174	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T117	1		T139	2		T126	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	2		T6	14		T30	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	1		T7	1		T30	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T259	1		T246	17		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T25	3		T161	10		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T1	1		T122	1		T125	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	12		T208	7		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	5		T119	4		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T29	11		T93	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T144	17		T211	11		T125	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T233	1		T14	2		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T173	1		T119	8		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14022	1			T3	5		T7	180		T9	288
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T138	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T275	6		T277	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T267	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T29	14		T206	10		T157	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T136	4		T209	12		T147	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	869	1			T143	32		T159	9		T94	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	1		T90	18		T214	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T8	16		T11	14		T29	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	1		T174	11		T216	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T139	27		T126	4		T153	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T3	1		T124	8		T222	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T16	2		T216	12		T63	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T148	2		T150	16		T80	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T278	1		T279	6		T280	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T147	15		T213	5		T250	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T208	14		T152	1		T92	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	14		T119	7		T120	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T29	10		T93	2		T128	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T144	15		T211	10		T152	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T84	5		T66	8		T18	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T173	10		T130	9		T156	28
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T10	1		T29	15		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T6	1		T209	13		T175	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T2	2		T5	1		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	2		T30	1		T136	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T8	17		T29	14		T93	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	1		T11	2		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	14		T117	1		T119	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T3	2		T6	1		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	1		T7	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T127	1		T147	16		T259	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T25	3		T264	1		T80	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	1		T119	8		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T10	1		T29	11		T93	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T9	15		T120	5		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T13	1		T84	6		T181	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T173	11		T144	16		T211	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T233	1		T14	2		T206	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T119	1		T130	10		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T261	13		T238	6		T269	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T23	7		T268	1		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T270	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T10	10		T29	11		T157	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	11		T209	13		T227	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T5	14		T21	34		T281	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	1		T30	7		T205	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T29	11		T117	13		T207	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	6		T30	10		T90	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	10		T119	7		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	1		T6	13		T165	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T30	18		T161	9		T123	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T127	12		T251	11		T150	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T264	14		T172	8		T242	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T119	3		T125	7		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T10	11		T29	10		T123	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T9	4		T123	19		T153	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T250	8		T282	2		T269	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T144	16		T211	10		T125	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T128	10		T18	3		T204	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T119	7		T138	12		T161	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T261	13		T269	12		T283	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T168	17		T284	2		T285	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T3	2		T7	3		T9	19
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T138	3		T273	1		T274	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T266	1		T275	7		T276	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T69	1		T267	14		T270	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T10	1		T29	15		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T136	5		T132	1		T209	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T2	2		T5	1		T21	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	1		T12	2		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T8	17		T9	1		T11	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	1		T11	2		T174	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T117	1		T139	29		T126	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	2		T6	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T1	1		T7	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T259	1		T246	1		T148	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T25	3		T161	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T1	1		T122	1		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	1		T208	15		T152	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	15		T119	8		T120	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T29	11		T93	3		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T144	16		T211	11		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T233	1		T14	2		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T173	11		T119	1		T130	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14123	1			T3	5		T7	180		T9	288
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T138	12		T273	2		T274	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T275	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T267	11		T224	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	10		T29	11		T157	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T209	13		T227	9		T254	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T5	14		T21	34		T126	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	11		T12	1		T30	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	10		T29	11		T117	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T6	6		T174	11		T142	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T126	7		T153	12		T220	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	1		T6	13		T30	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T30	18		T123	4		T140	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T246	16		T150	19		T267	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T161	9		T278	9		T280	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T125	7		T127	12		T250	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T10	11		T208	6		T175	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	4		T119	3		T123	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T29	10		T123	13		T140	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T144	16		T211	10		T125	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T18	3		T261	13		T282	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T119	7		T161	15		T156	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

auto[0]

3962

1

T3

1

T5

14

T6

30