Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22980

1

T1

2

T2

2

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19327

1

T1

1

T2

2

T3

7

auto[ADC_CTRL_FILTER_COND_OUT]

3653

1

T1

1

T3

3

T6

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17445

1

T1

1

T3

7

T7

183

auto[1]

5535

1

T1

1

T2

2

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19269

1

T1

2

T2

2

T3

9

auto[1]

3711

1

T3

1

T8

16

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	5	1			T23	1		T274	4		-	-
values[0]	40	1			T209	26		T286	3		T285	10
values[1]	467	1			T6	14		T30	19		T165	9
values[2]	595	1			T29	25		T137	1		T207	1
values[3]	726	1			T6	7		T7	1		T10	12
values[4]	931	1			T11	26		T117	1		T120	5
values[5]	512	1			T1	1		T9	1		T93	3
values[6]	690	1			T1	1		T8	17		T9	19
values[7]	636	1			T10	11		T12	3		T29	26
values[8]	436	1			T3	3		T6	12		T30	19
values[9]	3514	1			T2	2		T5	15		T11	2
minimum	14428	1			T3	7		T7	183		T9	307

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	686	1			T6	14		T29	25		T165	9
values[1]	631	1			T30	19		T139	15		T207	1
values[2]	819	1			T6	7		T7	1		T10	12
values[3]	719	1			T11	24		T138	15		T139	14
values[4]	574	1			T9	1		T93	3		T136	5
values[5]	739	1			T1	2		T8	17		T9	19
values[6]	2731	1			T2	2		T5	15		T6	12
values[7]	470	1			T3	3		T30	19		T205	13
values[8]	957	1			T130	10		T132	1		T13	1
values[9]	223	1			T11	2		T93	15		T117	29
minimum	14431	1			T3	7		T7	183		T9	307

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

3962

1

T3

1

T5

14

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	14		T122	1		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T29	12		T165	9		T144	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T30	11		T152	13		T92	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T30	8		T139	1		T207	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	1		T117	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T6	7		T10	12		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	11		T138	13		T126	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T139	1		T90	18		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T93	1		T120	1		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T9	1		T136	1		T124	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	1		T9	5		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T1	1		T8	1		T10	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1529	1			T2	2		T5	15		T12	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	12		T126	23		T127	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T30	19		T233	1		T127	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	2		T205	13		T206	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T130	1		T132	1		T123	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T13	1		T161	8		T208	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T11	1		T117	14		T119	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T93	1		T122	1		T87	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T273	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T156	12		T209	12		T92	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T29	13		T144	15		T129	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T152	8		T92	9		T222	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T139	14		T206	10		T152	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T126	11		T27	1		T210	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T11	1		T153	12		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	13		T138	2		T126	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T139	13		T90	18		T256	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T93	2		T120	4		T141	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T136	4		T124	8		T128	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T9	14		T29	10		T149	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	16		T29	14		T173	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T12	1		T143	32		T159	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T126	5		T84	5		T147	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T153	5		T147	4		T213	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T3	1		T206	6		T152	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T130	9		T211	10		T156	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T208	14		T26	2		T220	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T11	1		T117	15		T119	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T93	14		T163	9		T248	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T274	4		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T23	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T209	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T286	2		T285	10		T287	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T6	14		T30	11		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T30	8		T165	9		T144	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T137	1		T126	15		T92	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T29	12		T207	1		T84	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	1		T140	9		T152	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T6	7		T10	12		T161	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	11		T117	1		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T11	1		T139	1		T153	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	1		T93	1		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T9	1		T136	1		T124	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	5		T29	11		T119	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	1		T8	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	2		T93	1		T119	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T10	11		T29	12		T205	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T30	19		T233	1		T127	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	2		T6	12		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1718	1			T2	2		T5	15		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	420	1			T93	1		T122	1		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T209	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T286	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T156	12		T92	3		T219	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T144	15		T152	1		T129	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T126	11		T92	9		T288	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T29	13		T90	15		T92	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T152	8		T27	1		T216	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T139	14		T206	10		T174	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	13		T120	4		T138	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T11	1		T139	13		T153	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T93	2		T141	3		T214	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T136	4		T124	8		T128	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	14		T29	10		T157	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	16		T173	10		T156	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	1		T93	11		T119	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T29	14		T126	5		T84	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T147	4		T23	11		T148	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T3	1		T152	1		T181	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T11	1		T143	32		T159	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T93	14		T208	14		T26	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T6	1		T122	1		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T29	14		T165	1		T144	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T30	1		T152	9		T92	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T30	1		T139	15		T207	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	1		T117	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T6	1		T10	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	14		T138	3		T126	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T139	14		T90	19		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T93	3		T120	5		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T9	1		T136	5		T124	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	1		T9	15		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	1		T8	17		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T2	2		T5	1		T12	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	1		T126	6		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T30	1		T233	1		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	2		T205	1		T206	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T130	10		T132	1		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T13	1		T161	1		T208	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T11	2		T117	16		T119	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T93	15		T122	1		T87	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T273	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	13		T156	13		T209	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T29	11		T165	8		T144	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T30	10		T152	12		T222	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T30	7		T210	15		T63	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T140	8		T126	14		T27	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T6	6		T10	11		T161	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	10		T138	12		T126	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T90	17		T256	1		T254	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T161	9		T123	32		T207	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T124	8		T128	4		T179	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T9	4		T29	10		T119	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	10		T29	11		T156	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T5	14		T12	1		T21	34
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	11		T126	22		T127	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T30	18		T127	9		T153	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	1		T205	12		T43	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T123	4		T140	10		T211	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T161	7		T208	6		T26	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T117	13		T119	3		T254	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T163	9		T248	9		T289	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T273	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T274	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T23	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T209	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T286	2		T285	1		T287	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T6	1		T30	1		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T30	1		T165	1		T144	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T137	1		T126	12		T92	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T29	14		T207	1		T84	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	1		T140	1		T152	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	1		T10	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T11	14		T117	1		T120	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T11	2		T139	14		T153	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	1		T93	3		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	1		T136	5		T124	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	15		T29	11		T119	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	1		T8	17		T173	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	2		T93	12		T119	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	1		T29	15		T205	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T30	1		T233	1		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	2		T6	1		T152	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T2	2		T5	1		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	406	1			T93	15		T122	1		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T274	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T209	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T286	1		T285	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	13		T30	10		T156	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T30	7		T165	8		T144	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T126	14		T269	12		T288	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T29	11		T90	9		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T140	8		T152	12		T27	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	6		T10	11		T161	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	10		T138	12		T126	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T153	12		T90	17		T181	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T161	9		T123	19		T125	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T124	8		T128	4		T179	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	4		T29	10		T119	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T156	12		T252	8		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T12	1		T119	7		T140	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	10		T29	11		T205	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T30	18		T127	9		T23	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T3	1		T6	11		T142	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T5	14		T21	34		T117	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T161	7		T208	6		T26	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

auto[0]

3962

1

T3

1

T5

14

T6

30