Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22980

1

T1

2

T2

2

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19821

1

T2

2

T3

7

T5

15

auto[ADC_CTRL_FILTER_COND_OUT]

3159

1

T1

2

T3

3

T6

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17365

1

T1

2

T3

7

T6

7

auto[1]

5615

1

T2

2

T3

3

T5

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19269

1

T1

2

T2

2

T3

9

auto[1]

3711

1

T3

1

T8

16

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	34	1			T250	20		T43	5		T274	9
values[0]	86	1			T9	19		T119	8		T210	9
values[1]	492	1			T12	3		T119	18		T137	1
values[2]	868	1			T6	14		T11	4		T30	19
values[3]	611	1			T10	12		T136	5		T139	14
values[4]	599	1			T1	1		T165	9		T122	2
values[5]	2851	1			T2	2		T5	15		T9	1
values[6]	681	1			T10	11		T93	15		T120	5
values[7]	567	1			T1	1		T29	21		T117	29
values[8]	659	1			T3	3		T6	7		T7	1
values[9]	1104	1			T6	12		T8	17		T29	51
minimum	14428	1			T3	7		T7	183		T9	307

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	853	1			T6	14		T9	19		T12	3
values[1]	835	1			T10	12		T11	4		T30	19
values[2]	538	1			T136	5		T139	14		T26	6
values[3]	2785	1			T1	1		T2	2		T5	15
values[4]	730	1			T9	1		T11	24		T120	5
values[5]	587	1			T10	11		T93	15		T138	15
values[6]	633	1			T1	1		T29	21		T117	29
values[7]	663	1			T3	3		T6	7		T7	1
values[8]	796	1			T6	12		T8	17		T29	51
values[9]	132	1			T30	8		T126	12		T156	26
minimum	14428	1			T3	7		T7	183		T9	307

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

3962

1

T3

1

T5

14

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T119	8		T137	1		T25	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	14		T9	5		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T11	1		T161	26		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T10	12		T11	1		T30	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T206	1		T84	1		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T136	1		T139	1		T26	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T2	2		T5	15		T21	37
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	1		T122	1		T126	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T9	1		T120	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T11	11		T205	13		T123	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T93	1		T141	2		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T10	11		T138	13		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T156	1		T128	16		T90	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	1		T29	11		T117	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	7		T7	1		T264	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	2		T30	11		T144	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	12		T29	24		T93	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T8	1		T173	1		T121	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T30	8		T126	8		T214	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T156	13		T152	1		T212	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T119	10		T209	12		T157	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	14		T12	1		T90	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	1		T244	14		T67	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	1		T93	11		T211	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T206	10		T84	5		T149	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T136	4		T139	13		T26	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	913	1			T143	32		T159	9		T94	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T126	11		T67	4		T254	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T120	4		T130	9		T206	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	13		T208	14		T92	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T93	14		T141	3		T147	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T138	2		T290	1		T261	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T156	15		T128	19		T90	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T29	10		T117	15		T152	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T63	4		T219	14		T260	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	1		T144	15		T27	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T29	27		T93	2		T119	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T8	16		T173	10		T156	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T126	4		T214	5		T231	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T156	13		T152	1		T212	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T43	4		T274	9		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T250	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T210	5		T291	1		T292	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T9	5		T119	8		T68	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T119	8		T137	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	2		T87	1		T175	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T11	1		T25	3		T161	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	14		T11	1		T30	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T206	1		T84	1		T241	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T10	12		T136	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T165	9		T122	1		T126	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	1		T122	1		T140	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T2	2		T5	15		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	11		T123	5		T127	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T93	1		T120	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T10	11		T138	13		T205	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T128	16		T90	18		T142	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T1	1		T29	11		T117	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	7		T7	1		T125	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	2		T30	11		T144	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T6	12		T29	24		T30	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T8	1		T173	1		T121	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T43	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T250	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T210	4		T292	10		T293	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T9	14		T68	10		T294	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T119	10		T181	5		T149	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T12	1		T250	2		T295	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	1		T209	12		T157	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	1		T93	11		T152	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T206	10		T84	5		T149	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T136	4		T139	13		T211	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T126	5		T153	5		T213	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T126	11		T67	4		T296	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T143	32		T159	9		T94	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	13		T92	9		T175	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T93	14		T120	4		T130	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T138	2		T208	14		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T128	19		T90	18		T23	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T29	10		T117	15		T210	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T156	15		T63	4		T219	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	1		T144	15		T152	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T29	27		T93	2		T119	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T8	16		T173	10		T156	25
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T119	11		T137	1		T25	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T6	1		T9	15		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	2		T161	2		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	1		T11	2		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T206	11		T84	6		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T136	5		T139	14		T26	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T2	2		T5	1		T21	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T122	1		T126	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T9	1		T120	5		T130	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	14		T205	1		T123	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T93	15		T141	4		T147	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T10	1		T138	3		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T156	16		T128	21		T90	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T1	1		T29	11		T117	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T6	1		T7	1		T264	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	2		T30	1		T144	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	1		T29	29		T93	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T8	17		T173	11		T121	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T30	1		T126	5		T214	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T156	14		T152	2		T212	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T119	7		T140	2		T125	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	13		T9	4		T12	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T161	24		T244	17		T223	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T10	11		T30	18		T207	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T15	1		T149	4		T255	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T26	2		T246	7		T220	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T5	14		T21	34		T165	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T126	14		T254	1		T18	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T161	7		T140	8		T153	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	10		T205	12		T123	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T141	1		T142	1		T219	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T10	10		T138	12		T220	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T128	14		T90	17		T245	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T29	10		T117	13		T152	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	6		T264	14		T63	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	1		T30	10		T144	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	11		T29	22		T119	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T156	13		T129	6		T179	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T30	7		T126	7		T214	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T156	12		T212	2		T297	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T43	4		T274	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T250	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T210	5		T291	1		T292	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T9	15		T119	1		T68	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T119	11		T137	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T12	2		T87	1		T175	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	2		T25	3		T161	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	1		T11	2		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T206	11		T84	6		T241	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T10	1		T136	5		T139	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T165	1		T122	1		T126	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	1		T122	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T2	2		T5	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	14		T123	1		T127	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T93	15		T120	5		T130	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	1		T138	3		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T128	21		T90	19		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T1	1		T29	11		T117	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	1		T7	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	2		T30	1		T144	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T6	1		T29	29		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	386	1			T8	17		T173	11		T121	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T43	1		T274	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T250	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T210	4		T298	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T9	4		T119	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T119	7		T181	5		T246	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T12	1		T250	15		T295	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T161	24		T140	2		T125	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	13		T30	18		T207	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T223	7		T149	4		T255	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T10	11		T211	10		T26	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T165	8		T126	22		T127	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T140	10		T126	14		T296	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T5	14		T21	34		T140	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	10		T123	4		T127	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T161	7		T141	1		T222	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	10		T138	12		T205	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T128	14		T90	17		T142	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T29	10		T117	13		T252	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	6		T125	7		T264	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	1		T30	10		T144	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	11		T29	22		T30	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T156	25		T129	6		T179	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

auto[0]

3962

1

T3

1

T5

14

T6

30