Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22980

1

T1

2

T2

2

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19614

1

T1

1

T2

2

T3

7

auto[ADC_CTRL_FILTER_COND_OUT]

3366

1

T1

1

T3

3

T8

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17223

1

T1

1

T3

7

T6

7

auto[1]

5757

1

T1

1

T2

2

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19269

1

T1

2

T2

2

T3

9

auto[1]

3711

1

T3

1

T8

16

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T299	2		T300	11		-	-
values[0]	29	1			T30	11		T140	3		T207	1
values[1]	459	1			T173	11		T136	5		T122	1
values[2]	2801	1			T2	2		T5	15		T10	11
values[3]	669	1			T3	3		T10	12		T29	46
values[4]	587	1			T6	7		T9	19		T12	3
values[5]	686	1			T8	17		T11	2		T30	8
values[6]	629	1			T119	18		T121	1		T211	21
values[7]	721	1			T93	15		T119	19		T122	1
values[8]	721	1			T7	1		T117	29		T146	1
values[9]	1237	1			T1	2		T6	26		T9	1
minimum	14428	1			T3	7		T7	183		T9	307

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	633	1			T11	24		T30	11		T173	11
values[1]	2788	1			T2	2		T3	3		T5	15
values[2]	648	1			T10	12		T12	3		T130	10
values[3]	684	1			T6	7		T9	19		T11	2
values[4]	689	1			T8	17		T165	9		T119	18
values[5]	600	1			T119	11		T121	1		T13	1
values[6]	675	1			T7	1		T93	15		T117	29
values[7]	733	1			T30	19		T124	17		T146	1
values[8]	914	1			T1	2		T6	12		T9	1
values[9]	170	1			T6	14		T215	32		T301	4
minimum	14446	1			T3	7		T7	183		T9	307

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

3962

1

T3

1

T5

14

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	11		T173	1		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T30	11		T137	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1538	1			T2	2		T5	15		T21	37
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	2		T10	11		T29	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	12		T130	1		T123	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	2		T138	13		T207	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	7		T9	5		T29	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	1		T30	8		T156	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T165	9		T137	1		T205	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	1		T119	8		T128	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T119	4		T211	11		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T121	1		T13	1		T161	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	1		T119	8		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T93	1		T117	14		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T30	19		T209	14		T92	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T124	9		T146	1		T128	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T1	1		T6	12		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	1		T93	1		T161	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T6	14		T155	3		T234	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T215	18		T301	4		T172	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14328	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T302	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	13		T173	10		T136	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T139	14		T141	3		T63	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	867	1			T29	10		T143	32		T159	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	1		T29	14		T139	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T130	9		T126	4		T181	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T12	1		T138	2		T156	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	14		T29	13		T208	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	1		T156	13		T214	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T241	9		T148	2		T219	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	16		T119	10		T128	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T119	7		T211	10		T92	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T156	15		T152	1		T219	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T174	11		T175	11		T147	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T93	14		T117	15		T144	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T209	12		T92	9		T147	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T124	8		T128	9		T181	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	1		T93	2		T126	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T93	11		T23	6		T67	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T234	11		T303	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T215	14		T172	11		T248	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T13	3		T25	2		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T302	15		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T299	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T300	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T207	1		T67	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T30	11		T140	3		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T173	1		T136	1		T84	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T122	1		T137	1		T141	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1511	1			T2	2		T5	15		T11	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T10	11		T29	12		T139	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	12		T29	23		T125	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T3	2		T132	1		T138	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	7		T9	5		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	2		T156	13		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T165	9		T153	8		T92	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T8	1		T11	1		T30	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T211	11		T127	1		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T119	8		T121	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T119	12		T174	1		T175	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T93	1		T122	1		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T7	1		T209	14		T92	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T117	14		T146	1		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	374	1			T1	1		T6	26		T9	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T1	1		T93	1		T161	24
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T299	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T300	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T67	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T170	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T173	10		T136	4		T84	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T141	3		T157	12		T63	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T11	13		T143	32		T159	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T29	14		T139	27		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T29	23		T181	5		T227	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	1		T138	2		T156	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T9	14		T130	9		T208	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	1		T156	13		T22	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T153	5		T92	9		T256	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	16		T11	1		T128	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T211	10		T241	9		T250	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T119	10		T152	1		T213	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T119	7		T174	11		T175	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T93	14		T144	15		T124	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T209	12		T92	9		T80	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T117	15		T181	5		T244	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T11	1		T93	2		T126	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T93	11		T128	9		T23	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	14		T173	11		T136	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T30	1		T137	1		T139	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T2	2		T5	1		T21	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	2		T10	1		T29	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T10	1		T130	10		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	2		T138	3		T207	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	1		T9	15		T29	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T11	2		T30	1		T156	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T165	1		T137	1		T205	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T8	17		T119	11		T128	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T119	8		T211	11		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T121	1		T13	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	1		T119	1		T174	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T93	15		T117	16		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T30	1		T209	13		T92	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T124	9		T146	1		T128	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T1	1		T6	1		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	1		T93	12		T161	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T6	1		T155	1		T234	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T215	15		T301	4		T172	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14430	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T302	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T11	10		T63	2		T254	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T30	10		T140	2		T141	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T5	14		T21	34		T29	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	1		T10	10		T29	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	11		T123	13		T126	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	1		T138	12		T207	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T6	6		T9	4		T29	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T30	7		T156	12		T214	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T165	8		T205	12		T241	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T119	7		T128	10		T174	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T119	3		T211	10		T252	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T161	9		T140	10		T252	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T119	7		T175	10		T214	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T117	13		T144	16		T123	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T30	18		T209	13		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T124	8		T128	4		T181	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T6	11		T126	22		T152	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T161	22		T140	8		T304	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T6	13		T155	2		T234	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T215	17		T172	12		T248	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T299	2		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T300	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T207	1		T67	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T30	1		T140	1		T170	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T173	11		T136	5		T84	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T122	1		T137	1		T141	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T2	2		T5	1		T11	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	1		T29	15		T139	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T10	1		T29	25		T125	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	2		T132	1		T138	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	1		T9	15		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	2		T156	14		T22	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T165	1		T153	6		T92	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T8	17		T11	2		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T211	11		T127	1		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T119	11		T121	1		T152	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T119	9		T174	12		T175	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T93	15		T122	1		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	1		T209	13		T92	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T117	16		T146	1		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	363	1			T1	1		T6	2		T9	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T1	1		T93	12		T161	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T30	10		T140	2		T203	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T63	2		T149	2		T265	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T141	1		T157	11		T63	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T5	14		T11	10		T21	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	10		T29	11		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	11		T29	21		T125	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	1		T138	12		T207	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	6		T9	4		T205	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T12	1		T156	12		T250	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T165	8		T153	7		T256	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T30	7		T128	10		T174	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T211	10		T241	13		T252	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T119	7		T252	8		T219	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T119	10		T175	10		T214	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T161	9		T144	16		T123	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T209	13		T15	1		T246	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T117	13		T179	2		T181	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T6	24		T30	18		T126	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T161	22		T140	8		T128	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

auto[0]

3962

1

T3

1

T5

14

T6

30