Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22980

1

T1

2

T2

2

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19380

1

T2

2

T3

7

T5

15

auto[ADC_CTRL_FILTER_COND_OUT]

3600

1

T1

2

T3

3

T6

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17578

1

T1

1

T3

7

T6

14

auto[1]

5402

1

T1

1

T2

2

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19269

1

T1

2

T2

2

T3

9

auto[1]

3711

1

T3

1

T8

16

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	248	1			T93	15		T119	11		T13	1
values[0]	21	1			T258	21		-	-		-	-
values[1]	474	1			T6	14		T30	11		T165	9
values[2]	575	1			T29	25		T30	8		T139	15
values[3]	838	1			T6	7		T7	1		T10	12
values[4]	875	1			T11	24		T120	5		T138	15
values[5]	454	1			T1	1		T9	1		T93	3
values[6]	733	1			T1	1		T8	17		T9	19
values[7]	682	1			T6	12		T10	11		T12	3
values[8]	451	1			T3	3		T30	19		T233	1
values[9]	3201	1			T2	2		T5	15		T11	2
minimum	14428	1			T3	7		T7	183		T9	307

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	496	1			T6	14		T29	25		T122	1
values[1]	646	1			T30	19		T139	15		T207	1
values[2]	826	1			T6	7		T7	1		T10	12
values[3]	733	1			T11	24		T120	5		T138	15
values[4]	577	1			T1	1		T9	1		T93	3
values[5]	715	1			T1	1		T8	17		T9	19
values[6]	2728	1			T2	2		T5	15		T6	12
values[7]	549	1			T3	3		T30	19		T205	13
values[8]	985	1			T11	2		T117	29		T130	10
values[9]	131	1			T93	15		T119	11		T174	1
minimum	14594	1			T3	7		T7	183		T9	307

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

3962

1

T3

1

T5

14

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T122	1		T137	1		T156	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	14		T29	12		T144	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T126	15		T152	13		T268	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	19		T139	1		T207	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	1		T117	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T6	7		T10	12		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T120	1		T138	13		T126	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	11		T139	1		T90	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T93	1		T121	1		T161	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	1		T9	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	5		T10	11		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	1		T8	1		T29	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1525	1			T2	2		T5	15		T12	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	12		T126	23		T84	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T30	19		T233	1		T127	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	2		T205	13		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T11	1		T130	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T117	14		T122	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T119	4		T174	1		T254	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T93	1		T23	1		T163	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14372	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T165	9		T169	1		T305	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T156	12		T92	3		T67	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T29	13		T144	15		T129	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T126	11		T152	8		T222	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T139	14		T206	10		T152	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T27	1		T210	4		T245	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T11	1		T153	12		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T120	4		T138	2		T126	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	13		T139	13		T90	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T93	2		T141	3		T128	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T136	4		T124	8		T128	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	14		T29	10		T173	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	16		T29	14		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	916	1			T12	1		T143	32		T159	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T126	5		T84	5		T241	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T153	5		T181	5		T213	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T3	1		T152	1		T147	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	1		T130	9		T211	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T117	15		T208	14		T26	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T119	7		T254	3		T237	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T93	14		T163	9		T248	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T13	3		T25	2		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T305	6		T258	10		T306	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T119	4		T174	1		T259	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T93	1		T13	1		T161	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T258	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T122	1		T137	1		T156	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T6	14		T30	11		T165	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T126	15		T219	15		T268	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T29	12		T30	8		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	1		T117	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T6	7		T10	12		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T120	1		T138	13		T126	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T11	11		T139	1		T90	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T93	1		T121	1		T161	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T1	1		T9	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T9	5		T29	11		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	1		T8	1		T25	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T10	11		T12	2		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T6	12		T29	12		T205	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T30	19		T233	1		T127	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T3	2		T152	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1659	1			T2	2		T5	15		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T117	14		T122	1		T208	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T119	7		T66	8		T254	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T93	14		T26	2		T217	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T258	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T156	12		T209	12		T92	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T144	15		T152	1		T129	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T126	11		T219	14		T278	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T29	13		T139	14		T90	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T152	8		T27	1		T255	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T11	1		T206	10		T153	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T120	4		T138	2		T126	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T11	13		T139	13		T90	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T93	2		T141	3		T214	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T136	4		T124	8		T128	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	14		T29	10		T173	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	16		T156	13		T150	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	1		T93	11		T119	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	14		T126	5		T84	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T181	5		T23	11		T148	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T3	1		T152	1		T147	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T11	1		T143	32		T159	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T117	15		T208	14		T206	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T122	1		T137	1		T156	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	1		T29	14		T144	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T126	12		T152	9		T268	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T30	2		T139	15		T207	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	1		T117	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T6	1		T10	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T120	5		T138	3		T126	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T11	14		T139	14		T90	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T93	3		T121	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	1		T9	1		T136	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	15		T10	1		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	1		T8	17		T29	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T2	2		T5	1		T12	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	1		T126	6		T84	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T30	1		T233	1		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	2		T205	1		T152	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T11	2		T130	10		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T117	16		T122	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T119	8		T174	1		T254	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T93	15		T23	1		T163	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14455	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T165	1		T169	1		T305	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T156	13		T219	14		T225	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T6	13		T29	11		T144	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T126	14		T152	12		T222	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T30	17		T210	15		T63	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T140	8		T27	1		T210	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T6	6		T10	11		T161	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T138	12		T126	7		T214	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	10		T90	17		T256	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T161	9		T123	32		T207	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T124	8		T128	4		T179	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T9	4		T10	10		T29	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T29	11		T156	12		T127	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T5	14		T12	1		T21	34
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T6	11		T126	22		T241	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T30	18		T127	9		T153	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	1		T205	12		T20	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T123	4		T140	10		T211	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T117	13		T161	7		T208	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T119	3		T254	2		T237	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T163	9		T284	2		T248	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T209	13		T307	10		T248	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T165	8		T308	13		T309	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T119	8		T174	1		T259	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T93	15		T13	1		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T258	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T122	1		T137	1		T156	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T6	1		T30	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T126	12		T219	15		T268	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T29	14		T30	1		T139	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	1		T117	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T6	1		T10	1		T11	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T120	5		T138	3		T126	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T11	14		T139	14		T90	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T93	3		T121	1		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	1		T9	1		T136	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	15		T29	11		T173	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	1		T8	17		T25	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T10	1		T12	2		T93	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	1		T29	15		T205	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T30	1		T233	1		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	2		T152	2		T147	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T2	2		T5	1		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T117	16		T122	1		T208	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T119	3		T246	16		T254	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T161	7		T26	2		T217	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T258	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T156	13		T209	13		T310	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	13		T30	10		T165	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T126	14		T219	14		T225	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T29	11		T30	7		T90	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T140	8		T152	12		T27	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T6	6		T10	11		T161	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T138	12		T126	7		T210	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	10		T90	17		T246	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T161	9		T123	19		T125	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T124	8		T128	4		T179	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	4		T29	10		T119	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T156	12		T252	8		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T10	10		T12	1		T119	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	11		T29	11		T205	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T30	18		T127	9		T23	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T3	1		T142	1		T20	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T5	14		T21	34		T123	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T117	13		T208	6		T252	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

auto[0]

3962

1

T3

1

T5

14

T6

30