Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22980

1

T1

2

T2

2

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19691

1

T1

1

T2

2

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3289

1

T1

1

T6

33

T7

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17288

1

T3

10

T6

19

T7

184

auto[1]

5692

1

T1

2

T2

2

T5

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19269

1

T1

2

T2

2

T3

9

auto[1]

3711

1

T3

1

T8

16

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	201	1			T119	11		T205	13		T140	9
values[0]	28	1			T168	28		-	-		-	-
values[1]	495	1			T1	1		T8	17		T9	19
values[2]	580	1			T11	24		T12	3		T93	15
values[3]	646	1			T7	1		T9	1		T11	2
values[4]	2866	1			T2	2		T5	15		T21	37
values[5]	602	1			T10	12		T119	18		T122	1
values[6]	743	1			T29	21		T30	19		T93	12
values[7]	729	1			T1	1		T11	2		T122	1
values[8]	702	1			T6	19		T161	16		T123	5
values[9]	960	1			T3	3		T6	14		T30	19
minimum	14428	1			T3	7		T7	183		T9	307

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	456	1			T1	1		T8	17		T11	24
values[1]	662	1			T9	1		T12	3		T93	15
values[2]	568	1			T7	1		T11	2		T29	51
values[3]	2864	1			T2	2		T5	15		T21	37
values[4]	704	1			T10	12		T29	21		T30	8
values[5]	623	1			T30	11		T93	12		T119	8
values[6]	743	1			T1	1		T11	2		T25	3
values[7]	693	1			T6	19		T120	5		T123	5
values[8]	987	1			T3	3		T6	14		T30	19
values[9]	45	1			T216	13		T69	1		T311	1
minimum	14635	1			T3	7		T7	183		T9	326

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

3962

1

T3

1

T5

14

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T1	1		T8	1		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	11		T165	9		T125	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T9	1		T12	2		T93	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T152	13		T175	11		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T29	12		T139	1		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	1		T11	1		T29	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1615	1			T2	2		T5	15		T21	37
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T173	1		T130	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T30	8		T122	1		T138	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	12		T29	11		T119	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T30	11		T209	14		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T93	1		T119	8		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T25	3		T126	8		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	1		T11	1		T161	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T120	1		T123	5		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	19		T140	3		T214	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T3	2		T119	4		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T6	14		T30	19		T93	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T216	1		T311	1		T312	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T69	1		T224	3		T299	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14363	1			T3	7		T7	183		T9	312
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T10	11		T13	1		T128	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T8	16		T148	2		T260	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	13		T153	12		T84	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	1		T93	14		T144	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T152	8		T175	11		T147	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T29	14		T139	13		T210	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	1		T29	13		T157	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T143	32		T159	9		T94	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T173	10		T130	9		T126	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T138	2		T208	14		T211	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T29	10		T119	10		T156	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T209	12		T22	7		T212	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T93	11		T92	9		T254	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T126	4		T27	1		T213	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	1		T139	14		T124	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T120	4		T152	2		T147	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T214	14		T215	14		T255	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	1		T119	7		T136	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T93	2		T26	2		T206	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T216	12		T313	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T299	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	14		T13	3		T25	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T128	10		T262	10		T168	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T119	4		T205	13		T140	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T127	10		T90	10		T314	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T168	18		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T1	1		T8	1		T9	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	11		T165	9		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T12	2		T93	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	11		T152	13		T175	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	1		T174	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	1		T11	1		T29	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1648	1			T2	2		T5	15		T21	37
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T173	1		T130	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T122	1		T137	1		T138	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	12		T119	8		T126	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T30	19		T209	14		T90	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T29	11		T93	1		T119	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T25	3		T146	1		T27	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	1		T11	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T123	5		T126	8		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	19		T161	16		T140	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T3	2		T136	1		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T6	14		T30	19		T93	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T119	7		T181	5		T216	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T90	15		T314	1		T299	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T168	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T8	16		T9	14		T148	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T153	12		T128	10		T84	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T12	1		T93	14		T144	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	13		T152	8		T175	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T210	4		T216	7		T63	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	1		T29	13		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T29	14		T143	32		T159	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T173	10		T130	9		T153	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T138	2		T208	14		T211	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T119	10		T126	5		T156	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T209	12		T90	18		T22	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T29	10		T93	11		T128	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T27	1		T213	5		T212	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	1		T139	14		T124	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T126	4		T152	1		T147	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T126	11		T174	11		T214	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	1		T136	4		T120	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T93	2		T26	2		T206	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T1	1		T8	17		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	14		T165	1		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	1		T12	2		T93	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T152	9		T175	12		T147	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T29	15		T139	14		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	1		T11	2		T29	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T2	2		T5	1		T21	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T173	11		T130	10		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T30	1		T122	1		T138	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	1		T29	11		T119	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T30	1		T209	13		T22	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T93	12		T119	1		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T25	3		T126	5		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	1		T11	2		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T120	5		T123	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	2		T140	1		T214	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T3	2		T119	8		T136	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	1		T30	1		T93	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T216	13		T311	1		T312	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T69	1		T224	1		T299	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14484	1			T3	7		T7	183		T9	322
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T10	1		T13	1		T128	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T161	9		T204	9		T315	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	10		T165	8		T125	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T12	1		T144	16		T141	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T152	12		T175	10		T219	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T29	11		T210	4		T255	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T29	11		T157	11		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T5	14		T21	34		T117	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T126	22		T153	7		T220	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T30	7		T138	12		T208	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T10	11		T29	10		T119	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T30	10		T209	13		T220	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T119	7		T161	7		T123	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T126	7		T27	1		T222	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T161	15		T140	10		T124	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T123	4		T179	2		T214	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	17		T140	2		T214	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	1		T119	3		T205	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	13		T30	18		T123	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T312	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T224	2		T316	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T9	4		T63	2		T219	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T10	10		T128	10		T263	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T119	8		T205	1		T140	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T127	1		T90	16		T314	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T168	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T1	1		T8	17		T9	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	1		T165	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	2		T93	15		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T11	14		T152	9		T175	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	1		T174	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	1		T11	2		T29	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T2	2		T5	1		T21	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T173	11		T130	10		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T122	1		T137	1		T138	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	1		T119	11		T126	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T30	2		T209	13		T90	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T29	11		T93	12		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T25	3		T146	1		T27	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T11	2		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T123	1		T126	5		T152	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	2		T161	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	2		T136	5		T120	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	1		T30	1		T93	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T119	3		T205	12		T140	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T127	9		T90	9		T224	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T168	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T9	4		T63	2		T219	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T10	10		T165	8		T125	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T12	1		T161	9		T144	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	10		T152	12		T175	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T210	4		T63	6		T261	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T29	11		T157	11		T174	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T5	14		T21	34		T29	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T153	7		T220	2		T225	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T138	12		T208	6		T211	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T10	11		T119	7		T126	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T30	17		T209	13		T90	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	10		T119	7		T161	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T27	1		T212	2		T176	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T123	13		T124	8		T125	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T123	4		T126	7		T179	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	17		T161	15		T140	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	1		T247	10		T241	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	13		T30	18		T123	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

auto[0]

3962

1

T3

1

T5

14

T6

30