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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.07 96.67 100.00 100.00 98.83 98.33 91.34


Total test records in report: 920
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T796 /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2169679191 Aug 19 05:54:53 PM PDT 24 Aug 19 05:56:34 PM PDT 24 165224307529 ps
T797 /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1634288772 Aug 19 05:55:18 PM PDT 24 Aug 19 06:17:13 PM PDT 24 591489369974 ps
T798 /workspace/coverage/default/17.adc_ctrl_lowpower_counter.54314241 Aug 19 05:55:22 PM PDT 24 Aug 19 05:55:33 PM PDT 24 39676583668 ps
T799 /workspace/coverage/default/41.adc_ctrl_smoke.419912861 Aug 19 05:56:25 PM PDT 24 Aug 19 05:56:41 PM PDT 24 5913468170 ps
T800 /workspace/coverage/default/20.adc_ctrl_stress_all.523817592 Aug 19 05:55:26 PM PDT 24 Aug 19 06:01:06 PM PDT 24 537809483058 ps
T95 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4201823555 Aug 19 05:02:44 PM PDT 24 Aug 19 05:02:46 PM PDT 24 566393901 ps
T37 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3230367643 Aug 19 05:02:55 PM PDT 24 Aug 19 05:05:28 PM PDT 24 38518757857 ps
T801 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2437444035 Aug 19 05:03:34 PM PDT 24 Aug 19 05:03:36 PM PDT 24 515124213 ps
T40 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.80520503 Aug 19 05:02:42 PM PDT 24 Aug 19 05:02:49 PM PDT 24 4614834096 ps
T47 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3912767485 Aug 19 05:02:45 PM PDT 24 Aug 19 05:02:48 PM PDT 24 382281088 ps
T802 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1774105182 Aug 19 05:03:35 PM PDT 24 Aug 19 05:03:36 PM PDT 24 413618156 ps
T803 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1141442173 Aug 19 05:02:54 PM PDT 24 Aug 19 05:02:55 PM PDT 24 317046656 ps
T804 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.360810334 Aug 19 05:03:33 PM PDT 24 Aug 19 05:03:35 PM PDT 24 432161603 ps
T805 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1408587827 Aug 19 05:02:43 PM PDT 24 Aug 19 05:02:45 PM PDT 24 488310667 ps
T806 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.266832677 Aug 19 05:02:56 PM PDT 24 Aug 19 05:02:57 PM PDT 24 461167678 ps
T106 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3879547300 Aug 19 05:02:57 PM PDT 24 Aug 19 05:03:06 PM PDT 24 2158019481 ps
T38 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1220784468 Aug 19 05:02:43 PM PDT 24 Aug 19 05:03:24 PM PDT 24 16872958161 ps
T114 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3762266832 Aug 19 05:02:46 PM PDT 24 Aug 19 05:02:48 PM PDT 24 780205537 ps
T807 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3842892310 Aug 19 05:03:37 PM PDT 24 Aug 19 05:03:38 PM PDT 24 452509739 ps
T73 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1404456954 Aug 19 05:02:47 PM PDT 24 Aug 19 05:02:49 PM PDT 24 568933930 ps
T55 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.735711918 Aug 19 05:02:45 PM PDT 24 Aug 19 05:02:46 PM PDT 24 498652713 ps
T74 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1815496890 Aug 19 05:02:54 PM PDT 24 Aug 19 05:02:55 PM PDT 24 351124083 ps
T39 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2774940731 Aug 19 05:02:53 PM PDT 24 Aug 19 05:03:49 PM PDT 24 27109469203 ps
T48 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3517144703 Aug 19 05:02:53 PM PDT 24 Aug 19 05:02:56 PM PDT 24 505142919 ps
T115 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.805952519 Aug 19 05:02:56 PM PDT 24 Aug 19 05:02:57 PM PDT 24 713360149 ps
T107 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1636650084 Aug 19 05:02:46 PM PDT 24 Aug 19 05:02:54 PM PDT 24 2539155941 ps
T54 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.78105971 Aug 19 05:03:37 PM PDT 24 Aug 19 05:03:39 PM PDT 24 478637208 ps
T49 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2751633100 Aug 19 05:02:53 PM PDT 24 Aug 19 05:02:56 PM PDT 24 353292678 ps
T96 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.811081146 Aug 19 05:03:08 PM PDT 24 Aug 19 05:03:10 PM PDT 24 482641131 ps
T50 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2558218132 Aug 19 05:02:52 PM PDT 24 Aug 19 05:02:53 PM PDT 24 468085981 ps
T808 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.626803028 Aug 19 05:03:34 PM PDT 24 Aug 19 05:03:36 PM PDT 24 526844476 ps
T97 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4258085108 Aug 19 05:03:21 PM PDT 24 Aug 19 05:03:23 PM PDT 24 484307425 ps
T108 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2442578238 Aug 19 05:03:23 PM PDT 24 Aug 19 05:03:28 PM PDT 24 4529465862 ps
T53 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1951265573 Aug 19 05:03:23 PM PDT 24 Aug 19 05:03:25 PM PDT 24 296712268 ps
T809 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3419225655 Aug 19 05:03:31 PM PDT 24 Aug 19 05:03:33 PM PDT 24 291024841 ps
T810 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3782865988 Aug 19 05:03:05 PM PDT 24 Aug 19 05:03:07 PM PDT 24 388940050 ps
T109 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3434494647 Aug 19 05:03:09 PM PDT 24 Aug 19 05:03:13 PM PDT 24 4542059712 ps
T56 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2371498466 Aug 19 05:03:22 PM PDT 24 Aug 19 05:03:25 PM PDT 24 578787956 ps
T110 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.824615708 Aug 19 05:03:07 PM PDT 24 Aug 19 05:03:16 PM PDT 24 3018480978 ps
T41 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3526829744 Aug 19 05:03:08 PM PDT 24 Aug 19 05:03:20 PM PDT 24 4804720097 ps
T42 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1692959093 Aug 19 05:03:22 PM PDT 24 Aug 19 05:03:41 PM PDT 24 8201333752 ps
T111 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1744788953 Aug 19 05:03:23 PM PDT 24 Aug 19 05:03:40 PM PDT 24 4411774562 ps
T811 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2858467421 Aug 19 05:03:03 PM PDT 24 Aug 19 05:03:05 PM PDT 24 423604568 ps
T58 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2039172484 Aug 19 05:03:04 PM PDT 24 Aug 19 05:03:07 PM PDT 24 598827533 ps
T112 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1471399595 Aug 19 05:02:54 PM PDT 24 Aug 19 05:03:03 PM PDT 24 5007753867 ps
T812 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.619499253 Aug 19 05:03:34 PM PDT 24 Aug 19 05:03:36 PM PDT 24 467585774 ps
T813 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2331783152 Aug 19 05:03:21 PM PDT 24 Aug 19 05:03:23 PM PDT 24 497995521 ps
T113 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1453097427 Aug 19 05:03:04 PM PDT 24 Aug 19 05:03:14 PM PDT 24 4204189424 ps
T814 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2650090455 Aug 19 05:03:06 PM PDT 24 Aug 19 05:03:07 PM PDT 24 444531717 ps
T815 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2364049519 Aug 19 05:03:33 PM PDT 24 Aug 19 05:03:34 PM PDT 24 502491438 ps
T816 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3879974452 Aug 19 05:02:56 PM PDT 24 Aug 19 05:02:57 PM PDT 24 306210468 ps
T817 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3239001461 Aug 19 05:03:21 PM PDT 24 Aug 19 05:03:25 PM PDT 24 2367242320 ps
T818 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.458919303 Aug 19 05:03:37 PM PDT 24 Aug 19 05:03:38 PM PDT 24 431134188 ps
T98 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1585594524 Aug 19 05:02:42 PM PDT 24 Aug 19 05:02:43 PM PDT 24 439810413 ps
T819 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.820919620 Aug 19 05:03:23 PM PDT 24 Aug 19 05:03:28 PM PDT 24 5291835308 ps
T99 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2764658913 Aug 19 05:02:57 PM PDT 24 Aug 19 05:03:00 PM PDT 24 1339710508 ps
T57 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2501922230 Aug 19 05:02:46 PM PDT 24 Aug 19 05:02:49 PM PDT 24 377257273 ps
T820 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2265956871 Aug 19 05:03:23 PM PDT 24 Aug 19 05:03:26 PM PDT 24 746798813 ps
T821 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.451393133 Aug 19 05:03:35 PM PDT 24 Aug 19 05:03:36 PM PDT 24 338814417 ps
T822 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3879202141 Aug 19 05:02:54 PM PDT 24 Aug 19 05:03:00 PM PDT 24 4954626086 ps
T823 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.48090676 Aug 19 05:03:07 PM PDT 24 Aug 19 05:03:11 PM PDT 24 4222046913 ps
T824 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3650019551 Aug 19 05:03:34 PM PDT 24 Aug 19 05:03:35 PM PDT 24 470393804 ps
T825 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2058598956 Aug 19 05:03:24 PM PDT 24 Aug 19 05:03:26 PM PDT 24 375936332 ps
T826 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2069306774 Aug 19 05:02:47 PM PDT 24 Aug 19 05:02:48 PM PDT 24 457143024 ps
T827 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3700339471 Aug 19 05:03:21 PM PDT 24 Aug 19 05:03:23 PM PDT 24 477637039 ps
T828 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.640127538 Aug 19 05:03:21 PM PDT 24 Aug 19 05:03:22 PM PDT 24 643502354 ps
T337 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1770087846 Aug 19 05:03:07 PM PDT 24 Aug 19 05:03:18 PM PDT 24 4302207530 ps
T829 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3376895517 Aug 19 05:02:54 PM PDT 24 Aug 19 05:02:55 PM PDT 24 324919054 ps
T334 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3150849332 Aug 19 05:03:07 PM PDT 24 Aug 19 05:03:18 PM PDT 24 4056897160 ps
T830 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3885888553 Aug 19 05:02:53 PM PDT 24 Aug 19 05:02:57 PM PDT 24 4166849236 ps
T831 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3371427076 Aug 19 05:03:09 PM PDT 24 Aug 19 05:03:10 PM PDT 24 313629092 ps
T832 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4003707459 Aug 19 05:03:22 PM PDT 24 Aug 19 05:03:30 PM PDT 24 2128515977 ps
T833 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3969823865 Aug 19 05:03:37 PM PDT 24 Aug 19 05:03:38 PM PDT 24 325115572 ps
T834 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2333056791 Aug 19 05:02:40 PM PDT 24 Aug 19 05:02:42 PM PDT 24 549302247 ps
T100 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3491182658 Aug 19 05:03:09 PM PDT 24 Aug 19 05:03:11 PM PDT 24 519820208 ps
T835 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4243307274 Aug 19 05:02:41 PM PDT 24 Aug 19 05:02:43 PM PDT 24 1084644689 ps
T101 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.167850452 Aug 19 05:02:44 PM PDT 24 Aug 19 05:02:45 PM PDT 24 608234655 ps
T836 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2620059923 Aug 19 05:03:07 PM PDT 24 Aug 19 05:03:23 PM PDT 24 4776446920 ps
T837 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2306134228 Aug 19 05:03:08 PM PDT 24 Aug 19 05:03:10 PM PDT 24 392340178 ps
T838 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2583745579 Aug 19 05:03:04 PM PDT 24 Aug 19 05:03:05 PM PDT 24 461892926 ps
T839 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.638637881 Aug 19 05:02:44 PM PDT 24 Aug 19 05:02:53 PM PDT 24 4679479792 ps
T840 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1062240552 Aug 19 05:03:34 PM PDT 24 Aug 19 05:03:35 PM PDT 24 479678191 ps
T841 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3023480199 Aug 19 05:02:58 PM PDT 24 Aug 19 05:03:00 PM PDT 24 576749769 ps
T335 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3285372397 Aug 19 05:02:53 PM PDT 24 Aug 19 05:03:01 PM PDT 24 4827946606 ps
T104 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2700297418 Aug 19 05:03:05 PM PDT 24 Aug 19 05:03:07 PM PDT 24 474442773 ps
T105 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2584933370 Aug 19 05:03:05 PM PDT 24 Aug 19 05:03:06 PM PDT 24 387063479 ps
T102 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.66951187 Aug 19 05:02:56 PM PDT 24 Aug 19 05:03:00 PM PDT 24 768228978 ps
T842 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1499220059 Aug 19 05:03:34 PM PDT 24 Aug 19 05:03:35 PM PDT 24 334932912 ps
T843 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2451822106 Aug 19 05:03:06 PM PDT 24 Aug 19 05:03:07 PM PDT 24 671418689 ps
T844 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2797135344 Aug 19 05:03:08 PM PDT 24 Aug 19 05:03:10 PM PDT 24 316418556 ps
T845 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3161398491 Aug 19 05:02:55 PM PDT 24 Aug 19 05:03:08 PM PDT 24 8971355438 ps
T846 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1270230668 Aug 19 05:03:34 PM PDT 24 Aug 19 05:03:35 PM PDT 24 486638331 ps
T847 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.413374431 Aug 19 05:02:54 PM PDT 24 Aug 19 05:03:04 PM PDT 24 4240012908 ps
T848 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2348697952 Aug 19 05:03:24 PM PDT 24 Aug 19 05:03:25 PM PDT 24 467276151 ps
T849 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3962242449 Aug 19 05:03:32 PM PDT 24 Aug 19 05:03:33 PM PDT 24 379507983 ps
T850 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1844099011 Aug 19 05:03:22 PM PDT 24 Aug 19 05:03:26 PM PDT 24 4312437650 ps
T851 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2919670848 Aug 19 05:02:44 PM PDT 24 Aug 19 05:02:47 PM PDT 24 3437437262 ps
T852 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2052283390 Aug 19 05:03:24 PM PDT 24 Aug 19 05:03:26 PM PDT 24 505978875 ps
T853 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.872976775 Aug 19 05:03:08 PM PDT 24 Aug 19 05:03:19 PM PDT 24 5139320562 ps
T103 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.83433087 Aug 19 05:02:55 PM PDT 24 Aug 19 05:02:56 PM PDT 24 483558859 ps
T854 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3345411000 Aug 19 05:02:46 PM PDT 24 Aug 19 05:02:47 PM PDT 24 330107429 ps
T855 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.250727713 Aug 19 05:03:21 PM PDT 24 Aug 19 05:03:23 PM PDT 24 466136530 ps
T856 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2014126995 Aug 19 05:03:10 PM PDT 24 Aug 19 05:03:11 PM PDT 24 465254714 ps
T857 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.374196065 Aug 19 05:02:53 PM PDT 24 Aug 19 05:02:55 PM PDT 24 491276860 ps
T858 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2544700460 Aug 19 05:02:41 PM PDT 24 Aug 19 05:02:42 PM PDT 24 462261171 ps
T59 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.876336249 Aug 19 05:03:24 PM PDT 24 Aug 19 05:03:31 PM PDT 24 9061972831 ps
T859 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3602581305 Aug 19 05:03:08 PM PDT 24 Aug 19 05:03:10 PM PDT 24 485825169 ps
T860 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.316197617 Aug 19 05:02:58 PM PDT 24 Aug 19 05:03:01 PM PDT 24 569705483 ps
T861 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2920109179 Aug 19 05:02:55 PM PDT 24 Aug 19 05:02:56 PM PDT 24 307108865 ps
T862 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.304853081 Aug 19 05:03:22 PM PDT 24 Aug 19 05:03:31 PM PDT 24 2113269792 ps
T863 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.562109688 Aug 19 05:03:23 PM PDT 24 Aug 19 05:03:25 PM PDT 24 498743062 ps
T864 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1573319778 Aug 19 05:03:21 PM PDT 24 Aug 19 05:03:22 PM PDT 24 483705533 ps
T865 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.827161495 Aug 19 05:02:56 PM PDT 24 Aug 19 05:02:57 PM PDT 24 414125603 ps
T866 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3476470413 Aug 19 05:03:32 PM PDT 24 Aug 19 05:03:34 PM PDT 24 359747637 ps
T867 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.724865650 Aug 19 05:03:33 PM PDT 24 Aug 19 05:03:35 PM PDT 24 455900463 ps
T868 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2083418112 Aug 19 05:03:04 PM PDT 24 Aug 19 05:03:05 PM PDT 24 478977192 ps
T869 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.252337235 Aug 19 05:03:22 PM PDT 24 Aug 19 05:03:28 PM PDT 24 3872781918 ps
T870 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4224606258 Aug 19 05:03:05 PM PDT 24 Aug 19 05:03:09 PM PDT 24 638617197 ps
T871 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4254129583 Aug 19 05:02:42 PM PDT 24 Aug 19 05:02:43 PM PDT 24 372758935 ps
T872 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2384158032 Aug 19 05:03:34 PM PDT 24 Aug 19 05:03:35 PM PDT 24 392267230 ps
T873 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4055974236 Aug 19 05:03:22 PM PDT 24 Aug 19 05:03:24 PM PDT 24 374113960 ps
T338 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3568824608 Aug 19 05:02:39 PM PDT 24 Aug 19 05:02:43 PM PDT 24 4253497775 ps
T874 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2990205031 Aug 19 05:02:55 PM PDT 24 Aug 19 05:02:57 PM PDT 24 899270031 ps
T875 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2462109492 Aug 19 05:02:44 PM PDT 24 Aug 19 05:03:01 PM PDT 24 22579456291 ps
T876 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2067140022 Aug 19 05:03:06 PM PDT 24 Aug 19 05:03:08 PM PDT 24 461414807 ps
T877 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3724114994 Aug 19 05:03:22 PM PDT 24 Aug 19 05:03:24 PM PDT 24 717082087 ps
T878 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1546883318 Aug 19 05:03:37 PM PDT 24 Aug 19 05:03:38 PM PDT 24 452637968 ps
T879 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.660033917 Aug 19 05:02:40 PM PDT 24 Aug 19 05:02:42 PM PDT 24 1020701530 ps
T880 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2098470183 Aug 19 05:02:56 PM PDT 24 Aug 19 05:02:57 PM PDT 24 526765195 ps
T881 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.454128042 Aug 19 05:02:45 PM PDT 24 Aug 19 05:02:46 PM PDT 24 718701634 ps
T882 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.328685732 Aug 19 05:02:55 PM PDT 24 Aug 19 05:02:59 PM PDT 24 4655904633 ps
T883 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2018321141 Aug 19 05:03:10 PM PDT 24 Aug 19 05:03:11 PM PDT 24 450067067 ps
T884 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2743090069 Aug 19 05:03:21 PM PDT 24 Aug 19 05:03:22 PM PDT 24 497940114 ps
T885 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.304068033 Aug 19 05:03:08 PM PDT 24 Aug 19 05:03:10 PM PDT 24 502508090 ps
T886 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.703427779 Aug 19 05:02:43 PM PDT 24 Aug 19 05:02:45 PM PDT 24 305052777 ps
T887 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2500942267 Aug 19 05:02:44 PM PDT 24 Aug 19 05:03:04 PM PDT 24 7956102153 ps
T888 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3035920471 Aug 19 05:03:08 PM PDT 24 Aug 19 05:03:09 PM PDT 24 517542418 ps
T889 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1010012736 Aug 19 05:03:08 PM PDT 24 Aug 19 05:03:22 PM PDT 24 4507861757 ps
T890 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3700237206 Aug 19 05:03:21 PM PDT 24 Aug 19 05:03:24 PM PDT 24 1351168238 ps
T891 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3074712781 Aug 19 05:03:09 PM PDT 24 Aug 19 05:03:11 PM PDT 24 426316435 ps
T892 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.237297570 Aug 19 05:03:37 PM PDT 24 Aug 19 05:03:38 PM PDT 24 470869285 ps
T893 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1806227814 Aug 19 05:03:35 PM PDT 24 Aug 19 05:03:36 PM PDT 24 562682201 ps
T894 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.742015195 Aug 19 05:03:38 PM PDT 24 Aug 19 05:03:39 PM PDT 24 520785015 ps
T895 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1093623016 Aug 19 05:03:07 PM PDT 24 Aug 19 05:03:09 PM PDT 24 445561208 ps
T896 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4240938015 Aug 19 05:02:56 PM PDT 24 Aug 19 05:03:04 PM PDT 24 8866525083 ps
T897 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3671776437 Aug 19 05:02:54 PM PDT 24 Aug 19 05:02:55 PM PDT 24 527339094 ps
T898 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.281950322 Aug 19 05:03:31 PM PDT 24 Aug 19 05:03:32 PM PDT 24 295910170 ps
T899 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1809828543 Aug 19 05:02:44 PM PDT 24 Aug 19 05:04:40 PM PDT 24 44499152429 ps
T900 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2609308968 Aug 19 05:03:23 PM PDT 24 Aug 19 05:03:24 PM PDT 24 505493744 ps
T901 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.624145405 Aug 19 05:03:22 PM PDT 24 Aug 19 05:03:23 PM PDT 24 456435035 ps
T902 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2195954858 Aug 19 05:03:21 PM PDT 24 Aug 19 05:03:22 PM PDT 24 351078443 ps
T903 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.31200413 Aug 19 05:03:35 PM PDT 24 Aug 19 05:03:37 PM PDT 24 413566452 ps
T904 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.963589082 Aug 19 05:03:34 PM PDT 24 Aug 19 05:03:36 PM PDT 24 379723749 ps
T905 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.72847263 Aug 19 05:02:43 PM PDT 24 Aug 19 05:02:45 PM PDT 24 477387846 ps
T906 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2538045585 Aug 19 05:02:53 PM PDT 24 Aug 19 05:02:59 PM PDT 24 4059094441 ps
T907 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.906362068 Aug 19 05:02:55 PM PDT 24 Aug 19 05:02:56 PM PDT 24 335610489 ps
T908 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.283183767 Aug 19 05:03:34 PM PDT 24 Aug 19 05:03:36 PM PDT 24 403004010 ps
T909 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.543902191 Aug 19 05:02:57 PM PDT 24 Aug 19 05:02:59 PM PDT 24 408979396 ps
T910 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2043291202 Aug 19 05:02:54 PM PDT 24 Aug 19 05:02:56 PM PDT 24 357782560 ps
T911 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.301148778 Aug 19 05:02:55 PM PDT 24 Aug 19 05:02:57 PM PDT 24 528624664 ps
T912 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.188337245 Aug 19 05:03:06 PM PDT 24 Aug 19 05:03:14 PM PDT 24 8800736443 ps
T913 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3170325788 Aug 19 05:03:05 PM PDT 24 Aug 19 05:03:06 PM PDT 24 430887030 ps
T914 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2803249535 Aug 19 05:02:53 PM PDT 24 Aug 19 05:02:54 PM PDT 24 365150961 ps
T336 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1917620939 Aug 19 05:02:43 PM PDT 24 Aug 19 05:02:54 PM PDT 24 7885047695 ps
T915 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3918398869 Aug 19 05:03:06 PM PDT 24 Aug 19 05:03:28 PM PDT 24 8342635154 ps
T916 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3924722875 Aug 19 05:03:23 PM PDT 24 Aug 19 05:03:35 PM PDT 24 8774787430 ps
T917 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1337510231 Aug 19 05:03:35 PM PDT 24 Aug 19 05:03:36 PM PDT 24 552976998 ps
T918 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3283836366 Aug 19 05:03:33 PM PDT 24 Aug 19 05:03:35 PM PDT 24 378875442 ps
T919 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.954618691 Aug 19 05:02:54 PM PDT 24 Aug 19 05:02:56 PM PDT 24 555132883 ps
T920 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1255426194 Aug 19 05:03:34 PM PDT 24 Aug 19 05:03:35 PM PDT 24 419082204 ps

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1147051085
Short name T9
Test name
Test status
Simulation time 556581856553 ps
CPU time 845.62 seconds
Started Aug 19 05:56:50 PM PDT 24
Finished Aug 19 06:10:56 PM PDT 24
Peak memory 202408 kb
Host smart-4bf08d5b-5050-43a8-bf33-c2d001eea1eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147051085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1147051085
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3029323332
Short name T30
Test name
Test status
Simulation time 535721789988 ps
CPU time 290.44 seconds
Started Aug 19 05:56:52 PM PDT 24
Finished Aug 19 06:01:43 PM PDT 24
Peak memory 202164 kb
Host smart-86a59c24-4768-4e1c-ad8c-168f3cad1e34
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029323332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3029323332
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1916213297
Short name T3
Test name
Test status
Simulation time 18460630270 ps
CPU time 12.68 seconds
Started Aug 19 05:54:49 PM PDT 24
Finished Aug 19 05:55:02 PM PDT 24
Peak memory 210708 kb
Host smart-899673e2-da43-4f6b-95dc-dbda14af5df6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916213297 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1916213297
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.77176380
Short name T126
Test name
Test status
Simulation time 556591624063 ps
CPU time 675.09 seconds
Started Aug 19 05:54:54 PM PDT 24
Finished Aug 19 06:06:09 PM PDT 24
Peak memory 202180 kb
Host smart-1ee47332-5b8a-4f7f-9de3-0b399e7667d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77176380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.77176380
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2578730005
Short name T11
Test name
Test status
Simulation time 568918770531 ps
CPU time 223.16 seconds
Started Aug 19 05:55:09 PM PDT 24
Finished Aug 19 05:58:52 PM PDT 24
Peak memory 202152 kb
Host smart-8f1c14e3-fe04-4903-b19a-3177164288d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578730005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2578730005
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.758072217
Short name T29
Test name
Test status
Simulation time 483689319382 ps
CPU time 297.73 seconds
Started Aug 19 05:55:23 PM PDT 24
Finished Aug 19 06:00:21 PM PDT 24
Peak memory 202164 kb
Host smart-bc7f9aa1-914e-4f52-84c4-98d46dad8a8d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758072217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati
ng.758072217
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.56142746
Short name T156
Test name
Test status
Simulation time 510052167848 ps
CPU time 76.26 seconds
Started Aug 19 05:55:42 PM PDT 24
Finished Aug 19 05:56:59 PM PDT 24
Peak memory 202184 kb
Host smart-aa577086-1ea4-47cb-8f43-850e43531248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56142746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.56142746
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.357899975
Short name T175
Test name
Test status
Simulation time 493989879895 ps
CPU time 536.58 seconds
Started Aug 19 05:56:02 PM PDT 24
Finished Aug 19 06:04:58 PM PDT 24
Peak memory 202184 kb
Host smart-c2378b90-8c44-4f02-b144-0b26b015582e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357899975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
357899975
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1625405977
Short name T80
Test name
Test status
Simulation time 662532439376 ps
CPU time 1141.27 seconds
Started Aug 19 05:56:18 PM PDT 24
Finished Aug 19 06:15:20 PM PDT 24
Peak memory 210556 kb
Host smart-56cf9b22-e1b8-4768-9545-7a5693d6c867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625405977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1625405977
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3912767485
Short name T47
Test name
Test status
Simulation time 382281088 ps
CPU time 2.97 seconds
Started Aug 19 05:02:45 PM PDT 24
Finished Aug 19 05:02:48 PM PDT 24
Peak memory 217180 kb
Host smart-2e657d74-6b60-439e-8c25-970084548987
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912767485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3912767485
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2812296441
Short name T219
Test name
Test status
Simulation time 541272740929 ps
CPU time 1236.46 seconds
Started Aug 19 05:54:48 PM PDT 24
Finished Aug 19 06:15:29 PM PDT 24
Peak memory 202156 kb
Host smart-5c11ae99-95fe-423d-ae21-6f4e6365f6c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812296441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2812296441
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.144003480
Short name T35
Test name
Test status
Simulation time 86779650214 ps
CPU time 293.04 seconds
Started Aug 19 05:55:09 PM PDT 24
Finished Aug 19 06:00:02 PM PDT 24
Peak memory 202364 kb
Host smart-3f2add6f-3bbe-4b13-bdd9-e4c9ccf8576a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144003480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.144003480
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2446221049
Short name T119
Test name
Test status
Simulation time 518257752800 ps
CPU time 273.15 seconds
Started Aug 19 05:55:44 PM PDT 24
Finished Aug 19 06:00:18 PM PDT 24
Peak memory 202160 kb
Host smart-9b26adfe-71a4-4319-b90a-f55b45fcfaaf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446221049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2446221049
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2149622320
Short name T63
Test name
Test status
Simulation time 595109892046 ps
CPU time 1319.02 seconds
Started Aug 19 05:56:17 PM PDT 24
Finished Aug 19 06:18:16 PM PDT 24
Peak memory 202124 kb
Host smart-ed3cde9b-c591-4f2c-bf29-b83709c4f298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149622320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2149622320
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3784124700
Short name T255
Test name
Test status
Simulation time 502593118508 ps
CPU time 558.32 seconds
Started Aug 19 05:55:51 PM PDT 24
Finished Aug 19 06:05:09 PM PDT 24
Peak memory 202200 kb
Host smart-371c641e-e194-4377-832d-27f9f7636097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784124700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3784124700
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1492667446
Short name T23
Test name
Test status
Simulation time 507828959644 ps
CPU time 1210.69 seconds
Started Aug 19 05:54:51 PM PDT 24
Finished Aug 19 06:15:02 PM PDT 24
Peak memory 202172 kb
Host smart-b1978983-e7d6-41b1-abed-acdc10666b79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492667446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1492667446
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.811081146
Short name T96
Test name
Test status
Simulation time 482641131 ps
CPU time 1.89 seconds
Started Aug 19 05:03:08 PM PDT 24
Finished Aug 19 05:03:10 PM PDT 24
Peak memory 200928 kb
Host smart-bb4b1bf7-4d84-48d2-9668-e305ab388482
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811081146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.811081146
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.646488013
Short name T51
Test name
Test status
Simulation time 416922732 ps
CPU time 1.43 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 05:55:34 PM PDT 24
Peak memory 202012 kb
Host smart-0714ef87-7a9f-4551-ad76-df5cf89eb1f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646488013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.646488013
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1457476397
Short name T161
Test name
Test status
Simulation time 518654442719 ps
CPU time 317.81 seconds
Started Aug 19 05:55:08 PM PDT 24
Finished Aug 19 06:00:26 PM PDT 24
Peak memory 202184 kb
Host smart-bb63d8b0-cec6-44ac-b440-0a2926242449
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457476397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1457476397
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2140630642
Short name T61
Test name
Test status
Simulation time 4146841014 ps
CPU time 3.01 seconds
Started Aug 19 05:54:40 PM PDT 24
Finished Aug 19 05:54:43 PM PDT 24
Peak memory 217508 kb
Host smart-ce612cc0-2826-464b-8648-d614129411ee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140630642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2140630642
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.371999350
Short name T10
Test name
Test status
Simulation time 321368298056 ps
CPU time 766.76 seconds
Started Aug 19 05:55:21 PM PDT 24
Finished Aug 19 06:08:08 PM PDT 24
Peak memory 202176 kb
Host smart-1ec7c7bd-9058-4db4-be17-0f4af8a5f1a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371999350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.371999350
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2179570529
Short name T248
Test name
Test status
Simulation time 520309215158 ps
CPU time 586.27 seconds
Started Aug 19 05:55:00 PM PDT 24
Finished Aug 19 06:04:46 PM PDT 24
Peak memory 202144 kb
Host smart-ff3162cc-c464-4e8c-9e7e-559036ae9a35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179570529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2179570529
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3089468143
Short name T206
Test name
Test status
Simulation time 492418683426 ps
CPU time 242.1 seconds
Started Aug 19 05:56:04 PM PDT 24
Finished Aug 19 06:00:06 PM PDT 24
Peak memory 202252 kb
Host smart-9c801128-4622-4ea6-8475-ea6ce815168f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089468143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3089468143
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1169644398
Short name T170
Test name
Test status
Simulation time 488468157872 ps
CPU time 200.62 seconds
Started Aug 19 05:57:22 PM PDT 24
Finished Aug 19 06:00:43 PM PDT 24
Peak memory 202148 kb
Host smart-37bab145-a988-4e3b-9d9f-59d5628ed448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169644398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1169644398
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1994724685
Short name T143
Test name
Test status
Simulation time 497449007432 ps
CPU time 238.66 seconds
Started Aug 19 05:55:23 PM PDT 24
Finished Aug 19 05:59:22 PM PDT 24
Peak memory 202140 kb
Host smart-9a019091-bf8f-40e0-8ae0-a706d6ef5e73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994724685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1994724685
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.807476568
Short name T204
Test name
Test status
Simulation time 511721932096 ps
CPU time 1042.22 seconds
Started Aug 19 05:54:37 PM PDT 24
Finished Aug 19 06:12:00 PM PDT 24
Peak memory 202172 kb
Host smart-5902f8b3-e2f6-470a-9f3e-f4b36ec3c7c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807476568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.807476568
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3325346271
Short name T209
Test name
Test status
Simulation time 179235047822 ps
CPU time 182.95 seconds
Started Aug 19 05:55:23 PM PDT 24
Finished Aug 19 05:58:26 PM PDT 24
Peak memory 202152 kb
Host smart-6abe9d95-b596-4da0-b219-97f741f37af0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325346271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3325346271
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2819629465
Short name T250
Test name
Test status
Simulation time 386168622706 ps
CPU time 211.66 seconds
Started Aug 19 05:57:11 PM PDT 24
Finished Aug 19 06:00:43 PM PDT 24
Peak memory 202204 kb
Host smart-606a3baa-d7ee-441d-90fd-1ebffc501277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819629465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2819629465
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.38981590
Short name T150
Test name
Test status
Simulation time 520371763770 ps
CPU time 1266.39 seconds
Started Aug 19 05:55:16 PM PDT 24
Finished Aug 19 06:16:23 PM PDT 24
Peak memory 202208 kb
Host smart-21ace395-136b-4001-bf3e-3ede2720a71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38981590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.38981590
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.913716406
Short name T214
Test name
Test status
Simulation time 338574367614 ps
CPU time 498.64 seconds
Started Aug 19 05:55:59 PM PDT 24
Finished Aug 19 06:04:17 PM PDT 24
Peak memory 202144 kb
Host smart-46f60737-c501-4755-99de-2a01764cf92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913716406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.913716406
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.874785009
Short name T252
Test name
Test status
Simulation time 342157557142 ps
CPU time 718.28 seconds
Started Aug 19 05:56:18 PM PDT 24
Finished Aug 19 06:08:17 PM PDT 24
Peak memory 202232 kb
Host smart-e72900f3-e047-4bb9-928c-5b24749f2de2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874785009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.874785009
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3956076989
Short name T274
Test name
Test status
Simulation time 549282216640 ps
CPU time 736.47 seconds
Started Aug 19 05:55:30 PM PDT 24
Finished Aug 19 06:07:46 PM PDT 24
Peak memory 202180 kb
Host smart-07cbafea-5719-4c8e-b2f9-671b918d1820
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956076989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3956076989
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.557046982
Short name T256
Test name
Test status
Simulation time 11189881772 ps
CPU time 6.59 seconds
Started Aug 19 05:55:39 PM PDT 24
Finished Aug 19 05:55:46 PM PDT 24
Peak memory 202264 kb
Host smart-45874bc3-e17c-46dd-8cc6-3e97c0e9b38e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557046982 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.557046982
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.818779561
Short name T224
Test name
Test status
Simulation time 624233228618 ps
CPU time 1442.62 seconds
Started Aug 19 05:57:23 PM PDT 24
Finished Aug 19 06:21:26 PM PDT 24
Peak memory 202176 kb
Host smart-e76ed7e0-bc04-48f0-adfe-0217e7008233
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818779561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.818779561
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1692959093
Short name T42
Test name
Test status
Simulation time 8201333752 ps
CPU time 19.26 seconds
Started Aug 19 05:03:22 PM PDT 24
Finished Aug 19 05:03:41 PM PDT 24
Peak memory 201160 kb
Host smart-dfb89271-9711-4fbc-9985-44a734d7f61b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692959093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1692959093
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1980729652
Short name T172
Test name
Test status
Simulation time 603808185144 ps
CPU time 112.86 seconds
Started Aug 19 05:54:57 PM PDT 24
Finished Aug 19 05:56:50 PM PDT 24
Peak memory 202196 kb
Host smart-25959dfd-ba30-4e40-9eec-2910a08bef69
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980729652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1980729652
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3127754181
Short name T67
Test name
Test status
Simulation time 491069272514 ps
CPU time 586.36 seconds
Started Aug 19 05:55:46 PM PDT 24
Finished Aug 19 06:05:32 PM PDT 24
Peak memory 202296 kb
Host smart-fc3722cc-f347-4af0-8a08-eea1c4fe1be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127754181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3127754181
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.274433799
Short name T168
Test name
Test status
Simulation time 555310877625 ps
CPU time 108.14 seconds
Started Aug 19 05:55:02 PM PDT 24
Finished Aug 19 05:56:50 PM PDT 24
Peak memory 202156 kb
Host smart-717c22bb-9e3d-4dde-8ed7-b2e14c3f87aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274433799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.274433799
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.289736626
Short name T275
Test name
Test status
Simulation time 346154129332 ps
CPU time 827.96 seconds
Started Aug 19 05:54:47 PM PDT 24
Finished Aug 19 06:08:35 PM PDT 24
Peak memory 202204 kb
Host smart-72c35deb-20c9-4e17-b7e1-a9a9dbc27360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289736626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.289736626
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3997047874
Short name T258
Test name
Test status
Simulation time 177579882129 ps
CPU time 408.12 seconds
Started Aug 19 05:55:47 PM PDT 24
Finished Aug 19 06:02:36 PM PDT 24
Peak memory 202160 kb
Host smart-cc62de82-3433-408e-b0c2-d150f78dd360
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997047874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3997047874
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.946887226
Short name T210
Test name
Test status
Simulation time 368792464193 ps
CPU time 771.66 seconds
Started Aug 19 05:56:51 PM PDT 24
Finished Aug 19 06:09:43 PM PDT 24
Peak memory 202168 kb
Host smart-63f6e15c-628e-4413-a793-e3502cb3931d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946887226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.946887226
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1276286134
Short name T296
Test name
Test status
Simulation time 363064810690 ps
CPU time 834.87 seconds
Started Aug 19 05:55:10 PM PDT 24
Finished Aug 19 06:09:05 PM PDT 24
Peak memory 202216 kb
Host smart-61c9f40e-3f66-42f7-a633-5dae427fa28d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276286134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1276286134
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3243190764
Short name T238
Test name
Test status
Simulation time 330799081941 ps
CPU time 786.78 seconds
Started Aug 19 05:55:12 PM PDT 24
Finished Aug 19 06:08:19 PM PDT 24
Peak memory 202148 kb
Host smart-014430c4-c687-4b7f-a910-4688ee9b3e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243190764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3243190764
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2433470241
Short name T216
Test name
Test status
Simulation time 321054886047 ps
CPU time 768.45 seconds
Started Aug 19 05:54:48 PM PDT 24
Finished Aug 19 06:07:37 PM PDT 24
Peak memory 202152 kb
Host smart-75c38d9a-383e-429f-97c4-a8fe42807fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433470241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2433470241
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1940249561
Short name T203
Test name
Test status
Simulation time 81116140721 ps
CPU time 8.93 seconds
Started Aug 19 05:54:54 PM PDT 24
Finished Aug 19 05:55:03 PM PDT 24
Peak memory 202272 kb
Host smart-05defb5c-c3bb-456a-81b4-a00df06a77a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940249561 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1940249561
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1143886444
Short name T299
Test name
Test status
Simulation time 511001841751 ps
CPU time 766.88 seconds
Started Aug 19 05:55:25 PM PDT 24
Finished Aug 19 06:08:12 PM PDT 24
Peak memory 202064 kb
Host smart-dc64e804-c45a-45be-82b2-34c455f5ae5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143886444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1143886444
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3611538686
Short name T215
Test name
Test status
Simulation time 376232155911 ps
CPU time 784.32 seconds
Started Aug 19 05:55:31 PM PDT 24
Finished Aug 19 06:08:36 PM PDT 24
Peak memory 202172 kb
Host smart-a0242c63-7d33-4789-a86c-497e0aa091d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611538686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3611538686
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2142030443
Short name T232
Test name
Test status
Simulation time 341100132985 ps
CPU time 418.67 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 06:02:27 PM PDT 24
Peak memory 202208 kb
Host smart-1e944ecc-2509-4854-a161-b807ed1d36f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142030443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2142030443
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.865500143
Short name T267
Test name
Test status
Simulation time 503959761156 ps
CPU time 218.96 seconds
Started Aug 19 05:55:19 PM PDT 24
Finished Aug 19 05:58:58 PM PDT 24
Peak memory 202160 kb
Host smart-282600d5-9b62-4df1-b897-5a38d1833ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865500143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
865500143
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.644739695
Short name T124
Test name
Test status
Simulation time 163926707268 ps
CPU time 393.78 seconds
Started Aug 19 05:54:48 PM PDT 24
Finished Aug 19 06:01:22 PM PDT 24
Peak memory 202192 kb
Host smart-8cdd7667-38a7-457f-ac4e-a901d59d56ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644739695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.644739695
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.297643256
Short name T332
Test name
Test status
Simulation time 329448396466 ps
CPU time 186.06 seconds
Started Aug 19 05:55:59 PM PDT 24
Finished Aug 19 05:59:05 PM PDT 24
Peak memory 202168 kb
Host smart-e3620cc1-1881-4c73-b8fd-fba55aadb562
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297643256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.297643256
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2538847958
Short name T212
Test name
Test status
Simulation time 197739446721 ps
CPU time 311.42 seconds
Started Aug 19 05:56:00 PM PDT 24
Finished Aug 19 06:01:11 PM PDT 24
Peak memory 202148 kb
Host smart-abb618d6-8b9f-4e48-8295-5218be1fcd10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538847958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2538847958
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3625715303
Short name T285
Test name
Test status
Simulation time 389496497002 ps
CPU time 456.01 seconds
Started Aug 19 05:55:33 PM PDT 24
Finished Aug 19 06:03:10 PM PDT 24
Peak memory 202180 kb
Host smart-db0f1814-3900-4b64-b77b-10b8a1d88313
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625715303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3625715303
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3410703449
Short name T123
Test name
Test status
Simulation time 574573632535 ps
CPU time 1286.75 seconds
Started Aug 19 05:56:35 PM PDT 24
Finished Aug 19 06:18:02 PM PDT 24
Peak memory 202164 kb
Host smart-9f3b0ce4-5f8b-49b0-bfdf-b6070ff73ad1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410703449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3410703449
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3919519883
Short name T266
Test name
Test status
Simulation time 482217586601 ps
CPU time 1132.18 seconds
Started Aug 19 05:57:12 PM PDT 24
Finished Aug 19 06:16:04 PM PDT 24
Peak memory 202228 kb
Host smart-303bcdac-ee58-448e-8ee0-3d036631e793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919519883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3919519883
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3126026605
Short name T138
Test name
Test status
Simulation time 168524727485 ps
CPU time 91.68 seconds
Started Aug 19 05:55:00 PM PDT 24
Finished Aug 19 05:56:32 PM PDT 24
Peak memory 202132 kb
Host smart-04388110-cb80-480b-b9ad-9bddae6bd60d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126026605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3126026605
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2626482704
Short name T93
Test name
Test status
Simulation time 483383787368 ps
CPU time 1163.82 seconds
Started Aug 19 05:55:03 PM PDT 24
Finished Aug 19 06:14:27 PM PDT 24
Peak memory 202144 kb
Host smart-fc978ce9-630f-47b7-acd7-a1ff29f1667f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626482704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2626482704
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2738118153
Short name T300
Test name
Test status
Simulation time 333690914027 ps
CPU time 182.83 seconds
Started Aug 19 05:55:19 PM PDT 24
Finished Aug 19 05:58:22 PM PDT 24
Peak memory 202156 kb
Host smart-8fadc78f-1378-4f45-a03a-b39ab1f6329d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738118153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2738118153
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2515611511
Short name T194
Test name
Test status
Simulation time 136268295662 ps
CPU time 507.43 seconds
Started Aug 19 05:55:19 PM PDT 24
Finished Aug 19 06:03:47 PM PDT 24
Peak memory 202408 kb
Host smart-8f73db63-8c39-4ad9-b43b-c7734e0c80a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515611511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2515611511
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3968790294
Short name T464
Test name
Test status
Simulation time 110387310232 ps
CPU time 581.52 seconds
Started Aug 19 05:55:36 PM PDT 24
Finished Aug 19 06:05:18 PM PDT 24
Peak memory 202408 kb
Host smart-60e0bc0f-f369-492f-a4b7-257fc016eece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968790294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3968790294
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3655130697
Short name T68
Test name
Test status
Simulation time 165218896739 ps
CPU time 95.47 seconds
Started Aug 19 05:55:53 PM PDT 24
Finished Aug 19 05:57:29 PM PDT 24
Peak memory 202168 kb
Host smart-7300269c-56b9-4cf1-9ee1-5b5863e3b184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655130697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3655130697
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2563017870
Short name T273
Test name
Test status
Simulation time 387173223040 ps
CPU time 808.03 seconds
Started Aug 19 05:56:07 PM PDT 24
Finished Aug 19 06:09:35 PM PDT 24
Peak memory 202128 kb
Host smart-39888e4e-484d-49a0-8b46-41d45d8f5d2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563017870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2563017870
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2993826509
Short name T302
Test name
Test status
Simulation time 167606469355 ps
CPU time 97.59 seconds
Started Aug 19 05:56:34 PM PDT 24
Finished Aug 19 05:58:12 PM PDT 24
Peak memory 202108 kb
Host smart-4c041f6f-488b-430c-a6a5-1f50131f6273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993826509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2993826509
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3386201156
Short name T228
Test name
Test status
Simulation time 170288104094 ps
CPU time 99.35 seconds
Started Aug 19 05:56:44 PM PDT 24
Finished Aug 19 05:58:24 PM PDT 24
Peak memory 202172 kb
Host smart-a01b84d5-71b0-4c56-b114-436cb3587796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386201156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3386201156
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1663303040
Short name T693
Test name
Test status
Simulation time 17034644383 ps
CPU time 10.26 seconds
Started Aug 19 05:54:55 PM PDT 24
Finished Aug 19 05:55:06 PM PDT 24
Peak memory 210488 kb
Host smart-70460176-8c86-47f6-8fe2-0011b8a1eddb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663303040 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1663303040
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.587875459
Short name T153
Test name
Test status
Simulation time 434230398914 ps
CPU time 240.66 seconds
Started Aug 19 05:55:15 PM PDT 24
Finished Aug 19 05:59:16 PM PDT 24
Peak memory 202176 kb
Host smart-322f3979-e84e-4b04-bf1e-01770dc9f986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587875459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.587875459
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2636232724
Short name T303
Test name
Test status
Simulation time 638402837090 ps
CPU time 284.86 seconds
Started Aug 19 05:55:29 PM PDT 24
Finished Aug 19 06:00:14 PM PDT 24
Peak memory 202156 kb
Host smart-7c993d8f-8d99-49e3-b464-0c305ceed52d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636232724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2636232724
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.596623650
Short name T270
Test name
Test status
Simulation time 481783159985 ps
CPU time 542.56 seconds
Started Aug 19 05:55:26 PM PDT 24
Finished Aug 19 06:04:29 PM PDT 24
Peak memory 202036 kb
Host smart-b9aece8e-c2ae-48d2-952a-bd9ef5784ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596623650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.596623650
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3464051941
Short name T269
Test name
Test status
Simulation time 527729637068 ps
CPU time 1320.38 seconds
Started Aug 19 05:55:24 PM PDT 24
Finished Aug 19 06:17:25 PM PDT 24
Peak memory 202144 kb
Host smart-65b42f76-cbe6-4904-a3a1-91cd0c37bb54
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464051941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3464051941
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2333056791
Short name T834
Test name
Test status
Simulation time 549302247 ps
CPU time 1.6 seconds
Started Aug 19 05:02:40 PM PDT 24
Finished Aug 19 05:02:42 PM PDT 24
Peak memory 201184 kb
Host smart-2e320251-f0c4-40ac-9c9b-b84ba2ab40c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333056791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2333056791
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.876336249
Short name T59
Test name
Test status
Simulation time 9061972831 ps
CPU time 7.3 seconds
Started Aug 19 05:03:24 PM PDT 24
Finished Aug 19 05:03:31 PM PDT 24
Peak memory 201180 kb
Host smart-14cebaaf-91bf-464c-8875-9d9821eb38d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876336249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.876336249
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1917620939
Short name T336
Test name
Test status
Simulation time 7885047695 ps
CPU time 11.06 seconds
Started Aug 19 05:02:43 PM PDT 24
Finished Aug 19 05:02:54 PM PDT 24
Peak memory 201148 kb
Host smart-212c942f-b429-48f6-a624-288d5c105758
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917620939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1917620939
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.956345328
Short name T280
Test name
Test status
Simulation time 334270973336 ps
CPU time 767.21 seconds
Started Aug 19 05:54:39 PM PDT 24
Finished Aug 19 06:07:26 PM PDT 24
Peak memory 202108 kb
Host smart-39e39fa4-f897-46a4-ad81-90bc83bf38a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956345328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.956345328
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.4183424771
Short name T189
Test name
Test status
Simulation time 118072895152 ps
CPU time 396.67 seconds
Started Aug 19 05:55:10 PM PDT 24
Finished Aug 19 06:01:47 PM PDT 24
Peak memory 202400 kb
Host smart-a36b7842-9676-4a66-86a8-01ce6d6afba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183424771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.4183424771
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.195289100
Short name T263
Test name
Test status
Simulation time 175541008103 ps
CPU time 426.72 seconds
Started Aug 19 05:55:10 PM PDT 24
Finished Aug 19 06:02:17 PM PDT 24
Peak memory 202172 kb
Host smart-141dd96a-5ec6-4244-977f-43db2618e34a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195289100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.195289100
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.467031258
Short name T341
Test name
Test status
Simulation time 100821949280 ps
CPU time 302.97 seconds
Started Aug 19 05:55:12 PM PDT 24
Finished Aug 19 06:00:15 PM PDT 24
Peak memory 202428 kb
Host smart-e15e6504-f107-4369-85cd-b96709632855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467031258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.467031258
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.315443459
Short name T343
Test name
Test status
Simulation time 104199160654 ps
CPU time 535.01 seconds
Started Aug 19 05:55:18 PM PDT 24
Finished Aug 19 06:04:14 PM PDT 24
Peak memory 202452 kb
Host smart-10d5046e-2858-4189-be04-57145146c47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315443459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.315443459
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1373765112
Short name T198
Test name
Test status
Simulation time 97608543041 ps
CPU time 480.11 seconds
Started Aug 19 05:55:16 PM PDT 24
Finished Aug 19 06:03:17 PM PDT 24
Peak memory 202440 kb
Host smart-1bbc57a9-b88b-4e43-b437-5c9725c6f5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373765112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1373765112
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2990793530
Short name T229
Test name
Test status
Simulation time 491773382603 ps
CPU time 1062.57 seconds
Started Aug 19 05:55:32 PM PDT 24
Finished Aug 19 06:13:15 PM PDT 24
Peak memory 202180 kb
Host smart-ba97dd69-aa2b-4400-a398-9ab87a451400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990793530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2990793530
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.523817592
Short name T800
Test name
Test status
Simulation time 537809483058 ps
CPU time 339.8 seconds
Started Aug 19 05:55:26 PM PDT 24
Finished Aug 19 06:01:06 PM PDT 24
Peak memory 202124 kb
Host smart-e14733a6-74ca-45ca-af5a-f63ae62a9ce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523817592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
523817592
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1497946423
Short name T43
Test name
Test status
Simulation time 54568074379 ps
CPU time 19.08 seconds
Started Aug 19 05:55:45 PM PDT 24
Finished Aug 19 05:56:04 PM PDT 24
Peak memory 210772 kb
Host smart-56fcc734-6d6b-47ff-a6d8-44044adc7fac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497946423 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1497946423
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3910028422
Short name T326
Test name
Test status
Simulation time 6789041512 ps
CPU time 5.09 seconds
Started Aug 19 05:55:52 PM PDT 24
Finished Aug 19 05:55:57 PM PDT 24
Peak memory 212192 kb
Host smart-22266efd-480d-46a8-aa5b-93ac9b7d0ec3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910028422 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3910028422
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3054737418
Short name T312
Test name
Test status
Simulation time 365972276783 ps
CPU time 774.06 seconds
Started Aug 19 05:56:19 PM PDT 24
Finished Aug 19 06:09:13 PM PDT 24
Peak memory 202116 kb
Host smart-0b7e8798-522c-44e4-a8de-51b37ddc1787
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054737418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3054737418
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1638428316
Short name T265
Test name
Test status
Simulation time 330140204630 ps
CPU time 696.03 seconds
Started Aug 19 05:56:24 PM PDT 24
Finished Aug 19 06:08:01 PM PDT 24
Peak memory 200928 kb
Host smart-ee34e0cc-31f4-4931-8b4e-b43d0030c300
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638428316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1638428316
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2404437677
Short name T345
Test name
Test status
Simulation time 153884434900 ps
CPU time 422.72 seconds
Started Aug 19 05:56:35 PM PDT 24
Finished Aug 19 06:03:38 PM PDT 24
Peak memory 211636 kb
Host smart-0b674a8c-1708-4bf8-8b5b-ac7a40cf037b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404437677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2404437677
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2357864256
Short name T286
Test name
Test status
Simulation time 14026885283 ps
CPU time 19.3 seconds
Started Aug 19 05:56:42 PM PDT 24
Finished Aug 19 05:57:02 PM PDT 24
Peak memory 210724 kb
Host smart-1aa3b251-2305-4a72-a3fa-f8615cd47be9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357864256 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2357864256
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1601257543
Short name T201
Test name
Test status
Simulation time 131014309401 ps
CPU time 587.55 seconds
Started Aug 19 05:57:02 PM PDT 24
Finished Aug 19 06:06:50 PM PDT 24
Peak memory 202368 kb
Host smart-234f1a9f-4298-4bf6-a452-f63a5766815d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601257543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1601257543
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.660033917
Short name T879
Test name
Test status
Simulation time 1020701530 ps
CPU time 1.67 seconds
Started Aug 19 05:02:40 PM PDT 24
Finished Aug 19 05:02:42 PM PDT 24
Peak memory 201104 kb
Host smart-da4e7877-16dc-423e-93dc-4220d90a03d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660033917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.660033917
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2462109492
Short name T875
Test name
Test status
Simulation time 22579456291 ps
CPU time 16.24 seconds
Started Aug 19 05:02:44 PM PDT 24
Finished Aug 19 05:03:01 PM PDT 24
Peak memory 201184 kb
Host smart-33bfda5d-e5cf-4990-b827-f10f76a42bbb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462109492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2462109492
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.167850452
Short name T101
Test name
Test status
Simulation time 608234655 ps
CPU time 1.13 seconds
Started Aug 19 05:02:44 PM PDT 24
Finished Aug 19 05:02:45 PM PDT 24
Peak memory 200972 kb
Host smart-28d0c27f-fa51-42ec-af69-6dd4314576b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167850452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.167850452
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.735711918
Short name T55
Test name
Test status
Simulation time 498652713 ps
CPU time 1.46 seconds
Started Aug 19 05:02:45 PM PDT 24
Finished Aug 19 05:02:46 PM PDT 24
Peak memory 209388 kb
Host smart-721ec029-fb5d-4035-bec8-0e8c39df5460
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735711918 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.735711918
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.72847263
Short name T905
Test name
Test status
Simulation time 477387846 ps
CPU time 1.63 seconds
Started Aug 19 05:02:43 PM PDT 24
Finished Aug 19 05:02:45 PM PDT 24
Peak memory 200956 kb
Host smart-86593853-66ed-44fc-ac2b-a8329f691c2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72847263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.72847263
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2069306774
Short name T826
Test name
Test status
Simulation time 457143024 ps
CPU time 0.9 seconds
Started Aug 19 05:02:47 PM PDT 24
Finished Aug 19 05:02:48 PM PDT 24
Peak memory 200828 kb
Host smart-15ca5141-3945-4db6-8680-d214e9f13b37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069306774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2069306774
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2919670848
Short name T851
Test name
Test status
Simulation time 3437437262 ps
CPU time 3.22 seconds
Started Aug 19 05:02:44 PM PDT 24
Finished Aug 19 05:02:47 PM PDT 24
Peak memory 201172 kb
Host smart-bb598a50-a302-43aa-85d8-a1896ee0c830
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919670848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2919670848
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3568824608
Short name T338
Test name
Test status
Simulation time 4253497775 ps
CPU time 3.91 seconds
Started Aug 19 05:02:39 PM PDT 24
Finished Aug 19 05:02:43 PM PDT 24
Peak memory 201128 kb
Host smart-5837b0d6-4567-42f7-814f-eadbf47655f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568824608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3568824608
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4243307274
Short name T835
Test name
Test status
Simulation time 1084644689 ps
CPU time 1.63 seconds
Started Aug 19 05:02:41 PM PDT 24
Finished Aug 19 05:02:43 PM PDT 24
Peak memory 201172 kb
Host smart-6897a08f-78a5-4e8c-a810-09991fdce1af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243307274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.4243307274
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1809828543
Short name T899
Test name
Test status
Simulation time 44499152429 ps
CPU time 115.15 seconds
Started Aug 19 05:02:44 PM PDT 24
Finished Aug 19 05:04:40 PM PDT 24
Peak memory 201068 kb
Host smart-44b6dfea-66c1-4338-ac58-65634927e1d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809828543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1809828543
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.454128042
Short name T881
Test name
Test status
Simulation time 718701634 ps
CPU time 1.46 seconds
Started Aug 19 05:02:45 PM PDT 24
Finished Aug 19 05:02:46 PM PDT 24
Peak memory 200912 kb
Host smart-bff4d7a7-24fe-400a-ba1f-cce8fb58011b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454128042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.454128042
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4254129583
Short name T871
Test name
Test status
Simulation time 372758935 ps
CPU time 1.03 seconds
Started Aug 19 05:02:42 PM PDT 24
Finished Aug 19 05:02:43 PM PDT 24
Peak memory 200996 kb
Host smart-ea90df78-3d61-4b5c-9c68-fc897315d7b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254129583 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.4254129583
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1585594524
Short name T98
Test name
Test status
Simulation time 439810413 ps
CPU time 1.04 seconds
Started Aug 19 05:02:42 PM PDT 24
Finished Aug 19 05:02:43 PM PDT 24
Peak memory 200932 kb
Host smart-0b67f1bd-77ad-40ce-a93f-5fc24f7ed580
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585594524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1585594524
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1408587827
Short name T805
Test name
Test status
Simulation time 488310667 ps
CPU time 1.16 seconds
Started Aug 19 05:02:43 PM PDT 24
Finished Aug 19 05:02:45 PM PDT 24
Peak memory 200864 kb
Host smart-95e244c6-2a36-481a-8ad1-71fb592199e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408587827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1408587827
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.638637881
Short name T839
Test name
Test status
Simulation time 4679479792 ps
CPU time 8.62 seconds
Started Aug 19 05:02:44 PM PDT 24
Finished Aug 19 05:02:53 PM PDT 24
Peak memory 201096 kb
Host smart-e7f0be3c-7cea-48db-80d8-3ed3c2531e00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638637881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.638637881
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.703427779
Short name T886
Test name
Test status
Simulation time 305052777 ps
CPU time 2.36 seconds
Started Aug 19 05:02:43 PM PDT 24
Finished Aug 19 05:02:45 PM PDT 24
Peak memory 201172 kb
Host smart-52a2db98-015b-4025-bc61-548ae690f4b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703427779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.703427779
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2500942267
Short name T887
Test name
Test status
Simulation time 7956102153 ps
CPU time 20.14 seconds
Started Aug 19 05:02:44 PM PDT 24
Finished Aug 19 05:03:04 PM PDT 24
Peak memory 201120 kb
Host smart-d0f82090-b572-45c3-a2ea-f422343a69c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500942267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2500942267
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2451822106
Short name T843
Test name
Test status
Simulation time 671418689 ps
CPU time 1.4 seconds
Started Aug 19 05:03:06 PM PDT 24
Finished Aug 19 05:03:07 PM PDT 24
Peak memory 211608 kb
Host smart-e335e5e4-ba27-4522-839b-2a06505511a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451822106 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2451822106
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2584933370
Short name T105
Test name
Test status
Simulation time 387063479 ps
CPU time 1.1 seconds
Started Aug 19 05:03:05 PM PDT 24
Finished Aug 19 05:03:06 PM PDT 24
Peak memory 200940 kb
Host smart-324e9c7c-2628-4786-ae89-7903f28c53c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584933370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2584933370
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2067140022
Short name T876
Test name
Test status
Simulation time 461414807 ps
CPU time 1.71 seconds
Started Aug 19 05:03:06 PM PDT 24
Finished Aug 19 05:03:08 PM PDT 24
Peak memory 200884 kb
Host smart-bb845c38-83e3-4ea4-8a2a-998255e23857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067140022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2067140022
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.872976775
Short name T853
Test name
Test status
Simulation time 5139320562 ps
CPU time 11.26 seconds
Started Aug 19 05:03:08 PM PDT 24
Finished Aug 19 05:03:19 PM PDT 24
Peak memory 201144 kb
Host smart-b0a67492-6ac1-4168-baa4-224c523a6c09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872976775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.872976775
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.304068033
Short name T885
Test name
Test status
Simulation time 502508090 ps
CPU time 2 seconds
Started Aug 19 05:03:08 PM PDT 24
Finished Aug 19 05:03:10 PM PDT 24
Peak memory 201144 kb
Host smart-d2ed59b4-b958-409d-9c5e-52b851d4473c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304068033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.304068033
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.188337245
Short name T912
Test name
Test status
Simulation time 8800736443 ps
CPU time 7.47 seconds
Started Aug 19 05:03:06 PM PDT 24
Finished Aug 19 05:03:14 PM PDT 24
Peak memory 201116 kb
Host smart-f5f0d5e3-87a0-4766-8e9e-335845e2ec1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188337245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.188337245
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2858467421
Short name T811
Test name
Test status
Simulation time 423604568 ps
CPU time 1.36 seconds
Started Aug 19 05:03:03 PM PDT 24
Finished Aug 19 05:03:05 PM PDT 24
Peak memory 200912 kb
Host smart-f7da8b72-a5da-4872-9d48-bec1d2a9d82b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858467421 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2858467421
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2083418112
Short name T868
Test name
Test status
Simulation time 478977192 ps
CPU time 0.99 seconds
Started Aug 19 05:03:04 PM PDT 24
Finished Aug 19 05:03:05 PM PDT 24
Peak memory 200900 kb
Host smart-5d2b01fd-c16a-4cc8-9011-7839017a6784
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083418112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2083418112
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3035920471
Short name T888
Test name
Test status
Simulation time 517542418 ps
CPU time 0.89 seconds
Started Aug 19 05:03:08 PM PDT 24
Finished Aug 19 05:03:09 PM PDT 24
Peak memory 200892 kb
Host smart-0b63ca78-d412-437c-9554-2e03307d9c85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035920471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3035920471
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.824615708
Short name T110
Test name
Test status
Simulation time 3018480978 ps
CPU time 9.37 seconds
Started Aug 19 05:03:07 PM PDT 24
Finished Aug 19 05:03:16 PM PDT 24
Peak memory 200932 kb
Host smart-de6aec46-8ea2-45d5-af3f-bfa60a8caca9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824615708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.824615708
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2039172484
Short name T58
Test name
Test status
Simulation time 598827533 ps
CPU time 2.65 seconds
Started Aug 19 05:03:04 PM PDT 24
Finished Aug 19 05:03:07 PM PDT 24
Peak memory 217468 kb
Host smart-d08b8485-bb2f-416a-8353-91af768a0e58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039172484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2039172484
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3918398869
Short name T915
Test name
Test status
Simulation time 8342635154 ps
CPU time 22.21 seconds
Started Aug 19 05:03:06 PM PDT 24
Finished Aug 19 05:03:28 PM PDT 24
Peak memory 201200 kb
Host smart-32bad0fb-5d1a-4272-af08-043805baa8e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918398869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3918398869
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2306134228
Short name T837
Test name
Test status
Simulation time 392340178 ps
CPU time 1.2 seconds
Started Aug 19 05:03:08 PM PDT 24
Finished Aug 19 05:03:10 PM PDT 24
Peak memory 200972 kb
Host smart-0f0123cc-490e-4e01-927c-9f44fa4444f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306134228 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2306134228
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2700297418
Short name T104
Test name
Test status
Simulation time 474442773 ps
CPU time 1.12 seconds
Started Aug 19 05:03:05 PM PDT 24
Finished Aug 19 05:03:07 PM PDT 24
Peak memory 200948 kb
Host smart-c91f2b90-9152-453f-bba2-7b2e043f6c33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700297418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2700297418
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3782865988
Short name T810
Test name
Test status
Simulation time 388940050 ps
CPU time 1.43 seconds
Started Aug 19 05:03:05 PM PDT 24
Finished Aug 19 05:03:07 PM PDT 24
Peak memory 200888 kb
Host smart-1e32c461-a452-4005-930c-4436307cedce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782865988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3782865988
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2620059923
Short name T836
Test name
Test status
Simulation time 4776446920 ps
CPU time 16.35 seconds
Started Aug 19 05:03:07 PM PDT 24
Finished Aug 19 05:03:23 PM PDT 24
Peak memory 201040 kb
Host smart-d1be2ef0-7a1d-4a16-9a0f-836b3524bdef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620059923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2620059923
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4224606258
Short name T870
Test name
Test status
Simulation time 638617197 ps
CPU time 3.63 seconds
Started Aug 19 05:03:05 PM PDT 24
Finished Aug 19 05:03:09 PM PDT 24
Peak memory 217528 kb
Host smart-e2127b07-a46e-416c-99c6-9b8caba1769f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224606258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4224606258
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.48090676
Short name T823
Test name
Test status
Simulation time 4222046913 ps
CPU time 3.87 seconds
Started Aug 19 05:03:07 PM PDT 24
Finished Aug 19 05:03:11 PM PDT 24
Peak memory 201184 kb
Host smart-bca071c7-b6a1-43cc-974f-937d365de392
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48090676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_int
g_err.48090676
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2650090455
Short name T814
Test name
Test status
Simulation time 444531717 ps
CPU time 1.06 seconds
Started Aug 19 05:03:06 PM PDT 24
Finished Aug 19 05:03:07 PM PDT 24
Peak memory 201000 kb
Host smart-c1b303a6-76d2-402e-9164-7f02f14ec310
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650090455 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2650090455
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2014126995
Short name T856
Test name
Test status
Simulation time 465254714 ps
CPU time 1.39 seconds
Started Aug 19 05:03:10 PM PDT 24
Finished Aug 19 05:03:11 PM PDT 24
Peak memory 200952 kb
Host smart-ac7dde40-f6fa-4172-b1d0-2a83313582f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014126995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2014126995
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3602581305
Short name T859
Test name
Test status
Simulation time 485825169 ps
CPU time 1.73 seconds
Started Aug 19 05:03:08 PM PDT 24
Finished Aug 19 05:03:10 PM PDT 24
Peak memory 200836 kb
Host smart-efee2035-35e5-43e9-81bc-22fe77a49fe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602581305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3602581305
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1010012736
Short name T889
Test name
Test status
Simulation time 4507861757 ps
CPU time 14.35 seconds
Started Aug 19 05:03:08 PM PDT 24
Finished Aug 19 05:03:22 PM PDT 24
Peak memory 201132 kb
Host smart-54643457-c830-4977-a910-7164f8f22704
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010012736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1010012736
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2797135344
Short name T844
Test name
Test status
Simulation time 316418556 ps
CPU time 2.14 seconds
Started Aug 19 05:03:08 PM PDT 24
Finished Aug 19 05:03:10 PM PDT 24
Peak memory 201164 kb
Host smart-a48013a3-e64d-4b20-a9d1-19669a4bd931
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797135344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2797135344
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3526829744
Short name T41
Test name
Test status
Simulation time 4804720097 ps
CPU time 11.59 seconds
Started Aug 19 05:03:08 PM PDT 24
Finished Aug 19 05:03:20 PM PDT 24
Peak memory 201204 kb
Host smart-526aa29b-40fe-4e7b-8620-c3d78bc50eac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526829744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3526829744
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2331783152
Short name T813
Test name
Test status
Simulation time 497995521 ps
CPU time 1.48 seconds
Started Aug 19 05:03:21 PM PDT 24
Finished Aug 19 05:03:23 PM PDT 24
Peak memory 201000 kb
Host smart-76fbcf5c-f5c8-42cb-b07f-f73bf991c7fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331783152 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2331783152
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3371427076
Short name T831
Test name
Test status
Simulation time 313629092 ps
CPU time 1.31 seconds
Started Aug 19 05:03:09 PM PDT 24
Finished Aug 19 05:03:10 PM PDT 24
Peak memory 200832 kb
Host smart-fafd2006-4827-4b97-aa24-10f4fdd31a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371427076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3371427076
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2442578238
Short name T108
Test name
Test status
Simulation time 4529465862 ps
CPU time 5.53 seconds
Started Aug 19 05:03:23 PM PDT 24
Finished Aug 19 05:03:28 PM PDT 24
Peak memory 201204 kb
Host smart-5027e9f7-eccc-4fa1-8aec-3e67080d73df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442578238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2442578238
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3074712781
Short name T891
Test name
Test status
Simulation time 426316435 ps
CPU time 2.33 seconds
Started Aug 19 05:03:09 PM PDT 24
Finished Aug 19 05:03:11 PM PDT 24
Peak memory 217136 kb
Host smart-adb88ae2-df4f-4759-8831-9c88ea980b83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074712781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3074712781
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1770087846
Short name T337
Test name
Test status
Simulation time 4302207530 ps
CPU time 11.57 seconds
Started Aug 19 05:03:07 PM PDT 24
Finished Aug 19 05:03:18 PM PDT 24
Peak memory 201092 kb
Host smart-ff4ca6d3-3a26-4716-883c-d7216533f2c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770087846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1770087846
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.640127538
Short name T828
Test name
Test status
Simulation time 643502354 ps
CPU time 1.2 seconds
Started Aug 19 05:03:21 PM PDT 24
Finished Aug 19 05:03:22 PM PDT 24
Peak memory 201000 kb
Host smart-396f785f-982e-498b-8425-ae48628029b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640127538 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.640127538
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2052283390
Short name T852
Test name
Test status
Simulation time 505978875 ps
CPU time 1.88 seconds
Started Aug 19 05:03:24 PM PDT 24
Finished Aug 19 05:03:26 PM PDT 24
Peak memory 200952 kb
Host smart-4a9b2aba-54cf-4bfa-84d3-eda9dce4a193
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052283390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2052283390
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.250727713
Short name T855
Test name
Test status
Simulation time 466136530 ps
CPU time 1.62 seconds
Started Aug 19 05:03:21 PM PDT 24
Finished Aug 19 05:03:23 PM PDT 24
Peak memory 200864 kb
Host smart-810d83bd-f34a-4d2c-a312-91ba029ce614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250727713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.250727713
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.252337235
Short name T869
Test name
Test status
Simulation time 3872781918 ps
CPU time 5.69 seconds
Started Aug 19 05:03:22 PM PDT 24
Finished Aug 19 05:03:28 PM PDT 24
Peak memory 201156 kb
Host smart-12623c16-8ea2-43b4-a1bd-9496c1afd109
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252337235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.252337235
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2371498466
Short name T56
Test name
Test status
Simulation time 578787956 ps
CPU time 2.82 seconds
Started Aug 19 05:03:22 PM PDT 24
Finished Aug 19 05:03:25 PM PDT 24
Peak memory 201160 kb
Host smart-dff41e14-d004-42d5-95d7-a4bdd6fd05ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371498466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2371498466
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2058598956
Short name T825
Test name
Test status
Simulation time 375936332 ps
CPU time 1.85 seconds
Started Aug 19 05:03:24 PM PDT 24
Finished Aug 19 05:03:26 PM PDT 24
Peak memory 200988 kb
Host smart-908a9bf7-c762-4e91-96d3-014b2e325834
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058598956 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2058598956
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4258085108
Short name T97
Test name
Test status
Simulation time 484307425 ps
CPU time 1.36 seconds
Started Aug 19 05:03:21 PM PDT 24
Finished Aug 19 05:03:23 PM PDT 24
Peak memory 200936 kb
Host smart-f78fe972-4de4-4bd8-b46e-de31b71ae769
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258085108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.4258085108
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.624145405
Short name T901
Test name
Test status
Simulation time 456435035 ps
CPU time 0.98 seconds
Started Aug 19 05:03:22 PM PDT 24
Finished Aug 19 05:03:23 PM PDT 24
Peak memory 200820 kb
Host smart-c5f0300c-37dd-4efb-8954-a677adcbf106
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624145405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.624145405
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.304853081
Short name T862
Test name
Test status
Simulation time 2113269792 ps
CPU time 8.79 seconds
Started Aug 19 05:03:22 PM PDT 24
Finished Aug 19 05:03:31 PM PDT 24
Peak memory 200908 kb
Host smart-124b2b2a-238e-4bfc-bb42-8a0c9c77dbc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304853081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.304853081
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2265956871
Short name T820
Test name
Test status
Simulation time 746798813 ps
CPU time 3.31 seconds
Started Aug 19 05:03:23 PM PDT 24
Finished Aug 19 05:03:26 PM PDT 24
Peak memory 209376 kb
Host smart-ffdbea9e-4c0a-453e-9298-4da5e5c1879e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265956871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2265956871
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3924722875
Short name T916
Test name
Test status
Simulation time 8774787430 ps
CPU time 11.21 seconds
Started Aug 19 05:03:23 PM PDT 24
Finished Aug 19 05:03:35 PM PDT 24
Peak memory 201200 kb
Host smart-8b76a1da-5ed6-4468-9ce6-fc0143eb01c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924722875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3924722875
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3700339471
Short name T827
Test name
Test status
Simulation time 477637039 ps
CPU time 1.85 seconds
Started Aug 19 05:03:21 PM PDT 24
Finished Aug 19 05:03:23 PM PDT 24
Peak memory 200996 kb
Host smart-7af8bc07-f7c7-4141-a37f-d93abdf00986
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700339471 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3700339471
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2195954858
Short name T902
Test name
Test status
Simulation time 351078443 ps
CPU time 1.22 seconds
Started Aug 19 05:03:21 PM PDT 24
Finished Aug 19 05:03:22 PM PDT 24
Peak memory 200932 kb
Host smart-df507e75-abfa-4ba5-b381-9e29ccc56680
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195954858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2195954858
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1573319778
Short name T864
Test name
Test status
Simulation time 483705533 ps
CPU time 1.72 seconds
Started Aug 19 05:03:21 PM PDT 24
Finished Aug 19 05:03:22 PM PDT 24
Peak memory 200900 kb
Host smart-3b09de96-c011-442e-9812-8c87537d3a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573319778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1573319778
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3239001461
Short name T817
Test name
Test status
Simulation time 2367242320 ps
CPU time 4.3 seconds
Started Aug 19 05:03:21 PM PDT 24
Finished Aug 19 05:03:25 PM PDT 24
Peak memory 201012 kb
Host smart-99425ac0-7cd9-4a72-b1de-36e63644f414
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239001461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3239001461
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3700237206
Short name T890
Test name
Test status
Simulation time 1351168238 ps
CPU time 2.77 seconds
Started Aug 19 05:03:21 PM PDT 24
Finished Aug 19 05:03:24 PM PDT 24
Peak memory 201152 kb
Host smart-697dc98d-6456-4bd3-b1fe-ab6b1fb1e8cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700237206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3700237206
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.820919620
Short name T819
Test name
Test status
Simulation time 5291835308 ps
CPU time 4.34 seconds
Started Aug 19 05:03:23 PM PDT 24
Finished Aug 19 05:03:28 PM PDT 24
Peak memory 201108 kb
Host smart-975c1359-926f-414b-b4da-d78ab305a95a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820919620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.820919620
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2609308968
Short name T900
Test name
Test status
Simulation time 505493744 ps
CPU time 1.43 seconds
Started Aug 19 05:03:23 PM PDT 24
Finished Aug 19 05:03:24 PM PDT 24
Peak memory 201000 kb
Host smart-33bae4af-0ec8-4e7b-96e2-1cc0fb9307f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609308968 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2609308968
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2348697952
Short name T848
Test name
Test status
Simulation time 467276151 ps
CPU time 1.08 seconds
Started Aug 19 05:03:24 PM PDT 24
Finished Aug 19 05:03:25 PM PDT 24
Peak memory 200940 kb
Host smart-3525a031-b99e-4896-91cb-aaab4886ff48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348697952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2348697952
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.562109688
Short name T863
Test name
Test status
Simulation time 498743062 ps
CPU time 1.8 seconds
Started Aug 19 05:03:23 PM PDT 24
Finished Aug 19 05:03:25 PM PDT 24
Peak memory 200864 kb
Host smart-d4ac7213-6b89-4a88-9d85-1a03b8fe6a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562109688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.562109688
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4003707459
Short name T832
Test name
Test status
Simulation time 2128515977 ps
CPU time 7.69 seconds
Started Aug 19 05:03:22 PM PDT 24
Finished Aug 19 05:03:30 PM PDT 24
Peak memory 200876 kb
Host smart-166e56a2-3256-416b-864a-e8b2dea8829e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003707459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.4003707459
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1951265573
Short name T53
Test name
Test status
Simulation time 296712268 ps
CPU time 1.95 seconds
Started Aug 19 05:03:23 PM PDT 24
Finished Aug 19 05:03:25 PM PDT 24
Peak memory 201160 kb
Host smart-a86b1e82-4f4e-4522-99fb-c23183889a15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951265573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1951265573
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1844099011
Short name T850
Test name
Test status
Simulation time 4312437650 ps
CPU time 3.98 seconds
Started Aug 19 05:03:22 PM PDT 24
Finished Aug 19 05:03:26 PM PDT 24
Peak memory 201132 kb
Host smart-2ac8c2e4-8c37-4808-9e67-58b5613ebf9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844099011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1844099011
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.78105971
Short name T54
Test name
Test status
Simulation time 478637208 ps
CPU time 2.27 seconds
Started Aug 19 05:03:37 PM PDT 24
Finished Aug 19 05:03:39 PM PDT 24
Peak memory 200988 kb
Host smart-113022d1-b600-4719-b52e-b0e1421a2080
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78105971 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.78105971
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4055974236
Short name T873
Test name
Test status
Simulation time 374113960 ps
CPU time 1.6 seconds
Started Aug 19 05:03:22 PM PDT 24
Finished Aug 19 05:03:24 PM PDT 24
Peak memory 200932 kb
Host smart-70f6c26d-edea-46b1-9bec-38fc9d6f5f24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055974236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.4055974236
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2743090069
Short name T884
Test name
Test status
Simulation time 497940114 ps
CPU time 0.7 seconds
Started Aug 19 05:03:21 PM PDT 24
Finished Aug 19 05:03:22 PM PDT 24
Peak memory 200872 kb
Host smart-444c136b-ee3f-49b0-baeb-757fecec405b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743090069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2743090069
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1744788953
Short name T111
Test name
Test status
Simulation time 4411774562 ps
CPU time 16.76 seconds
Started Aug 19 05:03:23 PM PDT 24
Finished Aug 19 05:03:40 PM PDT 24
Peak memory 201200 kb
Host smart-4ee04ae9-e42f-492a-8b72-7122a046d827
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744788953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1744788953
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3724114994
Short name T877
Test name
Test status
Simulation time 717082087 ps
CPU time 2.47 seconds
Started Aug 19 05:03:22 PM PDT 24
Finished Aug 19 05:03:24 PM PDT 24
Peak memory 209356 kb
Host smart-431765cb-5f4d-4862-a197-08084f047844
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724114994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3724114994
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4201823555
Short name T95
Test name
Test status
Simulation time 566393901 ps
CPU time 2.15 seconds
Started Aug 19 05:02:44 PM PDT 24
Finished Aug 19 05:02:46 PM PDT 24
Peak memory 201120 kb
Host smart-72202b2b-21d4-4254-94e8-6800d01b7a6a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201823555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.4201823555
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1220784468
Short name T38
Test name
Test status
Simulation time 16872958161 ps
CPU time 41.37 seconds
Started Aug 19 05:02:43 PM PDT 24
Finished Aug 19 05:03:24 PM PDT 24
Peak memory 201184 kb
Host smart-cb095d90-9bc4-40c8-98c4-33bcefbf6e7d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220784468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1220784468
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3762266832
Short name T114
Test name
Test status
Simulation time 780205537 ps
CPU time 2.45 seconds
Started Aug 19 05:02:46 PM PDT 24
Finished Aug 19 05:02:48 PM PDT 24
Peak memory 200936 kb
Host smart-642df995-fce7-423c-8a46-ec5a6fd01302
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762266832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3762266832
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1404456954
Short name T73
Test name
Test status
Simulation time 568933930 ps
CPU time 1.63 seconds
Started Aug 19 05:02:47 PM PDT 24
Finished Aug 19 05:02:49 PM PDT 24
Peak memory 200996 kb
Host smart-4ae35188-7644-41ab-b07c-9ec50c7e4625
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404456954 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1404456954
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3345411000
Short name T854
Test name
Test status
Simulation time 330107429 ps
CPU time 1.61 seconds
Started Aug 19 05:02:46 PM PDT 24
Finished Aug 19 05:02:47 PM PDT 24
Peak memory 200900 kb
Host smart-f8c25271-7fc4-42ff-864c-abff2bac42a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345411000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3345411000
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2544700460
Short name T858
Test name
Test status
Simulation time 462261171 ps
CPU time 0.92 seconds
Started Aug 19 05:02:41 PM PDT 24
Finished Aug 19 05:02:42 PM PDT 24
Peak memory 200868 kb
Host smart-a7c40c0b-d094-4805-a4d2-aedf8586473a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544700460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2544700460
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1636650084
Short name T107
Test name
Test status
Simulation time 2539155941 ps
CPU time 7.65 seconds
Started Aug 19 05:02:46 PM PDT 24
Finished Aug 19 05:02:54 PM PDT 24
Peak memory 201024 kb
Host smart-c1627bc5-07c5-471e-a0ff-535ad9a29965
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636650084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1636650084
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2501922230
Short name T57
Test name
Test status
Simulation time 377257273 ps
CPU time 2.74 seconds
Started Aug 19 05:02:46 PM PDT 24
Finished Aug 19 05:02:49 PM PDT 24
Peak memory 201112 kb
Host smart-a1e26b27-bd86-472e-ba20-d8125cc5196d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501922230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2501922230
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.80520503
Short name T40
Test name
Test status
Simulation time 4614834096 ps
CPU time 7.61 seconds
Started Aug 19 05:02:42 PM PDT 24
Finished Aug 19 05:02:49 PM PDT 24
Peak memory 201152 kb
Host smart-eb314d57-1bf9-411b-9366-ce29771299da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80520503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_intg
_err.80520503
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3283836366
Short name T918
Test name
Test status
Simulation time 378875442 ps
CPU time 1.55 seconds
Started Aug 19 05:03:33 PM PDT 24
Finished Aug 19 05:03:35 PM PDT 24
Peak memory 200884 kb
Host smart-bfd71b9b-b731-47fc-a986-f07806f97270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283836366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3283836366
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3650019551
Short name T824
Test name
Test status
Simulation time 470393804 ps
CPU time 1.13 seconds
Started Aug 19 05:03:34 PM PDT 24
Finished Aug 19 05:03:35 PM PDT 24
Peak memory 200792 kb
Host smart-dd7ece47-aa79-48f0-837e-a7657454384f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650019551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3650019551
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1806227814
Short name T893
Test name
Test status
Simulation time 562682201 ps
CPU time 0.82 seconds
Started Aug 19 05:03:35 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 200820 kb
Host smart-cb84fa73-cf43-43a8-ae0e-54e8f2209a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806227814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1806227814
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.626803028
Short name T808
Test name
Test status
Simulation time 526844476 ps
CPU time 1.93 seconds
Started Aug 19 05:03:34 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 200824 kb
Host smart-47776336-659a-4363-b21f-47bfeed70f2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626803028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.626803028
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.31200413
Short name T903
Test name
Test status
Simulation time 413566452 ps
CPU time 1.61 seconds
Started Aug 19 05:03:35 PM PDT 24
Finished Aug 19 05:03:37 PM PDT 24
Peak memory 200864 kb
Host smart-bccdf4a3-930c-4ea6-bb3a-80a15183ef12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31200413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.31200413
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.458919303
Short name T818
Test name
Test status
Simulation time 431134188 ps
CPU time 0.78 seconds
Started Aug 19 05:03:37 PM PDT 24
Finished Aug 19 05:03:38 PM PDT 24
Peak memory 200824 kb
Host smart-8da8cc93-6b1c-41ef-82cd-1686f733be81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458919303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.458919303
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3962242449
Short name T849
Test name
Test status
Simulation time 379507983 ps
CPU time 0.81 seconds
Started Aug 19 05:03:32 PM PDT 24
Finished Aug 19 05:03:33 PM PDT 24
Peak memory 200876 kb
Host smart-9b0e600e-7e1d-4c6f-95e4-e255fe589d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962242449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3962242449
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1774105182
Short name T802
Test name
Test status
Simulation time 413618156 ps
CPU time 0.69 seconds
Started Aug 19 05:03:35 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 200760 kb
Host smart-3eed5b6d-a8b4-4088-90bf-df5ccb524701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774105182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1774105182
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.619499253
Short name T812
Test name
Test status
Simulation time 467585774 ps
CPU time 1.29 seconds
Started Aug 19 05:03:34 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 200864 kb
Host smart-3b2af573-ee00-4af8-8ec3-cc0e4695f059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619499253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.619499253
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2437444035
Short name T801
Test name
Test status
Simulation time 515124213 ps
CPU time 1.88 seconds
Started Aug 19 05:03:34 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 200840 kb
Host smart-08915bb4-f04c-4e5c-9bb8-8a8f6af0e488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437444035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2437444035
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.66951187
Short name T102
Test name
Test status
Simulation time 768228978 ps
CPU time 4.02 seconds
Started Aug 19 05:02:56 PM PDT 24
Finished Aug 19 05:03:00 PM PDT 24
Peak memory 201124 kb
Host smart-a853ea56-fbb7-4501-9d04-6a70c3c27b5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66951187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_aliasi
ng.66951187
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3230367643
Short name T37
Test name
Test status
Simulation time 38518757857 ps
CPU time 152.58 seconds
Started Aug 19 05:02:55 PM PDT 24
Finished Aug 19 05:05:28 PM PDT 24
Peak memory 201148 kb
Host smart-330ad37f-76df-4710-8409-25362d79c21e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230367643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3230367643
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.805952519
Short name T115
Test name
Test status
Simulation time 713360149 ps
CPU time 1.5 seconds
Started Aug 19 05:02:56 PM PDT 24
Finished Aug 19 05:02:57 PM PDT 24
Peak memory 200904 kb
Host smart-bd0f8d23-099f-474b-8698-c828f42308e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805952519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.805952519
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.543902191
Short name T909
Test name
Test status
Simulation time 408979396 ps
CPU time 1.87 seconds
Started Aug 19 05:02:57 PM PDT 24
Finished Aug 19 05:02:59 PM PDT 24
Peak memory 200856 kb
Host smart-9ff7ec30-9dde-46d8-9b6e-66fa3269f5d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543902191 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.543902191
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2098470183
Short name T880
Test name
Test status
Simulation time 526765195 ps
CPU time 1.84 seconds
Started Aug 19 05:02:56 PM PDT 24
Finished Aug 19 05:02:57 PM PDT 24
Peak memory 200904 kb
Host smart-d4fb1e89-74f4-49f0-ae50-2485cf8bb686
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098470183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2098470183
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3376895517
Short name T829
Test name
Test status
Simulation time 324919054 ps
CPU time 0.82 seconds
Started Aug 19 05:02:54 PM PDT 24
Finished Aug 19 05:02:55 PM PDT 24
Peak memory 200848 kb
Host smart-6fea70ac-104b-43ec-aadf-c39551abeb15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376895517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3376895517
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1471399595
Short name T112
Test name
Test status
Simulation time 5007753867 ps
CPU time 9.54 seconds
Started Aug 19 05:02:54 PM PDT 24
Finished Aug 19 05:03:03 PM PDT 24
Peak memory 201176 kb
Host smart-98041b8a-38b5-4f3c-bb75-84b746893749
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471399595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1471399595
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.724865650
Short name T867
Test name
Test status
Simulation time 455900463 ps
CPU time 1.61 seconds
Started Aug 19 05:03:33 PM PDT 24
Finished Aug 19 05:03:35 PM PDT 24
Peak memory 200852 kb
Host smart-437e844c-6f1d-41f2-8abc-2c333359797d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724865650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.724865650
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1546883318
Short name T878
Test name
Test status
Simulation time 452637968 ps
CPU time 1.57 seconds
Started Aug 19 05:03:37 PM PDT 24
Finished Aug 19 05:03:38 PM PDT 24
Peak memory 200876 kb
Host smart-20beeea1-0880-486b-b84d-f5158cc39f18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546883318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1546883318
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3969823865
Short name T833
Test name
Test status
Simulation time 325115572 ps
CPU time 0.87 seconds
Started Aug 19 05:03:37 PM PDT 24
Finished Aug 19 05:03:38 PM PDT 24
Peak memory 200876 kb
Host smart-4ac26ac6-44da-4a69-8122-c2d23141767c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969823865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3969823865
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.281950322
Short name T898
Test name
Test status
Simulation time 295910170 ps
CPU time 1.34 seconds
Started Aug 19 05:03:31 PM PDT 24
Finished Aug 19 05:03:32 PM PDT 24
Peak memory 200876 kb
Host smart-9f8b997d-597e-490c-9880-2aa69fd526e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281950322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.281950322
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1270230668
Short name T846
Test name
Test status
Simulation time 486638331 ps
CPU time 0.94 seconds
Started Aug 19 05:03:34 PM PDT 24
Finished Aug 19 05:03:35 PM PDT 24
Peak memory 200836 kb
Host smart-609d4dfd-a11a-46f8-89bf-0270163ffc20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270230668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1270230668
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.451393133
Short name T821
Test name
Test status
Simulation time 338814417 ps
CPU time 1.04 seconds
Started Aug 19 05:03:35 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 200864 kb
Host smart-c5ad87e0-879d-4df1-89e9-6225416bcaa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451393133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.451393133
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2384158032
Short name T872
Test name
Test status
Simulation time 392267230 ps
CPU time 0.77 seconds
Started Aug 19 05:03:34 PM PDT 24
Finished Aug 19 05:03:35 PM PDT 24
Peak memory 200876 kb
Host smart-9ac71483-c143-401f-8f6d-c1cd5d6aee07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384158032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2384158032
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.963589082
Short name T904
Test name
Test status
Simulation time 379723749 ps
CPU time 1.54 seconds
Started Aug 19 05:03:34 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 200880 kb
Host smart-a4fc3629-97db-49e9-af90-aba82649d0b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963589082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.963589082
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3842892310
Short name T807
Test name
Test status
Simulation time 452509739 ps
CPU time 0.87 seconds
Started Aug 19 05:03:37 PM PDT 24
Finished Aug 19 05:03:38 PM PDT 24
Peak memory 200884 kb
Host smart-cad85bd9-15a2-4fe4-8a53-69cea7ccb66d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842892310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3842892310
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3476470413
Short name T866
Test name
Test status
Simulation time 359747637 ps
CPU time 1.06 seconds
Started Aug 19 05:03:32 PM PDT 24
Finished Aug 19 05:03:34 PM PDT 24
Peak memory 200884 kb
Host smart-978ad269-0b15-4f32-a024-8909082eb926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476470413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3476470413
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2990205031
Short name T874
Test name
Test status
Simulation time 899270031 ps
CPU time 2.02 seconds
Started Aug 19 05:02:55 PM PDT 24
Finished Aug 19 05:02:57 PM PDT 24
Peak memory 201124 kb
Host smart-0427e3d9-577e-4a14-a376-957aba51b2cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990205031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2990205031
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2774940731
Short name T39
Test name
Test status
Simulation time 27109469203 ps
CPU time 55.32 seconds
Started Aug 19 05:02:53 PM PDT 24
Finished Aug 19 05:03:49 PM PDT 24
Peak memory 201144 kb
Host smart-1daa528b-4ca6-43dc-bc53-ec58f9bfd29b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774940731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2774940731
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2764658913
Short name T99
Test name
Test status
Simulation time 1339710508 ps
CPU time 2.22 seconds
Started Aug 19 05:02:57 PM PDT 24
Finished Aug 19 05:03:00 PM PDT 24
Peak memory 200932 kb
Host smart-f5156864-f774-4a75-b6fb-8302146794e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764658913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2764658913
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.827161495
Short name T865
Test name
Test status
Simulation time 414125603 ps
CPU time 0.99 seconds
Started Aug 19 05:02:56 PM PDT 24
Finished Aug 19 05:02:57 PM PDT 24
Peak memory 200956 kb
Host smart-eed385ca-4c0b-473c-be50-91c4c0dd9cc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827161495 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.827161495
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3671776437
Short name T897
Test name
Test status
Simulation time 527339094 ps
CPU time 1.54 seconds
Started Aug 19 05:02:54 PM PDT 24
Finished Aug 19 05:02:55 PM PDT 24
Peak memory 200952 kb
Host smart-ee24015f-d6a1-4be6-8044-289e202b7937
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671776437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3671776437
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2043291202
Short name T910
Test name
Test status
Simulation time 357782560 ps
CPU time 1.45 seconds
Started Aug 19 05:02:54 PM PDT 24
Finished Aug 19 05:02:56 PM PDT 24
Peak memory 200868 kb
Host smart-6d67f526-475e-46ea-a999-ed57fe9fdf66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043291202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2043291202
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3879547300
Short name T106
Test name
Test status
Simulation time 2158019481 ps
CPU time 8.11 seconds
Started Aug 19 05:02:57 PM PDT 24
Finished Aug 19 05:03:06 PM PDT 24
Peak memory 200860 kb
Host smart-9613b64f-8fab-4989-a52e-765b753a1d4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879547300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3879547300
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3023480199
Short name T841
Test name
Test status
Simulation time 576749769 ps
CPU time 1.44 seconds
Started Aug 19 05:02:58 PM PDT 24
Finished Aug 19 05:03:00 PM PDT 24
Peak memory 201180 kb
Host smart-95b5cde9-3c51-4a0f-a000-b1a3c0ed72e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023480199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3023480199
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4240938015
Short name T896
Test name
Test status
Simulation time 8866525083 ps
CPU time 7.87 seconds
Started Aug 19 05:02:56 PM PDT 24
Finished Aug 19 05:03:04 PM PDT 24
Peak memory 201188 kb
Host smart-cb52a326-6191-4cc6-9713-7e53f8738f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240938015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.4240938015
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.237297570
Short name T892
Test name
Test status
Simulation time 470869285 ps
CPU time 0.88 seconds
Started Aug 19 05:03:37 PM PDT 24
Finished Aug 19 05:03:38 PM PDT 24
Peak memory 200880 kb
Host smart-54ec5f4a-22a0-4a5c-8c49-c22028c1d3d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237297570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.237297570
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1255426194
Short name T920
Test name
Test status
Simulation time 419082204 ps
CPU time 1.14 seconds
Started Aug 19 05:03:34 PM PDT 24
Finished Aug 19 05:03:35 PM PDT 24
Peak memory 200884 kb
Host smart-cf64537c-a954-4696-a368-ecae7b303e83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255426194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1255426194
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1337510231
Short name T917
Test name
Test status
Simulation time 552976998 ps
CPU time 1.01 seconds
Started Aug 19 05:03:35 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 200840 kb
Host smart-77e7729c-5982-4cb1-9535-335510d82873
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337510231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1337510231
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1062240552
Short name T840
Test name
Test status
Simulation time 479678191 ps
CPU time 0.88 seconds
Started Aug 19 05:03:34 PM PDT 24
Finished Aug 19 05:03:35 PM PDT 24
Peak memory 200836 kb
Host smart-94e2460b-0223-42e5-a22e-a179e9e7e4f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062240552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1062240552
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2364049519
Short name T815
Test name
Test status
Simulation time 502491438 ps
CPU time 1.79 seconds
Started Aug 19 05:03:33 PM PDT 24
Finished Aug 19 05:03:34 PM PDT 24
Peak memory 200884 kb
Host smart-9b75cc07-c980-4b2f-967b-fadf2c414dfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364049519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2364049519
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.742015195
Short name T894
Test name
Test status
Simulation time 520785015 ps
CPU time 1.29 seconds
Started Aug 19 05:03:38 PM PDT 24
Finished Aug 19 05:03:39 PM PDT 24
Peak memory 200896 kb
Host smart-c80600ac-a83a-476d-8a1c-379c77409e6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742015195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.742015195
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1499220059
Short name T842
Test name
Test status
Simulation time 334932912 ps
CPU time 0.81 seconds
Started Aug 19 05:03:34 PM PDT 24
Finished Aug 19 05:03:35 PM PDT 24
Peak memory 200844 kb
Host smart-40d39e64-d14d-491d-a351-b8c101f65bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499220059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1499220059
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.360810334
Short name T804
Test name
Test status
Simulation time 432161603 ps
CPU time 1.6 seconds
Started Aug 19 05:03:33 PM PDT 24
Finished Aug 19 05:03:35 PM PDT 24
Peak memory 200888 kb
Host smart-613fe3c0-7beb-465d-ad55-97b375dab005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360810334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.360810334
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3419225655
Short name T809
Test name
Test status
Simulation time 291024841 ps
CPU time 1.3 seconds
Started Aug 19 05:03:31 PM PDT 24
Finished Aug 19 05:03:33 PM PDT 24
Peak memory 200836 kb
Host smart-b9b012d1-a972-4a8a-958b-a89810d853df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419225655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3419225655
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.283183767
Short name T908
Test name
Test status
Simulation time 403004010 ps
CPU time 1.51 seconds
Started Aug 19 05:03:34 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 200876 kb
Host smart-469502c8-aa25-4819-b8d5-9183e7f5a665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283183767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.283183767
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2803249535
Short name T914
Test name
Test status
Simulation time 365150961 ps
CPU time 1.02 seconds
Started Aug 19 05:02:53 PM PDT 24
Finished Aug 19 05:02:54 PM PDT 24
Peak memory 200972 kb
Host smart-8abf60bc-fe38-439c-99ec-2dc08de16935
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803249535 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2803249535
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.374196065
Short name T857
Test name
Test status
Simulation time 491276860 ps
CPU time 1.32 seconds
Started Aug 19 05:02:53 PM PDT 24
Finished Aug 19 05:02:55 PM PDT 24
Peak memory 200872 kb
Host smart-8de51d21-7733-4af3-9586-b55079de2ed6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374196065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.374196065
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.906362068
Short name T907
Test name
Test status
Simulation time 335610489 ps
CPU time 0.84 seconds
Started Aug 19 05:02:55 PM PDT 24
Finished Aug 19 05:02:56 PM PDT 24
Peak memory 200872 kb
Host smart-c4c7068c-a4ca-4f97-9dce-147913ed0081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906362068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.906362068
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.413374431
Short name T847
Test name
Test status
Simulation time 4240012908 ps
CPU time 10.41 seconds
Started Aug 19 05:02:54 PM PDT 24
Finished Aug 19 05:03:04 PM PDT 24
Peak memory 201132 kb
Host smart-892d9284-2036-4406-9764-0c2a653cd175
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413374431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.413374431
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3517144703
Short name T48
Test name
Test status
Simulation time 505142919 ps
CPU time 2.84 seconds
Started Aug 19 05:02:53 PM PDT 24
Finished Aug 19 05:02:56 PM PDT 24
Peak memory 201188 kb
Host smart-c42a1a5a-a388-4d26-97d1-5175ee59316a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517144703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3517144703
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.328685732
Short name T882
Test name
Test status
Simulation time 4655904633 ps
CPU time 4.16 seconds
Started Aug 19 05:02:55 PM PDT 24
Finished Aug 19 05:02:59 PM PDT 24
Peak memory 201112 kb
Host smart-17f70d9c-0f61-44f2-b54b-f5696110f45c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328685732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.328685732
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1815496890
Short name T74
Test name
Test status
Simulation time 351124083 ps
CPU time 1.09 seconds
Started Aug 19 05:02:54 PM PDT 24
Finished Aug 19 05:02:55 PM PDT 24
Peak memory 201000 kb
Host smart-7fa72236-a38a-4b0f-803a-827b32cc7994
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815496890 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1815496890
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2920109179
Short name T861
Test name
Test status
Simulation time 307108865 ps
CPU time 1.14 seconds
Started Aug 19 05:02:55 PM PDT 24
Finished Aug 19 05:02:56 PM PDT 24
Peak memory 200936 kb
Host smart-88cd68c8-aad4-4451-8dec-a683e9d6c29c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920109179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2920109179
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3879974452
Short name T816
Test name
Test status
Simulation time 306210468 ps
CPU time 0.96 seconds
Started Aug 19 05:02:56 PM PDT 24
Finished Aug 19 05:02:57 PM PDT 24
Peak memory 200864 kb
Host smart-7d4b426b-2ed5-4f78-bc1c-14b5176d06d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879974452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3879974452
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2538045585
Short name T906
Test name
Test status
Simulation time 4059094441 ps
CPU time 5.85 seconds
Started Aug 19 05:02:53 PM PDT 24
Finished Aug 19 05:02:59 PM PDT 24
Peak memory 201212 kb
Host smart-39f72eaf-16b0-4a40-b44e-463b3673ffa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538045585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2538045585
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2751633100
Short name T49
Test name
Test status
Simulation time 353292678 ps
CPU time 2.45 seconds
Started Aug 19 05:02:53 PM PDT 24
Finished Aug 19 05:02:56 PM PDT 24
Peak memory 201196 kb
Host smart-b3698b0f-2d5b-4b05-a8d5-6aa4845ee911
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751633100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2751633100
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3285372397
Short name T335
Test name
Test status
Simulation time 4827946606 ps
CPU time 7.54 seconds
Started Aug 19 05:02:53 PM PDT 24
Finished Aug 19 05:03:01 PM PDT 24
Peak memory 201184 kb
Host smart-723a0bc4-776c-4d92-b15e-9257c310380a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285372397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3285372397
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2558218132
Short name T50
Test name
Test status
Simulation time 468085981 ps
CPU time 1.1 seconds
Started Aug 19 05:02:52 PM PDT 24
Finished Aug 19 05:02:53 PM PDT 24
Peak memory 201004 kb
Host smart-9bf7c6e0-51aa-4f1c-932f-1fdfc59e02a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558218132 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2558218132
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.301148778
Short name T911
Test name
Test status
Simulation time 528624664 ps
CPU time 1.92 seconds
Started Aug 19 05:02:55 PM PDT 24
Finished Aug 19 05:02:57 PM PDT 24
Peak memory 200912 kb
Host smart-8bf79747-9bca-4934-8860-1733810e852a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301148778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.301148778
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.266832677
Short name T806
Test name
Test status
Simulation time 461167678 ps
CPU time 0.93 seconds
Started Aug 19 05:02:56 PM PDT 24
Finished Aug 19 05:02:57 PM PDT 24
Peak memory 200872 kb
Host smart-6fd8ab36-91b8-4cf3-8e6e-29fc4ed43552
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266832677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.266832677
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3879202141
Short name T822
Test name
Test status
Simulation time 4954626086 ps
CPU time 6.01 seconds
Started Aug 19 05:02:54 PM PDT 24
Finished Aug 19 05:03:00 PM PDT 24
Peak memory 201096 kb
Host smart-140ae90c-3565-4ae8-b4f0-420b65745b6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879202141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3879202141
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.316197617
Short name T860
Test name
Test status
Simulation time 569705483 ps
CPU time 2.45 seconds
Started Aug 19 05:02:58 PM PDT 24
Finished Aug 19 05:03:01 PM PDT 24
Peak memory 217036 kb
Host smart-cc180032-a608-41ea-a99f-14b518a0aced
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316197617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.316197617
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3885888553
Short name T830
Test name
Test status
Simulation time 4166849236 ps
CPU time 3.96 seconds
Started Aug 19 05:02:53 PM PDT 24
Finished Aug 19 05:02:57 PM PDT 24
Peak memory 201180 kb
Host smart-a0d45986-0ec5-4a03-ab75-6df06958bd64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885888553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3885888553
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3170325788
Short name T913
Test name
Test status
Simulation time 430887030 ps
CPU time 1.08 seconds
Started Aug 19 05:03:05 PM PDT 24
Finished Aug 19 05:03:06 PM PDT 24
Peak memory 201000 kb
Host smart-7f4122c8-93f0-4f00-96a7-a4924a7173ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170325788 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3170325788
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.83433087
Short name T103
Test name
Test status
Simulation time 483558859 ps
CPU time 1.06 seconds
Started Aug 19 05:02:55 PM PDT 24
Finished Aug 19 05:02:56 PM PDT 24
Peak memory 200940 kb
Host smart-81f72619-6c9a-46bb-af4e-9761694f6208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83433087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.83433087
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1141442173
Short name T803
Test name
Test status
Simulation time 317046656 ps
CPU time 0.78 seconds
Started Aug 19 05:02:54 PM PDT 24
Finished Aug 19 05:02:55 PM PDT 24
Peak memory 200824 kb
Host smart-a7ce0e66-399b-4390-b3d2-dd931e0842a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141442173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1141442173
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3434494647
Short name T109
Test name
Test status
Simulation time 4542059712 ps
CPU time 3.66 seconds
Started Aug 19 05:03:09 PM PDT 24
Finished Aug 19 05:03:13 PM PDT 24
Peak memory 201136 kb
Host smart-e335fe5a-1a99-480e-bb08-1264b8503c09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434494647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3434494647
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.954618691
Short name T919
Test name
Test status
Simulation time 555132883 ps
CPU time 1.72 seconds
Started Aug 19 05:02:54 PM PDT 24
Finished Aug 19 05:02:56 PM PDT 24
Peak memory 201156 kb
Host smart-de2f533b-dbd9-4981-9853-8deb609e43c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954618691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.954618691
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3161398491
Short name T845
Test name
Test status
Simulation time 8971355438 ps
CPU time 12.93 seconds
Started Aug 19 05:02:55 PM PDT 24
Finished Aug 19 05:03:08 PM PDT 24
Peak memory 201176 kb
Host smart-f23f58e0-f273-4d86-a042-e48b3adefa83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161398491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3161398491
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2018321141
Short name T883
Test name
Test status
Simulation time 450067067 ps
CPU time 1.41 seconds
Started Aug 19 05:03:10 PM PDT 24
Finished Aug 19 05:03:11 PM PDT 24
Peak memory 201004 kb
Host smart-33a0b99e-1cd1-4bc6-a57f-ae251edbaa96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018321141 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2018321141
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3491182658
Short name T100
Test name
Test status
Simulation time 519820208 ps
CPU time 1.92 seconds
Started Aug 19 05:03:09 PM PDT 24
Finished Aug 19 05:03:11 PM PDT 24
Peak memory 200956 kb
Host smart-4f7f1077-00e9-41a4-a9fb-6a10bbe26d74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491182658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3491182658
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2583745579
Short name T838
Test name
Test status
Simulation time 461892926 ps
CPU time 1.13 seconds
Started Aug 19 05:03:04 PM PDT 24
Finished Aug 19 05:03:05 PM PDT 24
Peak memory 200864 kb
Host smart-8ad88a38-a47d-4879-8580-067cc72e5429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583745579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2583745579
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1453097427
Short name T113
Test name
Test status
Simulation time 4204189424 ps
CPU time 9.59 seconds
Started Aug 19 05:03:04 PM PDT 24
Finished Aug 19 05:03:14 PM PDT 24
Peak memory 201176 kb
Host smart-eee7467f-3ca8-4686-ab39-c10343c9ccc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453097427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1453097427
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1093623016
Short name T895
Test name
Test status
Simulation time 445561208 ps
CPU time 2.58 seconds
Started Aug 19 05:03:07 PM PDT 24
Finished Aug 19 05:03:09 PM PDT 24
Peak memory 201144 kb
Host smart-d3a32af9-974b-4ced-9e74-1e0395cde537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093623016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1093623016
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3150849332
Short name T334
Test name
Test status
Simulation time 4056897160 ps
CPU time 10.37 seconds
Started Aug 19 05:03:07 PM PDT 24
Finished Aug 19 05:03:18 PM PDT 24
Peak memory 201188 kb
Host smart-ad4e096e-c7a0-4a77-9132-5c9b782c1edc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150849332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3150849332
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3762836263
Short name T390
Test name
Test status
Simulation time 467190613 ps
CPU time 1.69 seconds
Started Aug 19 05:54:24 PM PDT 24
Finished Aug 19 05:54:26 PM PDT 24
Peak memory 202180 kb
Host smart-c0bf9260-224c-4af3-a4f5-ae5789f0a573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762836263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3762836263
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3209838105
Short name T167
Test name
Test status
Simulation time 336532135156 ps
CPU time 122.17 seconds
Started Aug 19 05:54:36 PM PDT 24
Finished Aug 19 05:56:39 PM PDT 24
Peak memory 202192 kb
Host smart-fb2cc5e3-0a69-4f87-8492-eaf1ce3104f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209838105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3209838105
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1991413948
Short name T736
Test name
Test status
Simulation time 159921167817 ps
CPU time 100.78 seconds
Started Aug 19 05:54:48 PM PDT 24
Finished Aug 19 05:56:29 PM PDT 24
Peak memory 202108 kb
Host smart-f2b434b6-da6a-4781-ab20-ae04d378c862
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991413948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1991413948
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1968311315
Short name T422
Test name
Test status
Simulation time 162640347003 ps
CPU time 50.48 seconds
Started Aug 19 05:54:57 PM PDT 24
Finished Aug 19 05:55:47 PM PDT 24
Peak memory 202156 kb
Host smart-264ecaba-be83-4147-bedc-9a3a26308928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968311315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1968311315
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3022215706
Short name T718
Test name
Test status
Simulation time 494687154799 ps
CPU time 1168.6 seconds
Started Aug 19 05:54:27 PM PDT 24
Finished Aug 19 06:13:56 PM PDT 24
Peak memory 202156 kb
Host smart-6fd1d951-fc5e-49a1-a9e3-7753861fdb38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022215706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3022215706
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.326411221
Short name T207
Test name
Test status
Simulation time 369036403120 ps
CPU time 217.92 seconds
Started Aug 19 05:54:59 PM PDT 24
Finished Aug 19 05:58:37 PM PDT 24
Peak memory 202144 kb
Host smart-5e1a0fed-7d9a-4457-a288-c82f220f00f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326411221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.326411221
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2212533217
Short name T516
Test name
Test status
Simulation time 395919134418 ps
CPU time 219.7 seconds
Started Aug 19 05:54:40 PM PDT 24
Finished Aug 19 05:58:20 PM PDT 24
Peak memory 202092 kb
Host smart-34e7d120-a2eb-4fd9-bf23-b87394d03816
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212533217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2212533217
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.462383339
Short name T574
Test name
Test status
Simulation time 110948380771 ps
CPU time 594.55 seconds
Started Aug 19 05:54:40 PM PDT 24
Finished Aug 19 06:04:35 PM PDT 24
Peak memory 202420 kb
Host smart-d2e57618-4f07-46d6-8551-4c6d6f344a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462383339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.462383339
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1783116290
Short name T369
Test name
Test status
Simulation time 32806423835 ps
CPU time 77.34 seconds
Started Aug 19 05:54:26 PM PDT 24
Finished Aug 19 05:55:44 PM PDT 24
Peak memory 201972 kb
Host smart-6837b3c6-0665-491c-9a79-7030bb31e2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783116290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1783116290
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3182299432
Short name T538
Test name
Test status
Simulation time 4019170608 ps
CPU time 5.68 seconds
Started Aug 19 05:54:39 PM PDT 24
Finished Aug 19 05:54:45 PM PDT 24
Peak memory 201864 kb
Host smart-51235071-b060-4dc6-a850-95cfbb2b1b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182299432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3182299432
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.4267779553
Short name T636
Test name
Test status
Simulation time 5972526061 ps
CPU time 11.22 seconds
Started Aug 19 05:54:45 PM PDT 24
Finished Aug 19 05:54:56 PM PDT 24
Peak memory 201968 kb
Host smart-5f873821-7f61-4ea5-abad-2c8a740b916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267779553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.4267779553
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.4236119143
Short name T14
Test name
Test status
Simulation time 3454713205 ps
CPU time 9.14 seconds
Started Aug 19 05:54:37 PM PDT 24
Finished Aug 19 05:54:47 PM PDT 24
Peak memory 202264 kb
Host smart-a72d344e-eeaa-4476-a648-30b4c99a63e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236119143 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.4236119143
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1109945414
Short name T685
Test name
Test status
Simulation time 323971716 ps
CPU time 1.32 seconds
Started Aug 19 05:55:02 PM PDT 24
Finished Aug 19 05:55:03 PM PDT 24
Peak memory 201972 kb
Host smart-c680666a-52ea-4fbf-91e4-72e90c825d11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109945414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1109945414
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.821054153
Short name T789
Test name
Test status
Simulation time 323078102244 ps
CPU time 90.82 seconds
Started Aug 19 05:54:49 PM PDT 24
Finished Aug 19 05:56:19 PM PDT 24
Peak memory 202172 kb
Host smart-f4943a25-a601-4528-a7b3-d19d89775185
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821054153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.821054153
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1134099273
Short name T726
Test name
Test status
Simulation time 164856704874 ps
CPU time 104.23 seconds
Started Aug 19 05:54:37 PM PDT 24
Finished Aug 19 05:56:21 PM PDT 24
Peak memory 202152 kb
Host smart-1c4ae5e8-a4a9-41ef-a9fd-d9c2a57fb77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134099273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1134099273
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1971206173
Short name T770
Test name
Test status
Simulation time 327957071728 ps
CPU time 731.91 seconds
Started Aug 19 05:54:55 PM PDT 24
Finished Aug 19 06:07:07 PM PDT 24
Peak memory 202140 kb
Host smart-c54bb0e7-0ecf-47be-bc71-34e2998b05fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971206173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1971206173
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2868398750
Short name T218
Test name
Test status
Simulation time 491178088779 ps
CPU time 1172 seconds
Started Aug 19 05:54:34 PM PDT 24
Finished Aug 19 06:14:06 PM PDT 24
Peak memory 202352 kb
Host smart-76c42b85-fbb7-4bf6-b298-702a96b4acba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868398750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2868398750
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3999393910
Short name T757
Test name
Test status
Simulation time 321856000183 ps
CPU time 350.02 seconds
Started Aug 19 05:54:29 PM PDT 24
Finished Aug 19 06:00:19 PM PDT 24
Peak memory 202100 kb
Host smart-511860c4-f42d-4b12-bfba-997f1787457c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999393910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3999393910
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3379893839
Short name T283
Test name
Test status
Simulation time 197977650718 ps
CPU time 213.65 seconds
Started Aug 19 05:54:42 PM PDT 24
Finished Aug 19 05:58:16 PM PDT 24
Peak memory 202176 kb
Host smart-0d783eca-dd15-4c45-b185-a9af190be87b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379893839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3379893839
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3772976115
Short name T500
Test name
Test status
Simulation time 387843195524 ps
CPU time 396.68 seconds
Started Aug 19 05:54:29 PM PDT 24
Finished Aug 19 06:01:06 PM PDT 24
Peak memory 202156 kb
Host smart-74cadda2-43d7-4ad6-9a08-87069a3dc590
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772976115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3772976115
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3613393907
Short name T450
Test name
Test status
Simulation time 76023560496 ps
CPU time 413.49 seconds
Started Aug 19 05:54:45 PM PDT 24
Finished Aug 19 06:01:38 PM PDT 24
Peak memory 202364 kb
Host smart-1031c03c-e411-41f9-8de4-781a15a59b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613393907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3613393907
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3477551329
Short name T378
Test name
Test status
Simulation time 36178891230 ps
CPU time 50.95 seconds
Started Aug 19 05:54:33 PM PDT 24
Finished Aug 19 05:55:24 PM PDT 24
Peak memory 201976 kb
Host smart-12f869bf-a948-41ed-8149-e282cb470aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477551329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3477551329
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.340474421
Short name T405
Test name
Test status
Simulation time 4308495963 ps
CPU time 1.95 seconds
Started Aug 19 05:54:36 PM PDT 24
Finished Aug 19 05:54:39 PM PDT 24
Peak memory 201964 kb
Host smart-3d8a7472-6c72-4397-8797-605adba329d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340474421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.340474421
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3368070119
Short name T44
Test name
Test status
Simulation time 8268810750 ps
CPU time 3.68 seconds
Started Aug 19 05:54:44 PM PDT 24
Finished Aug 19 05:54:48 PM PDT 24
Peak memory 218508 kb
Host smart-069d5f99-78e3-44c9-9197-1ffe16cc8145
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368070119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3368070119
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3212330554
Short name T485
Test name
Test status
Simulation time 5647214606 ps
CPU time 6.99 seconds
Started Aug 19 05:54:48 PM PDT 24
Finished Aug 19 05:54:58 PM PDT 24
Peak memory 202000 kb
Host smart-c4ed1259-0d0a-49a6-b904-2ca788096313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212330554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3212330554
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1517532678
Short name T142
Test name
Test status
Simulation time 323440459820 ps
CPU time 59.24 seconds
Started Aug 19 05:54:37 PM PDT 24
Finished Aug 19 05:55:36 PM PDT 24
Peak memory 202212 kb
Host smart-e4307a19-0d6a-496a-800e-cacacd6a8fdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517532678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1517532678
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3958170390
Short name T409
Test name
Test status
Simulation time 459494080 ps
CPU time 1.61 seconds
Started Aug 19 05:55:31 PM PDT 24
Finished Aug 19 05:55:32 PM PDT 24
Peak memory 202008 kb
Host smart-8edf6fb7-16c7-4a61-80b7-3b1df8540dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958170390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3958170390
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3801865075
Short name T230
Test name
Test status
Simulation time 498082051925 ps
CPU time 394.9 seconds
Started Aug 19 05:55:14 PM PDT 24
Finished Aug 19 06:01:49 PM PDT 24
Peak memory 202252 kb
Host smart-5030eb56-3994-45a9-99ee-c52e016c6d4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801865075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3801865075
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1473512135
Short name T573
Test name
Test status
Simulation time 162286665842 ps
CPU time 196.79 seconds
Started Aug 19 05:55:06 PM PDT 24
Finished Aug 19 05:58:23 PM PDT 24
Peak memory 202160 kb
Host smart-1dd0bf8b-ef59-49a2-b477-2df696365a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473512135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1473512135
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4063592310
Short name T468
Test name
Test status
Simulation time 165312697264 ps
CPU time 99.74 seconds
Started Aug 19 05:55:13 PM PDT 24
Finished Aug 19 05:56:53 PM PDT 24
Peak memory 202144 kb
Host smart-a869178b-b131-49d1-bb5f-24739f1de793
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063592310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.4063592310
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.4146391352
Short name T665
Test name
Test status
Simulation time 166403979367 ps
CPU time 148.53 seconds
Started Aug 19 05:55:13 PM PDT 24
Finished Aug 19 05:57:42 PM PDT 24
Peak memory 202164 kb
Host smart-64ed0a38-3ae5-4df5-8fb7-e81a8b65d7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146391352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.4146391352
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1771230454
Short name T754
Test name
Test status
Simulation time 166266793888 ps
CPU time 365.82 seconds
Started Aug 19 05:55:12 PM PDT 24
Finished Aug 19 06:01:18 PM PDT 24
Peak memory 202140 kb
Host smart-b893901b-3b5b-4c96-8698-47d39106e5f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771230454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1771230454
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3738265889
Short name T611
Test name
Test status
Simulation time 533525980740 ps
CPU time 1209.92 seconds
Started Aug 19 05:55:12 PM PDT 24
Finished Aug 19 06:15:22 PM PDT 24
Peak memory 202172 kb
Host smart-055e89c0-9fc6-4bae-b9a8-7e297239f373
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738265889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3738265889
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1441770852
Short name T528
Test name
Test status
Simulation time 199339562923 ps
CPU time 200.48 seconds
Started Aug 19 05:55:32 PM PDT 24
Finished Aug 19 05:58:52 PM PDT 24
Peak memory 202196 kb
Host smart-27d90a47-f8b1-4fa4-a163-ba38c5995337
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441770852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1441770852
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2532374133
Short name T367
Test name
Test status
Simulation time 47155565517 ps
CPU time 111.16 seconds
Started Aug 19 05:55:07 PM PDT 24
Finished Aug 19 05:56:58 PM PDT 24
Peak memory 201972 kb
Host smart-1e9cf806-f1e5-4466-ab80-12782290a69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532374133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2532374133
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1680284705
Short name T507
Test name
Test status
Simulation time 2905905982 ps
CPU time 2.19 seconds
Started Aug 19 05:55:16 PM PDT 24
Finished Aug 19 05:55:19 PM PDT 24
Peak memory 201976 kb
Host smart-8e968d7c-68f1-4a63-a614-33116806a959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680284705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1680284705
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2531922701
Short name T724
Test name
Test status
Simulation time 6014489307 ps
CPU time 4.95 seconds
Started Aug 19 05:55:14 PM PDT 24
Finished Aug 19 05:55:19 PM PDT 24
Peak memory 201928 kb
Host smart-2024d552-5ce1-47e4-b1e3-3fc07e0f7037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531922701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2531922701
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3523699663
Short name T322
Test name
Test status
Simulation time 209980110452 ps
CPU time 488.34 seconds
Started Aug 19 05:55:05 PM PDT 24
Finished Aug 19 06:03:14 PM PDT 24
Peak memory 202168 kb
Host smart-45f4faa5-5eef-4f79-8503-eb73c5f957b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523699663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3523699663
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2763127491
Short name T550
Test name
Test status
Simulation time 5912424491 ps
CPU time 6.91 seconds
Started Aug 19 05:55:29 PM PDT 24
Finished Aug 19 05:55:36 PM PDT 24
Peak memory 202124 kb
Host smart-72964e1a-5e13-41f6-a866-ef829cc8dc60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763127491 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2763127491
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3369474253
Short name T532
Test name
Test status
Simulation time 373082250 ps
CPU time 1.46 seconds
Started Aug 19 05:55:33 PM PDT 24
Finished Aug 19 05:55:35 PM PDT 24
Peak memory 202000 kb
Host smart-d16dafaa-18ba-4690-98a3-d4171dfbd000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369474253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3369474253
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.990137260
Short name T243
Test name
Test status
Simulation time 265711161132 ps
CPU time 284.87 seconds
Started Aug 19 05:55:15 PM PDT 24
Finished Aug 19 06:00:00 PM PDT 24
Peak memory 202224 kb
Host smart-4b37fe2a-641e-4f79-9ff3-b98b52401de4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990137260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.990137260
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1227961157
Short name T239
Test name
Test status
Simulation time 555203042576 ps
CPU time 634.01 seconds
Started Aug 19 05:55:06 PM PDT 24
Finished Aug 19 06:05:40 PM PDT 24
Peak memory 202192 kb
Host smart-60bfe397-5e9f-405c-a7c8-6d5aa62ed2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227961157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1227961157
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3112563675
Short name T277
Test name
Test status
Simulation time 489937380666 ps
CPU time 295.62 seconds
Started Aug 19 05:55:14 PM PDT 24
Finished Aug 19 06:00:10 PM PDT 24
Peak memory 202148 kb
Host smart-1ab6145a-ac66-4b8c-a03d-fe0d4865a6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112563675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3112563675
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3743876733
Short name T771
Test name
Test status
Simulation time 159735359909 ps
CPU time 373.16 seconds
Started Aug 19 05:55:31 PM PDT 24
Finished Aug 19 06:01:45 PM PDT 24
Peak memory 202144 kb
Host smart-11e9eb5c-0db2-4eae-ba01-590a31ef8f72
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743876733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3743876733
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.800756605
Short name T614
Test name
Test status
Simulation time 323299545093 ps
CPU time 726.28 seconds
Started Aug 19 05:55:07 PM PDT 24
Finished Aug 19 06:07:14 PM PDT 24
Peak memory 202112 kb
Host smart-66a229af-3c27-47d0-ba9a-847bc176456f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800756605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.800756605
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.164944224
Short name T680
Test name
Test status
Simulation time 164601130305 ps
CPU time 330.93 seconds
Started Aug 19 05:55:11 PM PDT 24
Finished Aug 19 06:00:42 PM PDT 24
Peak memory 202112 kb
Host smart-c8a7f732-b257-4563-a4e9-c5d41fdb00a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=164944224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.164944224
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.651357065
Short name T695
Test name
Test status
Simulation time 178955675455 ps
CPU time 107.67 seconds
Started Aug 19 05:55:15 PM PDT 24
Finished Aug 19 05:57:02 PM PDT 24
Peak memory 202160 kb
Host smart-b2de63b7-0860-415f-8bdd-6f9402e2161c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651357065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.651357065
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.16366273
Short name T743
Test name
Test status
Simulation time 402584105501 ps
CPU time 209.34 seconds
Started Aug 19 05:55:14 PM PDT 24
Finished Aug 19 05:58:43 PM PDT 24
Peak memory 202132 kb
Host smart-d5a0ab97-b230-4dbf-815d-1846fdfe85b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16366273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.a
dc_ctrl_filters_wakeup_fixed.16366273
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.4188913068
Short name T729
Test name
Test status
Simulation time 89371968462 ps
CPU time 293.39 seconds
Started Aug 19 05:55:14 PM PDT 24
Finished Aug 19 06:00:07 PM PDT 24
Peak memory 202400 kb
Host smart-bc48829d-4aa3-4c9a-933e-c31ded1f1267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188913068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.4188913068
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.4229960443
Short name T484
Test name
Test status
Simulation time 44709027051 ps
CPU time 100.3 seconds
Started Aug 19 05:55:08 PM PDT 24
Finished Aug 19 05:56:48 PM PDT 24
Peak memory 202000 kb
Host smart-03ad7e00-ef9c-4ebe-bdb4-d6342630c4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229960443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.4229960443
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1731994257
Short name T482
Test name
Test status
Simulation time 3540874153 ps
CPU time 8.28 seconds
Started Aug 19 05:55:14 PM PDT 24
Finished Aug 19 05:55:22 PM PDT 24
Peak memory 201992 kb
Host smart-8a1de192-bde7-4fe8-a8f0-5be85d560eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731994257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1731994257
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.492674997
Short name T510
Test name
Test status
Simulation time 5709981473 ps
CPU time 3.68 seconds
Started Aug 19 05:55:08 PM PDT 24
Finished Aug 19 05:55:12 PM PDT 24
Peak memory 201972 kb
Host smart-73ad7e24-f515-4779-bcb5-216a8192025e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492674997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.492674997
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3438469326
Short name T244
Test name
Test status
Simulation time 218335448112 ps
CPU time 127.21 seconds
Started Aug 19 05:55:06 PM PDT 24
Finished Aug 19 05:57:14 PM PDT 24
Peak memory 202180 kb
Host smart-8b28a8f6-0caf-41a4-9b48-b87230c86b5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438469326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3438469326
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.460629798
Short name T26
Test name
Test status
Simulation time 9274416683 ps
CPU time 5.08 seconds
Started Aug 19 05:55:11 PM PDT 24
Finished Aug 19 05:55:17 PM PDT 24
Peak memory 202328 kb
Host smart-39bed17d-78ac-4434-acd6-54c3b71be621
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460629798 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.460629798
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.28484879
Short name T217
Test name
Test status
Simulation time 325471146916 ps
CPU time 671.22 seconds
Started Aug 19 05:55:20 PM PDT 24
Finished Aug 19 06:06:31 PM PDT 24
Peak memory 202156 kb
Host smart-a85b8986-4e4b-458e-8152-0d97dcc13c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28484879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.28484879
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2027645183
Short name T313
Test name
Test status
Simulation time 488829080763 ps
CPU time 285.23 seconds
Started Aug 19 05:55:09 PM PDT 24
Finished Aug 19 05:59:54 PM PDT 24
Peak memory 202180 kb
Host smart-32e66494-7bf9-4756-ac27-7e0f80eca768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027645183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2027645183
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2886067558
Short name T133
Test name
Test status
Simulation time 164996235627 ps
CPU time 383.45 seconds
Started Aug 19 05:55:07 PM PDT 24
Finished Aug 19 06:01:30 PM PDT 24
Peak memory 202172 kb
Host smart-5c0ecc92-97f2-4d4d-871c-1c0fa619291b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886067558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2886067558
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.686069482
Short name T70
Test name
Test status
Simulation time 344521975002 ps
CPU time 190.28 seconds
Started Aug 19 05:55:16 PM PDT 24
Finished Aug 19 05:58:26 PM PDT 24
Peak memory 202164 kb
Host smart-48e09f18-6538-44ab-a57e-d5b1054de83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686069482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.686069482
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3029703848
Short name T426
Test name
Test status
Simulation time 327996746947 ps
CPU time 73.9 seconds
Started Aug 19 05:55:10 PM PDT 24
Finished Aug 19 05:56:24 PM PDT 24
Peak memory 202164 kb
Host smart-53eec3da-5f9b-4257-9e17-979871db10c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029703848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3029703848
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2418371225
Short name T525
Test name
Test status
Simulation time 193246674936 ps
CPU time 460.91 seconds
Started Aug 19 05:55:17 PM PDT 24
Finished Aug 19 06:02:58 PM PDT 24
Peak memory 202148 kb
Host smart-f874a2c5-1b66-408a-a8f9-f6c6264a4e3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418371225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2418371225
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1694633087
Short name T479
Test name
Test status
Simulation time 195911264676 ps
CPU time 30.91 seconds
Started Aug 19 05:55:14 PM PDT 24
Finished Aug 19 05:55:45 PM PDT 24
Peak memory 202136 kb
Host smart-f254a715-be58-41a3-8ea8-2cc7e334a291
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694633087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1694633087
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.682661689
Short name T496
Test name
Test status
Simulation time 131047676553 ps
CPU time 503.6 seconds
Started Aug 19 05:55:13 PM PDT 24
Finished Aug 19 06:03:37 PM PDT 24
Peak memory 202456 kb
Host smart-b234d367-00a6-4a61-b213-cbd129c7c034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682661689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.682661689
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3875901028
Short name T646
Test name
Test status
Simulation time 31608521382 ps
CPU time 35.15 seconds
Started Aug 19 05:55:04 PM PDT 24
Finished Aug 19 05:55:40 PM PDT 24
Peak memory 201976 kb
Host smart-095b9a26-301e-4802-a0a4-e08ac2e581bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875901028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3875901028
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3962683148
Short name T448
Test name
Test status
Simulation time 5040340494 ps
CPU time 3.83 seconds
Started Aug 19 05:55:19 PM PDT 24
Finished Aug 19 05:55:23 PM PDT 24
Peak memory 201980 kb
Host smart-fc3f5190-ebea-4077-987b-3c17003e3304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962683148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3962683148
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3484875845
Short name T116
Test name
Test status
Simulation time 5699456515 ps
CPU time 6.33 seconds
Started Aug 19 05:55:13 PM PDT 24
Finished Aug 19 05:55:19 PM PDT 24
Peak memory 202012 kb
Host smart-825ccdee-2a22-46f5-a9c2-ea0e6f0cc891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484875845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3484875845
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2408186823
Short name T279
Test name
Test status
Simulation time 327302057362 ps
CPU time 119.08 seconds
Started Aug 19 05:55:05 PM PDT 24
Finished Aug 19 05:57:04 PM PDT 24
Peak memory 202132 kb
Host smart-34b8c2e0-1069-4a62-8420-dbfa38395e7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408186823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2408186823
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2676327806
Short name T399
Test name
Test status
Simulation time 1697169597 ps
CPU time 6.73 seconds
Started Aug 19 05:55:08 PM PDT 24
Finished Aug 19 05:55:15 PM PDT 24
Peak memory 202052 kb
Host smart-e42fbe15-be40-43ec-8261-0e8ad9454f2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676327806 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2676327806
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2980327122
Short name T629
Test name
Test status
Simulation time 311799271 ps
CPU time 1.41 seconds
Started Aug 19 05:55:19 PM PDT 24
Finished Aug 19 05:55:21 PM PDT 24
Peak memory 202000 kb
Host smart-ecd645b6-bfd2-457a-b129-cec5434f230b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980327122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2980327122
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1895769052
Short name T295
Test name
Test status
Simulation time 347015335277 ps
CPU time 560.31 seconds
Started Aug 19 05:55:26 PM PDT 24
Finished Aug 19 06:04:46 PM PDT 24
Peak memory 202156 kb
Host smart-66df5399-a195-4856-bc72-b42795177a2f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895769052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1895769052
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3806487883
Short name T163
Test name
Test status
Simulation time 507130261500 ps
CPU time 228.47 seconds
Started Aug 19 05:55:19 PM PDT 24
Finished Aug 19 05:59:08 PM PDT 24
Peak memory 202236 kb
Host smart-1332be12-14c8-441e-a84a-9dbf2f0bac5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806487883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3806487883
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1881482466
Short name T737
Test name
Test status
Simulation time 325679844416 ps
CPU time 770.23 seconds
Started Aug 19 05:55:08 PM PDT 24
Finished Aug 19 06:07:58 PM PDT 24
Peak memory 202196 kb
Host smart-c4d3b180-e681-4dfd-a0aa-add80a350797
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881482466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1881482466
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.591302466
Short name T469
Test name
Test status
Simulation time 167637729554 ps
CPU time 93.63 seconds
Started Aug 19 05:55:07 PM PDT 24
Finished Aug 19 05:56:41 PM PDT 24
Peak memory 202136 kb
Host smart-8d8c6ebf-fbd8-4377-a08c-270f56c07ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591302466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.591302466
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2560716157
Short name T497
Test name
Test status
Simulation time 499822659502 ps
CPU time 278.49 seconds
Started Aug 19 05:55:16 PM PDT 24
Finished Aug 19 05:59:55 PM PDT 24
Peak memory 202140 kb
Host smart-e667c50e-1f33-42ba-9d96-3caa7d8d40c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560716157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2560716157
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2698563720
Short name T408
Test name
Test status
Simulation time 394386600300 ps
CPU time 833.18 seconds
Started Aug 19 05:55:10 PM PDT 24
Finished Aug 19 06:09:03 PM PDT 24
Peak memory 202140 kb
Host smart-5de83c7e-8b1d-4d9d-941a-0f561efdedf0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698563720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2698563720
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3009674694
Short name T354
Test name
Test status
Simulation time 34260114030 ps
CPU time 72.12 seconds
Started Aug 19 05:55:13 PM PDT 24
Finished Aug 19 05:56:25 PM PDT 24
Peak memory 201996 kb
Host smart-ebfac433-49ee-4ea7-9b48-5c1f780ab625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009674694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3009674694
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.4110907139
Short name T545
Test name
Test status
Simulation time 4233644129 ps
CPU time 10.4 seconds
Started Aug 19 05:55:09 PM PDT 24
Finished Aug 19 05:55:20 PM PDT 24
Peak memory 201968 kb
Host smart-e33bc51d-d01b-4e87-824e-65f9dae00b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110907139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.4110907139
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.711896687
Short name T543
Test name
Test status
Simulation time 5929662165 ps
CPU time 5.14 seconds
Started Aug 19 05:55:22 PM PDT 24
Finished Aug 19 05:55:27 PM PDT 24
Peak memory 201980 kb
Host smart-c0768d5d-bd83-4a78-8d8a-6678e8d50cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711896687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.711896687
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3504236090
Short name T625
Test name
Test status
Simulation time 181905705063 ps
CPU time 389.63 seconds
Started Aug 19 05:55:15 PM PDT 24
Finished Aug 19 06:01:45 PM PDT 24
Peak memory 202140 kb
Host smart-2837fd7b-ea48-40f6-90f5-5a3abc7de784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504236090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3504236090
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2168371547
Short name T28
Test name
Test status
Simulation time 928219803 ps
CPU time 3.03 seconds
Started Aug 19 05:55:21 PM PDT 24
Finished Aug 19 05:55:24 PM PDT 24
Peak memory 202020 kb
Host smart-0a1d5799-e649-437f-bdae-1d70905a2258
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168371547 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2168371547
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2594472413
Short name T439
Test name
Test status
Simulation time 570408429 ps
CPU time 0.82 seconds
Started Aug 19 05:55:20 PM PDT 24
Finished Aug 19 05:55:21 PM PDT 24
Peak memory 201884 kb
Host smart-b1d728a3-adc7-4ed4-9283-fd4122695f8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594472413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2594472413
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2169932720
Short name T635
Test name
Test status
Simulation time 350500138701 ps
CPU time 38.68 seconds
Started Aug 19 05:55:24 PM PDT 24
Finished Aug 19 05:56:03 PM PDT 24
Peak memory 202140 kb
Host smart-21d3bc3f-fa8c-4119-878f-6a95dc769018
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169932720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2169932720
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1607561353
Short name T555
Test name
Test status
Simulation time 192292155938 ps
CPU time 28.95 seconds
Started Aug 19 05:55:12 PM PDT 24
Finished Aug 19 05:55:41 PM PDT 24
Peak memory 202136 kb
Host smart-b4835aa4-5f3e-489e-a04c-529ad07093ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607561353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1607561353
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.687517589
Short name T120
Test name
Test status
Simulation time 164097408200 ps
CPU time 39.61 seconds
Started Aug 19 05:55:10 PM PDT 24
Finished Aug 19 05:55:50 PM PDT 24
Peak memory 202192 kb
Host smart-20c339e3-3e1a-4826-9884-6bb05ef62e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687517589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.687517589
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3362735948
Short name T471
Test name
Test status
Simulation time 488686320046 ps
CPU time 1126.74 seconds
Started Aug 19 05:55:08 PM PDT 24
Finished Aug 19 06:13:55 PM PDT 24
Peak memory 202124 kb
Host smart-5b6c9602-9533-4f42-9bf4-ed703ba6d780
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362735948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3362735948
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2717599824
Short name T404
Test name
Test status
Simulation time 327235570495 ps
CPU time 742.06 seconds
Started Aug 19 05:55:18 PM PDT 24
Finished Aug 19 06:07:41 PM PDT 24
Peak memory 202132 kb
Host smart-d3183938-2bd5-48d7-ab30-9aaf77ac79bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717599824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2717599824
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2002046073
Short name T443
Test name
Test status
Simulation time 487429143386 ps
CPU time 292.61 seconds
Started Aug 19 05:55:13 PM PDT 24
Finished Aug 19 06:00:06 PM PDT 24
Peak memory 202140 kb
Host smart-915579f3-2e80-4d9d-b004-13f4c2789fb9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002046073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2002046073
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.962524152
Short name T715
Test name
Test status
Simulation time 177663145880 ps
CPU time 410.14 seconds
Started Aug 19 05:55:16 PM PDT 24
Finished Aug 19 06:02:06 PM PDT 24
Peak memory 202224 kb
Host smart-dc122c01-a6ba-424b-9192-933bf4b0aabc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962524152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.962524152
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1634288772
Short name T797
Test name
Test status
Simulation time 591489369974 ps
CPU time 1314.77 seconds
Started Aug 19 05:55:18 PM PDT 24
Finished Aug 19 06:17:13 PM PDT 24
Peak memory 202156 kb
Host smart-d64248bd-7943-45c1-9281-a6c416c03d12
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634288772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1634288772
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3179089178
Short name T694
Test name
Test status
Simulation time 25793542409 ps
CPU time 11.25 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 05:55:39 PM PDT 24
Peak memory 201984 kb
Host smart-8f2b6b7b-2b33-4deb-87d7-719e28ff9666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179089178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3179089178
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3116918023
Short name T576
Test name
Test status
Simulation time 5476718159 ps
CPU time 6.22 seconds
Started Aug 19 05:55:13 PM PDT 24
Finished Aug 19 05:55:19 PM PDT 24
Peak memory 201996 kb
Host smart-3f828bad-8442-45ba-a022-06842cca203b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116918023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3116918023
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3225350229
Short name T411
Test name
Test status
Simulation time 5927002936 ps
CPU time 14.46 seconds
Started Aug 19 05:55:11 PM PDT 24
Finished Aug 19 05:55:26 PM PDT 24
Peak memory 201976 kb
Host smart-12d19fb5-e5fd-45fe-b607-5ea1833d07e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225350229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3225350229
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2907868903
Short name T461
Test name
Test status
Simulation time 8232236837 ps
CPU time 2.94 seconds
Started Aug 19 05:55:16 PM PDT 24
Finished Aug 19 05:55:19 PM PDT 24
Peak memory 201996 kb
Host smart-a905d73b-fc2b-4c2f-bb1c-3a0fc44c3460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907868903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2907868903
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.643263151
Short name T570
Test name
Test status
Simulation time 182120461874 ps
CPU time 24.76 seconds
Started Aug 19 05:55:12 PM PDT 24
Finished Aug 19 05:55:37 PM PDT 24
Peak memory 217908 kb
Host smart-3b5839f3-eff9-4e6b-bbb6-7282f924332e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643263151 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.643263151
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2905197958
Short name T60
Test name
Test status
Simulation time 344571333 ps
CPU time 1.45 seconds
Started Aug 19 05:55:10 PM PDT 24
Finished Aug 19 05:55:12 PM PDT 24
Peak memory 201996 kb
Host smart-46e73892-7290-4324-8144-383291b730f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905197958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2905197958
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1655668021
Short name T662
Test name
Test status
Simulation time 519566520501 ps
CPU time 1050.26 seconds
Started Aug 19 05:55:17 PM PDT 24
Finished Aug 19 06:12:47 PM PDT 24
Peak memory 202120 kb
Host smart-e776afcc-9fe5-452a-b5fa-8fead5334b8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655668021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1655668021
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.555870672
Short name T213
Test name
Test status
Simulation time 162920210457 ps
CPU time 358.38 seconds
Started Aug 19 05:55:11 PM PDT 24
Finished Aug 19 06:01:09 PM PDT 24
Peak memory 202196 kb
Host smart-8aca091e-e9e4-40dc-b11c-fdde3def6cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555870672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.555870672
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.589126289
Short name T684
Test name
Test status
Simulation time 503427703443 ps
CPU time 1138.74 seconds
Started Aug 19 05:55:15 PM PDT 24
Finished Aug 19 06:14:14 PM PDT 24
Peak memory 202148 kb
Host smart-1cef6e8f-d2c8-48e9-bcd0-23757bc7c3c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=589126289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.589126289
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.427382993
Short name T553
Test name
Test status
Simulation time 155735994511 ps
CPU time 72.94 seconds
Started Aug 19 05:55:09 PM PDT 24
Finished Aug 19 05:56:22 PM PDT 24
Peak memory 202144 kb
Host smart-d5dbfc0e-ae18-49b5-9ebd-fc79e129678e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427382993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.427382993
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1015286136
Short name T349
Test name
Test status
Simulation time 164323935981 ps
CPU time 79.45 seconds
Started Aug 19 05:55:24 PM PDT 24
Finished Aug 19 05:56:43 PM PDT 24
Peak memory 202124 kb
Host smart-ed64a0cf-d17c-42c2-8105-1bb87afa0f09
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015286136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1015286136
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.617260048
Short name T125
Test name
Test status
Simulation time 360088449183 ps
CPU time 759.26 seconds
Started Aug 19 05:55:10 PM PDT 24
Finished Aug 19 06:07:49 PM PDT 24
Peak memory 202116 kb
Host smart-65933dbb-ddc8-4a80-aa99-ddaea82e06d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617260048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.617260048
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.4230209524
Short name T727
Test name
Test status
Simulation time 405705654865 ps
CPU time 959.97 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 06:11:29 PM PDT 24
Peak memory 202172 kb
Host smart-e23bc39d-bacb-42ae-b049-1f70fe90b49c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230209524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.4230209524
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1283063616
Short name T544
Test name
Test status
Simulation time 78346604737 ps
CPU time 405.11 seconds
Started Aug 19 05:55:22 PM PDT 24
Finished Aug 19 06:02:08 PM PDT 24
Peak memory 202388 kb
Host smart-0ee6ef5a-d02a-42ee-963f-eb5dfcb74cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283063616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1283063616
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1886725247
Short name T474
Test name
Test status
Simulation time 40198383586 ps
CPU time 38.27 seconds
Started Aug 19 05:55:18 PM PDT 24
Finished Aug 19 05:55:56 PM PDT 24
Peak memory 201940 kb
Host smart-342d595d-212f-41f5-84d6-a6c1c0440353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886725247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1886725247
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3914876330
Short name T756
Test name
Test status
Simulation time 5472999414 ps
CPU time 6.89 seconds
Started Aug 19 05:55:17 PM PDT 24
Finished Aug 19 05:55:24 PM PDT 24
Peak memory 201968 kb
Host smart-223d90aa-c072-41c1-9133-795160413a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914876330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3914876330
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1099548604
Short name T558
Test name
Test status
Simulation time 5809450995 ps
CPU time 15.25 seconds
Started Aug 19 05:55:13 PM PDT 24
Finished Aug 19 05:55:28 PM PDT 24
Peak memory 201976 kb
Host smart-9a42b7f4-1fe6-47ae-9345-1074712eafb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099548604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1099548604
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1180980486
Short name T129
Test name
Test status
Simulation time 308994052909 ps
CPU time 756.07 seconds
Started Aug 19 05:55:11 PM PDT 24
Finished Aug 19 06:07:47 PM PDT 24
Peak memory 202392 kb
Host smart-946204b2-29cc-442a-b917-3e3b8d65dc3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180980486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1180980486
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.4074317875
Short name T603
Test name
Test status
Simulation time 33845645074 ps
CPU time 18.76 seconds
Started Aug 19 05:55:37 PM PDT 24
Finished Aug 19 05:55:56 PM PDT 24
Peak memory 218476 kb
Host smart-9a32ba67-1460-4c98-aaf4-183315436d01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074317875 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.4074317875
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3938377745
Short name T89
Test name
Test status
Simulation time 492412644 ps
CPU time 1.16 seconds
Started Aug 19 05:55:22 PM PDT 24
Finished Aug 19 05:55:24 PM PDT 24
Peak memory 202008 kb
Host smart-f614f7c2-1914-4646-9cdc-c19f684d8a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938377745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3938377745
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1404100814
Short name T327
Test name
Test status
Simulation time 202483364708 ps
CPU time 193.1 seconds
Started Aug 19 05:55:30 PM PDT 24
Finished Aug 19 05:58:43 PM PDT 24
Peak memory 202264 kb
Host smart-4549b315-ea40-48a2-b84a-9c52e84bd3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404100814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1404100814
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2919445686
Short name T466
Test name
Test status
Simulation time 335402427880 ps
CPU time 123.09 seconds
Started Aug 19 05:55:13 PM PDT 24
Finished Aug 19 05:57:16 PM PDT 24
Peak memory 202184 kb
Host smart-3dfb3166-37af-4057-9a23-f1c924b6f6ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919445686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2919445686
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1545707556
Short name T169
Test name
Test status
Simulation time 337139372398 ps
CPU time 197.9 seconds
Started Aug 19 05:55:31 PM PDT 24
Finished Aug 19 05:58:49 PM PDT 24
Peak memory 202032 kb
Host smart-d6abef77-71e9-481b-b40d-690b42f6f5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545707556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1545707556
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2004855399
Short name T505
Test name
Test status
Simulation time 166240279039 ps
CPU time 90.32 seconds
Started Aug 19 05:55:18 PM PDT 24
Finished Aug 19 05:56:48 PM PDT 24
Peak memory 202120 kb
Host smart-04ab0d3b-4846-42c7-be1c-a86fbf383e01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004855399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2004855399
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1506285733
Short name T542
Test name
Test status
Simulation time 605758682315 ps
CPU time 1280.07 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 06:16:48 PM PDT 24
Peak memory 202144 kb
Host smart-a3e7896a-d3c2-4ee6-b34f-16db8c7d632e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506285733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1506285733
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2452811360
Short name T342
Test name
Test status
Simulation time 70703803810 ps
CPU time 383.32 seconds
Started Aug 19 05:55:47 PM PDT 24
Finished Aug 19 06:02:10 PM PDT 24
Peak memory 202276 kb
Host smart-1c2954b7-6028-4519-8532-e540cf8f9253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452811360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2452811360
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.792694766
Short name T449
Test name
Test status
Simulation time 23074685063 ps
CPU time 13.9 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 05:55:42 PM PDT 24
Peak memory 201968 kb
Host smart-fc31ab9f-436b-401c-a713-ab1236feace8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792694766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.792694766
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3847637448
Short name T431
Test name
Test status
Simulation time 3612227002 ps
CPU time 8.94 seconds
Started Aug 19 05:55:16 PM PDT 24
Finished Aug 19 05:55:26 PM PDT 24
Peak memory 201964 kb
Host smart-6a8634ef-b2a4-4580-94c9-73019ae6394e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847637448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3847637448
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1769260143
Short name T647
Test name
Test status
Simulation time 5797389036 ps
CPU time 13.96 seconds
Started Aug 19 05:55:16 PM PDT 24
Finished Aug 19 05:55:30 PM PDT 24
Peak memory 201980 kb
Host smart-38415763-0386-473e-af65-30fb2db86cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769260143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1769260143
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.4001460035
Short name T677
Test name
Test status
Simulation time 274192663087 ps
CPU time 583.63 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 06:05:12 PM PDT 24
Peak memory 213308 kb
Host smart-ce32f684-0a77-4f7b-aa8e-be7433cfd1a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001460035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.4001460035
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2807692268
Short name T325
Test name
Test status
Simulation time 6118728532 ps
CPU time 7.53 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 05:55:35 PM PDT 24
Peak memory 200844 kb
Host smart-b7d9a9d6-49c5-4ad1-a13d-4f7c40097c36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807692268 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2807692268
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3459415887
Short name T350
Test name
Test status
Simulation time 416795303 ps
CPU time 0.98 seconds
Started Aug 19 05:55:16 PM PDT 24
Finished Aug 19 05:55:17 PM PDT 24
Peak memory 202032 kb
Host smart-a524f851-653c-460e-8e2e-0fa16574440e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459415887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3459415887
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.308709755
Short name T513
Test name
Test status
Simulation time 190071619137 ps
CPU time 211.44 seconds
Started Aug 19 05:55:26 PM PDT 24
Finished Aug 19 05:58:57 PM PDT 24
Peak memory 202152 kb
Host smart-9e8e8fa2-84cf-425a-8612-4a2607c3ac91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308709755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.308709755
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1358697863
Short name T130
Test name
Test status
Simulation time 164447020808 ps
CPU time 99.08 seconds
Started Aug 19 05:55:33 PM PDT 24
Finished Aug 19 05:57:12 PM PDT 24
Peak memory 202128 kb
Host smart-71ad66aa-930b-4670-807f-552de219484c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358697863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1358697863
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1531879182
Short name T559
Test name
Test status
Simulation time 325563518310 ps
CPU time 179.9 seconds
Started Aug 19 05:56:47 PM PDT 24
Finished Aug 19 05:59:47 PM PDT 24
Peak memory 202160 kb
Host smart-00c8b5df-8cf8-4291-abac-0364696c5a2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531879182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1531879182
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1370254608
Short name T716
Test name
Test status
Simulation time 490792985318 ps
CPU time 148.9 seconds
Started Aug 19 05:55:27 PM PDT 24
Finished Aug 19 05:57:56 PM PDT 24
Peak memory 202160 kb
Host smart-121fadeb-6980-41f3-99ea-19920c251346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370254608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1370254608
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2439295663
Short name T383
Test name
Test status
Simulation time 484277746611 ps
CPU time 290.96 seconds
Started Aug 19 05:55:19 PM PDT 24
Finished Aug 19 06:00:10 PM PDT 24
Peak memory 202140 kb
Host smart-bfc11563-81f6-4d23-aa75-cd620d158a46
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439295663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2439295663
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3622537233
Short name T225
Test name
Test status
Simulation time 200531096905 ps
CPU time 117.09 seconds
Started Aug 19 05:55:23 PM PDT 24
Finished Aug 19 05:57:20 PM PDT 24
Peak memory 202184 kb
Host smart-a087f7df-3804-40e5-be22-e4625a6bdc0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622537233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3622537233
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3374744489
Short name T660
Test name
Test status
Simulation time 396118839389 ps
CPU time 222.21 seconds
Started Aug 19 05:55:25 PM PDT 24
Finished Aug 19 05:59:08 PM PDT 24
Peak memory 202156 kb
Host smart-13fedc92-74c6-407d-b1af-0e9e5090baa7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374744489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3374744489
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.54314241
Short name T798
Test name
Test status
Simulation time 39676583668 ps
CPU time 10.63 seconds
Started Aug 19 05:55:22 PM PDT 24
Finished Aug 19 05:55:33 PM PDT 24
Peak memory 201968 kb
Host smart-1db63441-0ebf-429f-86a8-08dbabfbeda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54314241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.54314241
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.218666190
Short name T738
Test name
Test status
Simulation time 4908463380 ps
CPU time 1.45 seconds
Started Aug 19 05:55:30 PM PDT 24
Finished Aug 19 05:55:31 PM PDT 24
Peak memory 202036 kb
Host smart-aeead0c1-9961-463d-a6de-098fc164cac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218666190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.218666190
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.953705712
Short name T427
Test name
Test status
Simulation time 6016910750 ps
CPU time 4.59 seconds
Started Aug 19 05:55:27 PM PDT 24
Finished Aug 19 05:55:32 PM PDT 24
Peak memory 201980 kb
Host smart-78903e80-22f2-4ea5-9784-adf824c31020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953705712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.953705712
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.4220997775
Short name T22
Test name
Test status
Simulation time 337086420310 ps
CPU time 358.64 seconds
Started Aug 19 05:55:20 PM PDT 24
Finished Aug 19 06:01:19 PM PDT 24
Peak memory 202184 kb
Host smart-af3f891b-70bf-4d6c-8360-204a1ed705b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220997775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.4220997775
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.334893585
Short name T20
Test name
Test status
Simulation time 9151347057 ps
CPU time 11.26 seconds
Started Aug 19 05:55:09 PM PDT 24
Finished Aug 19 05:55:20 PM PDT 24
Peak memory 210488 kb
Host smart-32a879b4-6272-40ad-a6f8-b970e3b88110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334893585 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.334893585
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.4151716881
Short name T4
Test name
Test status
Simulation time 520540029 ps
CPU time 1.8 seconds
Started Aug 19 05:55:18 PM PDT 24
Finished Aug 19 05:55:20 PM PDT 24
Peak memory 201968 kb
Host smart-939d3453-7ee0-4dd8-8252-7b5543718ee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151716881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.4151716881
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1821108979
Short name T626
Test name
Test status
Simulation time 356879119488 ps
CPU time 124.69 seconds
Started Aug 19 05:55:27 PM PDT 24
Finished Aug 19 05:57:32 PM PDT 24
Peak memory 202208 kb
Host smart-f2822d55-8171-4ccb-b45d-82a4355ef662
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821108979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1821108979
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2012685022
Short name T616
Test name
Test status
Simulation time 324943389460 ps
CPU time 342.63 seconds
Started Aug 19 05:55:20 PM PDT 24
Finished Aug 19 06:01:03 PM PDT 24
Peak memory 202212 kb
Host smart-bb37ac0a-14cf-4f5a-b024-505c73964b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012685022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2012685022
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1451904695
Short name T453
Test name
Test status
Simulation time 498931413226 ps
CPU time 1125.56 seconds
Started Aug 19 05:55:23 PM PDT 24
Finished Aug 19 06:14:08 PM PDT 24
Peak memory 202036 kb
Host smart-ad9d658e-37db-4873-be47-853eef0ef551
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451904695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1451904695
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.604086433
Short name T547
Test name
Test status
Simulation time 200992587213 ps
CPU time 272.36 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 06:00:00 PM PDT 24
Peak memory 202120 kb
Host smart-4fffef17-b955-4e75-b7a2-3dceea526161
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604086433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.604086433
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.279939338
Short name T412
Test name
Test status
Simulation time 36364420715 ps
CPU time 37.97 seconds
Started Aug 19 05:55:27 PM PDT 24
Finished Aug 19 05:56:05 PM PDT 24
Peak memory 201948 kb
Host smart-02fbea52-dfbe-4060-9448-7e2ff8ff0b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279939338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.279939338
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2788580449
Short name T400
Test name
Test status
Simulation time 5204793329 ps
CPU time 2.04 seconds
Started Aug 19 05:55:41 PM PDT 24
Finished Aug 19 05:55:44 PM PDT 24
Peak memory 201984 kb
Host smart-16199c0a-467b-408d-906a-edbd77cda167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788580449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2788580449
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2223191569
Short name T348
Test name
Test status
Simulation time 5751246143 ps
CPU time 13.68 seconds
Started Aug 19 05:55:27 PM PDT 24
Finished Aug 19 05:55:40 PM PDT 24
Peak memory 201936 kb
Host smart-5fafc390-083b-49f6-879e-fb1ebbaa29e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223191569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2223191569
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3964456804
Short name T606
Test name
Test status
Simulation time 3837180035 ps
CPU time 3.57 seconds
Started Aug 19 05:55:20 PM PDT 24
Finished Aug 19 05:55:24 PM PDT 24
Peak memory 202148 kb
Host smart-7f2cc40a-a3ee-496d-8a03-253f0eaf813f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964456804 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3964456804
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.398584848
Short name T416
Test name
Test status
Simulation time 481674298 ps
CPU time 0.73 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 05:55:29 PM PDT 24
Peak memory 201992 kb
Host smart-f9eed18b-8e5a-4ce7-a60b-d6280e291e4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398584848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.398584848
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3197588044
Short name T769
Test name
Test status
Simulation time 171747817327 ps
CPU time 316.69 seconds
Started Aug 19 05:55:25 PM PDT 24
Finished Aug 19 06:00:41 PM PDT 24
Peak memory 202148 kb
Host smart-c3a325f5-bf86-46c6-85be-d6627da90c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197588044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3197588044
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1297625018
Short name T240
Test name
Test status
Simulation time 325145452590 ps
CPU time 121.1 seconds
Started Aug 19 05:55:19 PM PDT 24
Finished Aug 19 05:57:21 PM PDT 24
Peak memory 202160 kb
Host smart-f464ba32-a3a1-4277-a2f2-c5e35eff9d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297625018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1297625018
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2606924453
Short name T608
Test name
Test status
Simulation time 490160299823 ps
CPU time 1114.53 seconds
Started Aug 19 05:55:34 PM PDT 24
Finished Aug 19 06:14:09 PM PDT 24
Peak memory 202188 kb
Host smart-602b3361-5ffe-4d3a-b138-365452e699db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606924453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2606924453
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3071033458
Short name T81
Test name
Test status
Simulation time 486395278199 ps
CPU time 1186.57 seconds
Started Aug 19 05:55:30 PM PDT 24
Finished Aug 19 06:15:17 PM PDT 24
Peak memory 202184 kb
Host smart-1d592432-b46a-448c-926c-bfc88703fb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071033458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3071033458
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2041195769
Short name T135
Test name
Test status
Simulation time 168070799767 ps
CPU time 68.28 seconds
Started Aug 19 05:55:08 PM PDT 24
Finished Aug 19 05:56:16 PM PDT 24
Peak memory 202140 kb
Host smart-fe1d8411-ade6-40e7-884c-e668bfa42785
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041195769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2041195769
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1472974660
Short name T711
Test name
Test status
Simulation time 334874751720 ps
CPU time 182.83 seconds
Started Aug 19 05:55:32 PM PDT 24
Finished Aug 19 05:58:35 PM PDT 24
Peak memory 200684 kb
Host smart-37f3b7a8-9474-4ab0-ba1f-aae15d80998b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472974660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1472974660
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1736332276
Short name T571
Test name
Test status
Simulation time 395467415803 ps
CPU time 173.63 seconds
Started Aug 19 05:55:23 PM PDT 24
Finished Aug 19 05:58:17 PM PDT 24
Peak memory 202176 kb
Host smart-38ae0d81-fd2a-4a6f-a6ce-cbbdc2cee69e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736332276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1736332276
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3626246979
Short name T200
Test name
Test status
Simulation time 93175078264 ps
CPU time 380.07 seconds
Started Aug 19 05:55:38 PM PDT 24
Finished Aug 19 06:01:58 PM PDT 24
Peak memory 202408 kb
Host smart-0523c4a0-d5e9-43ac-9dca-6a7b2aab0ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626246979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3626246979
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1470572471
Short name T689
Test name
Test status
Simulation time 46043692017 ps
CPU time 51.9 seconds
Started Aug 19 05:55:17 PM PDT 24
Finished Aug 19 05:56:09 PM PDT 24
Peak memory 202000 kb
Host smart-18ac0fef-a46b-4e97-9a67-0ca85e727a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470572471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1470572471
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.124386633
Short name T417
Test name
Test status
Simulation time 5804138271 ps
CPU time 6.7 seconds
Started Aug 19 05:55:25 PM PDT 24
Finished Aug 19 05:55:32 PM PDT 24
Peak memory 201956 kb
Host smart-0152f44e-69ef-4d52-a9c3-9a0f80ded190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124386633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.124386633
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2059440388
Short name T353
Test name
Test status
Simulation time 5969577811 ps
CPU time 15.83 seconds
Started Aug 19 05:55:29 PM PDT 24
Finished Aug 19 05:55:45 PM PDT 24
Peak memory 201992 kb
Host smart-4102a9cd-7300-4b10-8305-e771bfe5435f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059440388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2059440388
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3559311680
Short name T690
Test name
Test status
Simulation time 218817173479 ps
CPU time 261.35 seconds
Started Aug 19 05:55:22 PM PDT 24
Finished Aug 19 05:59:43 PM PDT 24
Peak memory 202160 kb
Host smart-ba0160ae-070c-49d2-b6be-6c62bcab34ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559311680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3559311680
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2842467658
Short name T72
Test name
Test status
Simulation time 17529970655 ps
CPU time 9.39 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 05:55:38 PM PDT 24
Peak memory 210768 kb
Host smart-c36f68a0-e68f-4c42-9892-662d80af743b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842467658 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2842467658
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1861721122
Short name T607
Test name
Test status
Simulation time 492688754 ps
CPU time 0.83 seconds
Started Aug 19 05:54:58 PM PDT 24
Finished Aug 19 05:54:59 PM PDT 24
Peak memory 202004 kb
Host smart-44eefb80-c3b1-443d-9902-b06b16ac4e5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861721122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1861721122
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1986588766
Short name T781
Test name
Test status
Simulation time 332252058704 ps
CPU time 394.84 seconds
Started Aug 19 05:54:44 PM PDT 24
Finished Aug 19 06:01:19 PM PDT 24
Peak memory 202116 kb
Host smart-c00f98a5-731c-4e4d-ba67-be437f28680b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986588766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1986588766
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.501361152
Short name T462
Test name
Test status
Simulation time 488458464209 ps
CPU time 1204.45 seconds
Started Aug 19 05:55:00 PM PDT 24
Finished Aug 19 06:15:04 PM PDT 24
Peak memory 202156 kb
Host smart-f010848e-4e45-49f1-a8ed-6a1038f2cf83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=501361152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.501361152
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1082059158
Short name T675
Test name
Test status
Simulation time 498306719353 ps
CPU time 651.88 seconds
Started Aug 19 05:54:45 PM PDT 24
Finished Aug 19 06:05:37 PM PDT 24
Peak memory 202116 kb
Host smart-8f189cdc-3e3a-43d1-866d-77fa8b0dfe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082059158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1082059158
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.4223371900
Short name T696
Test name
Test status
Simulation time 321630473068 ps
CPU time 752.68 seconds
Started Aug 19 05:54:48 PM PDT 24
Finished Aug 19 06:07:21 PM PDT 24
Peak memory 202116 kb
Host smart-6946b402-83e2-4ef6-b994-5b36af5f6c03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223371900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.4223371900
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1999198876
Short name T165
Test name
Test status
Simulation time 200426589832 ps
CPU time 119.81 seconds
Started Aug 19 05:55:04 PM PDT 24
Finished Aug 19 05:57:04 PM PDT 24
Peak memory 202176 kb
Host smart-6249f0c1-efeb-42e2-9ea6-5a987102ce5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999198876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1999198876
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3185672619
Short name T508
Test name
Test status
Simulation time 190932160810 ps
CPU time 449.4 seconds
Started Aug 19 05:54:56 PM PDT 24
Finished Aug 19 06:02:26 PM PDT 24
Peak memory 202120 kb
Host smart-2c7c5476-f14d-4785-84c3-2eeb86f43c65
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185672619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3185672619
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1258415345
Short name T627
Test name
Test status
Simulation time 110413840454 ps
CPU time 492.19 seconds
Started Aug 19 05:54:55 PM PDT 24
Finished Aug 19 06:03:07 PM PDT 24
Peak memory 202404 kb
Host smart-2ce2606a-afb6-4c70-8969-5fdd5a0762dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258415345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1258415345
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2123161806
Short name T552
Test name
Test status
Simulation time 42141801292 ps
CPU time 22.28 seconds
Started Aug 19 05:54:56 PM PDT 24
Finished Aug 19 05:55:19 PM PDT 24
Peak memory 202000 kb
Host smart-1086e372-557a-415c-bdd4-5365bff24c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123161806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2123161806
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.735470788
Short name T391
Test name
Test status
Simulation time 4188786132 ps
CPU time 2.84 seconds
Started Aug 19 05:54:37 PM PDT 24
Finished Aug 19 05:54:40 PM PDT 24
Peak memory 201968 kb
Host smart-0042b170-749e-4451-9de4-9f9bbabe9442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735470788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.735470788
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2354244432
Short name T46
Test name
Test status
Simulation time 7541949140 ps
CPU time 16.94 seconds
Started Aug 19 05:54:51 PM PDT 24
Finished Aug 19 05:55:08 PM PDT 24
Peak memory 218552 kb
Host smart-ef56f90a-f3a9-4423-862b-0144307d9b6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354244432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2354244432
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1913287893
Short name T640
Test name
Test status
Simulation time 6030017821 ps
CPU time 8.07 seconds
Started Aug 19 05:54:31 PM PDT 24
Finished Aug 19 05:54:45 PM PDT 24
Peak memory 202036 kb
Host smart-77c86358-8c63-4642-a8ad-62c13057ed5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913287893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1913287893
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1507260026
Short name T117
Test name
Test status
Simulation time 347017833813 ps
CPU time 241.72 seconds
Started Aug 19 05:54:54 PM PDT 24
Finished Aug 19 05:58:56 PM PDT 24
Peak memory 202152 kb
Host smart-72805100-a1f3-4e50-a4d5-11552a2429bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507260026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1507260026
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.925255707
Short name T470
Test name
Test status
Simulation time 2796215051 ps
CPU time 7.3 seconds
Started Aug 19 05:54:52 PM PDT 24
Finished Aug 19 05:55:00 PM PDT 24
Peak memory 202304 kb
Host smart-80d1c804-3cc3-4778-9301-8476da6da176
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925255707 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.925255707
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2986355634
Short name T82
Test name
Test status
Simulation time 329912907 ps
CPU time 0.81 seconds
Started Aug 19 05:55:29 PM PDT 24
Finished Aug 19 05:55:30 PM PDT 24
Peak memory 201960 kb
Host smart-28113131-0284-4e70-8bf0-7fc945a1d9fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986355634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2986355634
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.950297262
Short name T782
Test name
Test status
Simulation time 366925745142 ps
CPU time 395.03 seconds
Started Aug 19 05:55:13 PM PDT 24
Finished Aug 19 06:01:48 PM PDT 24
Peak memory 202176 kb
Host smart-a52b9ba9-43c2-43cb-948d-3f20cd25f171
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950297262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.950297262
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3891058545
Short name T176
Test name
Test status
Simulation time 361111147597 ps
CPU time 204.72 seconds
Started Aug 19 05:55:31 PM PDT 24
Finished Aug 19 05:58:56 PM PDT 24
Peak memory 202172 kb
Host smart-03e93f20-1dbe-4636-9220-912103ea8319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891058545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3891058545
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1264134203
Short name T92
Test name
Test status
Simulation time 489494475292 ps
CPU time 557.35 seconds
Started Aug 19 05:55:11 PM PDT 24
Finished Aug 19 06:04:29 PM PDT 24
Peak memory 202160 kb
Host smart-34727e52-800d-4dff-9210-172bc8a11e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264134203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1264134203
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2655160473
Short name T166
Test name
Test status
Simulation time 320567444745 ps
CPU time 760.13 seconds
Started Aug 19 05:55:34 PM PDT 24
Finished Aug 19 06:08:15 PM PDT 24
Peak memory 202148 kb
Host smart-414239c7-5e4f-4bfc-90a9-47f06ad261dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655160473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2655160473
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2985415285
Short name T268
Test name
Test status
Simulation time 171434159483 ps
CPU time 380.84 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 06:01:49 PM PDT 24
Peak memory 202164 kb
Host smart-71d13d91-f6ae-4b84-b605-5f89ea252fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985415285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2985415285
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1399814981
Short name T581
Test name
Test status
Simulation time 496812826871 ps
CPU time 1126.99 seconds
Started Aug 19 05:55:26 PM PDT 24
Finished Aug 19 06:14:14 PM PDT 24
Peak memory 202128 kb
Host smart-201caa8c-5ed7-47b1-b514-5ba32cf9db0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399814981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1399814981
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.759274682
Short name T289
Test name
Test status
Simulation time 551212258193 ps
CPU time 1201.41 seconds
Started Aug 19 05:55:16 PM PDT 24
Finished Aug 19 06:15:17 PM PDT 24
Peak memory 202200 kb
Host smart-7e38722f-c50d-4058-8ce6-017439a4f448
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759274682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.759274682
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1187609822
Short name T480
Test name
Test status
Simulation time 603999010574 ps
CPU time 1014.38 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 06:12:23 PM PDT 24
Peak memory 200712 kb
Host smart-c9b0eed3-2b34-480b-9f6b-de9a9a56e0f3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187609822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1187609822
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3664513292
Short name T193
Test name
Test status
Simulation time 83304511471 ps
CPU time 278.62 seconds
Started Aug 19 05:55:15 PM PDT 24
Finished Aug 19 05:59:54 PM PDT 24
Peak memory 202432 kb
Host smart-6965753f-0902-437e-835b-9a4411c36ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664513292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3664513292
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.914515106
Short name T714
Test name
Test status
Simulation time 27234148330 ps
CPU time 30.03 seconds
Started Aug 19 05:55:25 PM PDT 24
Finished Aug 19 05:55:55 PM PDT 24
Peak memory 201940 kb
Host smart-233dd2bf-f08d-471a-8f2e-67b11aa0431f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914515106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.914515106
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2968673180
Short name T347
Test name
Test status
Simulation time 3863445586 ps
CPU time 5.16 seconds
Started Aug 19 05:55:18 PM PDT 24
Finished Aug 19 05:55:23 PM PDT 24
Peak memory 201956 kb
Host smart-91162ec6-a70f-4094-96df-a43eeea80eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968673180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2968673180
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2409995247
Short name T526
Test name
Test status
Simulation time 5623921101 ps
CPU time 6.8 seconds
Started Aug 19 05:55:13 PM PDT 24
Finished Aug 19 05:55:20 PM PDT 24
Peak memory 201976 kb
Host smart-fe714218-dd5b-46f3-a2fb-48d348c8d6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409995247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2409995247
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1381009871
Short name T186
Test name
Test status
Simulation time 10026967237 ps
CPU time 11.59 seconds
Started Aug 19 05:55:23 PM PDT 24
Finished Aug 19 05:55:35 PM PDT 24
Peak memory 202324 kb
Host smart-369bb4bd-ff6a-483a-b97b-5b58cd40d833
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381009871 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1381009871
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3073280497
Short name T465
Test name
Test status
Simulation time 504053932 ps
CPU time 0.8 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 05:55:29 PM PDT 24
Peak memory 201992 kb
Host smart-b152b6ad-f633-4a94-aa67-382e90176e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073280497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3073280497
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2212500206
Short name T294
Test name
Test status
Simulation time 163689606895 ps
CPU time 354.6 seconds
Started Aug 19 05:55:33 PM PDT 24
Finished Aug 19 06:01:28 PM PDT 24
Peak memory 202164 kb
Host smart-71c750da-1f67-46f2-8360-dcf533edb432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212500206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2212500206
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.348379281
Short name T66
Test name
Test status
Simulation time 162759513979 ps
CPU time 342.54 seconds
Started Aug 19 05:55:17 PM PDT 24
Finished Aug 19 06:00:59 PM PDT 24
Peak memory 200676 kb
Host smart-a22efd0f-166c-4e39-8535-826cfd9e75c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348379281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.348379281
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.267121292
Short name T503
Test name
Test status
Simulation time 497200629826 ps
CPU time 1227.87 seconds
Started Aug 19 05:55:16 PM PDT 24
Finished Aug 19 06:15:44 PM PDT 24
Peak memory 202148 kb
Host smart-ae3b5363-5b1d-4b72-8195-c1919579ccf6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=267121292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.267121292
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.747996679
Short name T154
Test name
Test status
Simulation time 329958542550 ps
CPU time 180.87 seconds
Started Aug 19 05:55:12 PM PDT 24
Finished Aug 19 05:58:12 PM PDT 24
Peak memory 200752 kb
Host smart-70bf77b5-e0d2-4bdc-9c29-c463d6d904a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747996679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.747996679
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.882722874
Short name T561
Test name
Test status
Simulation time 497145514452 ps
CPU time 1084.04 seconds
Started Aug 19 05:55:38 PM PDT 24
Finished Aug 19 06:13:42 PM PDT 24
Peak memory 202180 kb
Host smart-80bc5752-7492-46f8-a7cc-2de2050380b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=882722874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixe
d.882722874
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3671612428
Short name T406
Test name
Test status
Simulation time 210757770301 ps
CPU time 456.74 seconds
Started Aug 19 05:55:26 PM PDT 24
Finished Aug 19 06:03:03 PM PDT 24
Peak memory 202108 kb
Host smart-8a6be941-2304-45b1-86c2-484807d44797
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671612428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3671612428
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.4233866632
Short name T33
Test name
Test status
Simulation time 128015026524 ps
CPU time 711.53 seconds
Started Aug 19 05:55:23 PM PDT 24
Finished Aug 19 06:07:15 PM PDT 24
Peak memory 202352 kb
Host smart-e03c744c-4766-47e1-ae0e-7966cdb3da7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233866632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.4233866632
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.330711007
Short name T792
Test name
Test status
Simulation time 27015662951 ps
CPU time 57.27 seconds
Started Aug 19 05:55:23 PM PDT 24
Finished Aug 19 05:56:20 PM PDT 24
Peak memory 201968 kb
Host smart-2f35ebc4-a3c3-4c2c-a6fc-a011d96997a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330711007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.330711007
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.233375478
Short name T766
Test name
Test status
Simulation time 4328013227 ps
CPU time 10.93 seconds
Started Aug 19 05:55:33 PM PDT 24
Finished Aug 19 05:55:44 PM PDT 24
Peak memory 201976 kb
Host smart-1eb10f93-141c-4068-b249-e84e73a26fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233375478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.233375478
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.937971267
Short name T71
Test name
Test status
Simulation time 5972184858 ps
CPU time 9.52 seconds
Started Aug 19 05:55:31 PM PDT 24
Finished Aug 19 05:55:41 PM PDT 24
Peak memory 201972 kb
Host smart-5fc45630-bb69-4397-9795-92b3c2dbb5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937971267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.937971267
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2799924447
Short name T708
Test name
Test status
Simulation time 331506861926 ps
CPU time 520.02 seconds
Started Aug 19 05:55:17 PM PDT 24
Finished Aug 19 06:03:58 PM PDT 24
Peak memory 202128 kb
Host smart-c9a30a36-7545-48c3-9880-bfbf863f388d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799924447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2799924447
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1837948486
Short name T18
Test name
Test status
Simulation time 19689074848 ps
CPU time 9.58 seconds
Started Aug 19 05:55:33 PM PDT 24
Finished Aug 19 05:55:43 PM PDT 24
Peak memory 212312 kb
Host smart-5b85af06-02aa-4a33-951f-f7cfe90b703c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837948486 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1837948486
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2257733173
Short name T362
Test name
Test status
Simulation time 291225918 ps
CPU time 1.28 seconds
Started Aug 19 05:55:36 PM PDT 24
Finished Aug 19 05:55:37 PM PDT 24
Peak memory 201976 kb
Host smart-62d0f98f-002b-43d0-9309-d044f76784da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257733173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2257733173
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3251199018
Short name T645
Test name
Test status
Simulation time 531705359712 ps
CPU time 959.29 seconds
Started Aug 19 05:55:39 PM PDT 24
Finished Aug 19 06:11:38 PM PDT 24
Peak memory 202140 kb
Host smart-5c2701eb-78b0-4317-bda4-f492ad1966ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251199018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3251199018
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.4064849545
Short name T787
Test name
Test status
Simulation time 160517494258 ps
CPU time 85.94 seconds
Started Aug 19 05:55:22 PM PDT 24
Finished Aug 19 05:56:48 PM PDT 24
Peak memory 202172 kb
Host smart-ac3de78c-5b3a-4435-96c2-c663ec5d06b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064849545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.4064849545
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2972181185
Short name T414
Test name
Test status
Simulation time 326007347771 ps
CPU time 682.77 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 06:06:51 PM PDT 24
Peak memory 202096 kb
Host smart-eb28a978-f972-4182-9b16-af21612f19bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972181185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2972181185
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2481030593
Short name T1
Test name
Test status
Simulation time 323160302987 ps
CPU time 185.24 seconds
Started Aug 19 05:55:12 PM PDT 24
Finished Aug 19 05:58:17 PM PDT 24
Peak memory 202160 kb
Host smart-f02ffee8-530e-46a0-88c1-562362e39fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481030593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2481030593
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1555593568
Short name T361
Test name
Test status
Simulation time 328968847676 ps
CPU time 179.47 seconds
Started Aug 19 05:55:24 PM PDT 24
Finished Aug 19 05:58:23 PM PDT 24
Peak memory 202088 kb
Host smart-5c1b20f0-c1a0-4604-9c25-a96b9e8f7314
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555593568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1555593568
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3135683770
Short name T246
Test name
Test status
Simulation time 557379453257 ps
CPU time 1304.52 seconds
Started Aug 19 05:55:26 PM PDT 24
Finished Aug 19 06:17:10 PM PDT 24
Peak memory 202152 kb
Host smart-f9a194f0-a143-44f8-83ef-4c6f1a17db88
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135683770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3135683770
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3245496727
Short name T457
Test name
Test status
Simulation time 204599666046 ps
CPU time 234.23 seconds
Started Aug 19 05:55:31 PM PDT 24
Finished Aug 19 05:59:26 PM PDT 24
Peak memory 202148 kb
Host smart-edf00131-0b42-496c-8651-d9fe38e05563
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245496727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3245496727
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3860781014
Short name T394
Test name
Test status
Simulation time 127144596092 ps
CPU time 390.57 seconds
Started Aug 19 05:58:10 PM PDT 24
Finished Aug 19 06:04:41 PM PDT 24
Peak memory 202484 kb
Host smart-f6175189-9388-4138-9ed7-804746e68012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860781014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3860781014
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1590960054
Short name T723
Test name
Test status
Simulation time 45325457078 ps
CPU time 28.48 seconds
Started Aug 19 05:55:32 PM PDT 24
Finished Aug 19 05:56:00 PM PDT 24
Peak memory 202120 kb
Host smart-f4826270-e89a-43a4-bc8a-3ec52cbb2baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590960054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1590960054
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1351622663
Short name T596
Test name
Test status
Simulation time 4507307619 ps
CPU time 3.3 seconds
Started Aug 19 05:55:23 PM PDT 24
Finished Aug 19 05:55:27 PM PDT 24
Peak memory 201996 kb
Host smart-9a5cad7a-8ec3-4cd5-a85d-c2bd39eb5c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351622663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1351622663
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3269784933
Short name T747
Test name
Test status
Simulation time 5940629949 ps
CPU time 2.94 seconds
Started Aug 19 05:55:34 PM PDT 24
Finished Aug 19 05:55:37 PM PDT 24
Peak memory 201988 kb
Host smart-bc3e61dc-7254-4010-ad3d-261758057810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269784933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3269784933
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.322262410
Short name T604
Test name
Test status
Simulation time 3956256374 ps
CPU time 9.92 seconds
Started Aug 19 05:55:37 PM PDT 24
Finished Aug 19 05:55:47 PM PDT 24
Peak memory 202024 kb
Host smart-9829a5d0-d59e-4076-b14c-c78122aae789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322262410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
322262410
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.947264536
Short name T25
Test name
Test status
Simulation time 4608511356 ps
CPU time 11.5 seconds
Started Aug 19 05:55:27 PM PDT 24
Finished Aug 19 05:55:39 PM PDT 24
Peak memory 210504 kb
Host smart-ea48b180-efc0-4e6a-83b0-03b4189c40d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947264536 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.947264536
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2321139555
Short name T776
Test name
Test status
Simulation time 489059789 ps
CPU time 0.86 seconds
Started Aug 19 05:55:24 PM PDT 24
Finished Aug 19 05:55:25 PM PDT 24
Peak memory 201992 kb
Host smart-efd4588a-8c85-41f9-9941-13a885803091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321139555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2321139555
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2807487379
Short name T722
Test name
Test status
Simulation time 414636331490 ps
CPU time 494.68 seconds
Started Aug 19 05:55:30 PM PDT 24
Finished Aug 19 06:03:45 PM PDT 24
Peak memory 202136 kb
Host smart-7cd1dd3e-7a26-44e4-9e71-cfa8f60d7ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807487379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2807487379
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3826656320
Short name T537
Test name
Test status
Simulation time 490038178788 ps
CPU time 323.3 seconds
Started Aug 19 05:55:30 PM PDT 24
Finished Aug 19 06:00:53 PM PDT 24
Peak memory 202160 kb
Host smart-259f450c-8891-444e-8bb0-ac4190a95b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826656320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3826656320
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.540143908
Short name T79
Test name
Test status
Simulation time 161002817068 ps
CPU time 348.15 seconds
Started Aug 19 05:55:34 PM PDT 24
Finished Aug 19 06:01:22 PM PDT 24
Peak memory 202192 kb
Host smart-b7d7983a-9a61-4fe7-ad74-14a60aa608b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=540143908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.540143908
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.59022992
Short name T178
Test name
Test status
Simulation time 495074120725 ps
CPU time 647.32 seconds
Started Aug 19 05:55:32 PM PDT 24
Finished Aug 19 06:06:24 PM PDT 24
Peak memory 202216 kb
Host smart-861c2857-ca2f-47d3-aad1-372a1950c435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59022992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.59022992
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1256023311
Short name T514
Test name
Test status
Simulation time 159601846956 ps
CPU time 376.46 seconds
Started Aug 19 05:55:19 PM PDT 24
Finished Aug 19 06:01:36 PM PDT 24
Peak memory 202124 kb
Host smart-d9582324-6b8f-41b2-9af0-06203d46a887
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256023311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1256023311
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.619041130
Short name T310
Test name
Test status
Simulation time 643985832124 ps
CPU time 799.02 seconds
Started Aug 19 05:55:30 PM PDT 24
Finished Aug 19 06:08:49 PM PDT 24
Peak memory 202188 kb
Host smart-12923b21-bd63-4808-b229-f417ba5fb21c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619041130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.619041130
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.4215645909
Short name T669
Test name
Test status
Simulation time 197894305627 ps
CPU time 227.77 seconds
Started Aug 19 05:55:49 PM PDT 24
Finished Aug 19 05:59:37 PM PDT 24
Peak memory 202144 kb
Host smart-c393feae-8a45-4b8a-bc43-db10143914c7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215645909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.4215645909
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.854700121
Short name T758
Test name
Test status
Simulation time 90779939826 ps
CPU time 323.08 seconds
Started Aug 19 05:55:35 PM PDT 24
Finished Aug 19 06:00:58 PM PDT 24
Peak memory 202368 kb
Host smart-07ca19af-fb29-4ed0-8bd1-d91e659a9915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854700121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.854700121
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1730845710
Short name T385
Test name
Test status
Simulation time 44383263944 ps
CPU time 8.71 seconds
Started Aug 19 05:55:34 PM PDT 24
Finished Aug 19 05:55:43 PM PDT 24
Peak memory 201968 kb
Host smart-0a458360-32d6-4c89-8a8e-95e2d00ff74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730845710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1730845710
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.479071212
Short name T733
Test name
Test status
Simulation time 3026502911 ps
CPU time 4.42 seconds
Started Aug 19 05:55:33 PM PDT 24
Finished Aug 19 05:55:38 PM PDT 24
Peak memory 201972 kb
Host smart-5f9c0ec2-6459-4371-b6b8-3635eb9ef8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479071212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.479071212
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3632534647
Short name T524
Test name
Test status
Simulation time 5918062929 ps
CPU time 7.66 seconds
Started Aug 19 05:55:24 PM PDT 24
Finished Aug 19 05:55:32 PM PDT 24
Peak memory 201972 kb
Host smart-992bb44e-0045-43df-8de3-53979cdf03f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632534647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3632534647
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3699495240
Short name T734
Test name
Test status
Simulation time 197567938584 ps
CPU time 417.9 seconds
Started Aug 19 05:55:37 PM PDT 24
Finished Aug 19 06:02:35 PM PDT 24
Peak memory 202148 kb
Host smart-ad98f9d8-07eb-40da-8753-1b7e3a2aa3ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699495240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3699495240
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3280681005
Short name T297
Test name
Test status
Simulation time 5963428072 ps
CPU time 11.4 seconds
Started Aug 19 05:55:27 PM PDT 24
Finished Aug 19 05:55:39 PM PDT 24
Peak memory 218628 kb
Host smart-d3181c8e-b176-42bc-aee9-65ea8a1344dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280681005 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3280681005
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2586751263
Short name T615
Test name
Test status
Simulation time 505852613 ps
CPU time 1.42 seconds
Started Aug 19 05:55:21 PM PDT 24
Finished Aug 19 05:55:23 PM PDT 24
Peak memory 202000 kb
Host smart-282e3f64-58e9-4c20-969a-94f72eff170b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586751263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2586751263
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2428691140
Short name T424
Test name
Test status
Simulation time 162717769133 ps
CPU time 21.66 seconds
Started Aug 19 05:55:34 PM PDT 24
Finished Aug 19 05:55:56 PM PDT 24
Peak memory 202160 kb
Host smart-bac3ec39-54f9-4326-a34c-612b27ad75b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428691140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2428691140
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3711904653
Short name T164
Test name
Test status
Simulation time 538337769357 ps
CPU time 264.24 seconds
Started Aug 19 05:55:37 PM PDT 24
Finished Aug 19 06:00:01 PM PDT 24
Peak memory 202144 kb
Host smart-90a7ac02-64f6-46db-a82a-842a6bfeba6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711904653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3711904653
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1533829327
Short name T173
Test name
Test status
Simulation time 161637700496 ps
CPU time 188.97 seconds
Started Aug 19 05:55:50 PM PDT 24
Finished Aug 19 05:58:59 PM PDT 24
Peak memory 202152 kb
Host smart-5a6524a7-20ce-401f-94d4-1b25c5fafdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533829327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1533829327
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.771797935
Short name T755
Test name
Test status
Simulation time 486622242031 ps
CPU time 817.91 seconds
Started Aug 19 05:55:33 PM PDT 24
Finished Aug 19 06:09:11 PM PDT 24
Peak memory 202116 kb
Host smart-13eb3dd5-b3d4-4e39-a591-9217b517bfb0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=771797935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.771797935
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3787098731
Short name T578
Test name
Test status
Simulation time 159139390062 ps
CPU time 371.04 seconds
Started Aug 19 05:55:47 PM PDT 24
Finished Aug 19 06:01:58 PM PDT 24
Peak memory 202112 kb
Host smart-d09c364b-1f6e-4b07-82b1-cc40dfa0b05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787098731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3787098731
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3626236327
Short name T360
Test name
Test status
Simulation time 323189116883 ps
CPU time 178.21 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 05:58:27 PM PDT 24
Peak memory 202128 kb
Host smart-84e206a2-e91a-4446-bbaa-80096abe1d4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626236327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3626236327
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.38790943
Short name T140
Test name
Test status
Simulation time 625157049073 ps
CPU time 388.76 seconds
Started Aug 19 05:55:34 PM PDT 24
Finished Aug 19 06:02:03 PM PDT 24
Peak memory 202180 kb
Host smart-00de80b5-1c3e-4065-a849-14c5b7f068f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38790943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_w
akeup.38790943
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1400908558
Short name T498
Test name
Test status
Simulation time 201375577089 ps
CPU time 98.86 seconds
Started Aug 19 05:55:15 PM PDT 24
Finished Aug 19 05:56:54 PM PDT 24
Peak memory 202336 kb
Host smart-a1b140b2-86b4-4cbd-a9ee-358435c26e6c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400908558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1400908558
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3506744352
Short name T540
Test name
Test status
Simulation time 107739344790 ps
CPU time 474.62 seconds
Started Aug 19 05:55:25 PM PDT 24
Finished Aug 19 06:03:20 PM PDT 24
Peak memory 202384 kb
Host smart-d831f998-e711-44f8-b6e3-e97791957422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506744352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3506744352
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.934390421
Short name T577
Test name
Test status
Simulation time 27117462694 ps
CPU time 62.7 seconds
Started Aug 19 05:55:34 PM PDT 24
Finished Aug 19 05:56:36 PM PDT 24
Peak memory 201972 kb
Host smart-485dfa01-ead1-4bdc-8b1b-6f727a0ca332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934390421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.934390421
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2068060559
Short name T679
Test name
Test status
Simulation time 4285548745 ps
CPU time 11.17 seconds
Started Aug 19 05:55:41 PM PDT 24
Finished Aug 19 05:55:52 PM PDT 24
Peak memory 202140 kb
Host smart-ab128cc3-2e7d-43b0-8af6-a20aa4bd7ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068060559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2068060559
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2196005818
Short name T641
Test name
Test status
Simulation time 5950534095 ps
CPU time 13.99 seconds
Started Aug 19 05:55:41 PM PDT 24
Finished Aug 19 05:55:55 PM PDT 24
Peak memory 202144 kb
Host smart-06354f45-2a81-42f6-adc7-fffaccd2748d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196005818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2196005818
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.71956319
Short name T208
Test name
Test status
Simulation time 219399583636 ps
CPU time 512.41 seconds
Started Aug 19 05:55:23 PM PDT 24
Finished Aug 19 06:03:55 PM PDT 24
Peak memory 202156 kb
Host smart-8242e026-4d05-400f-8659-c0735472c27a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71956319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.71956319
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2437201506
Short name T475
Test name
Test status
Simulation time 371043837 ps
CPU time 1.49 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 05:55:30 PM PDT 24
Peak memory 201980 kb
Host smart-e8ed9ad9-dccc-49ae-922c-da4df4b8af1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437201506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2437201506
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.485506714
Short name T588
Test name
Test status
Simulation time 340592080483 ps
CPU time 810.17 seconds
Started Aug 19 05:55:39 PM PDT 24
Finished Aug 19 06:09:09 PM PDT 24
Peak memory 202148 kb
Host smart-97fb2aab-c1a5-48ea-973e-2b17198fb4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485506714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.485506714
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2110963449
Short name T455
Test name
Test status
Simulation time 168244863943 ps
CPU time 382.78 seconds
Started Aug 19 05:55:24 PM PDT 24
Finished Aug 19 06:01:47 PM PDT 24
Peak memory 202160 kb
Host smart-4f63968b-8b38-4b94-b38b-11ee350047ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110963449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2110963449
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.337035302
Short name T355
Test name
Test status
Simulation time 160555546337 ps
CPU time 195.86 seconds
Started Aug 19 05:55:23 PM PDT 24
Finished Aug 19 05:58:39 PM PDT 24
Peak memory 202192 kb
Host smart-92f796f0-ffe8-4c21-a6ff-c68c6a6b48f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=337035302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.337035302
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2734162582
Short name T775
Test name
Test status
Simulation time 164234343320 ps
CPU time 397.44 seconds
Started Aug 19 05:55:41 PM PDT 24
Finished Aug 19 06:02:18 PM PDT 24
Peak memory 202172 kb
Host smart-5f58f35f-9689-4ba1-8c99-fe15bdbacd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734162582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2734162582
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1959295322
Short name T384
Test name
Test status
Simulation time 333564674615 ps
CPU time 48.59 seconds
Started Aug 19 05:55:33 PM PDT 24
Finished Aug 19 05:56:22 PM PDT 24
Peak memory 202128 kb
Host smart-75b8904a-c2d9-4aa9-821f-d1ff83dbcecd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959295322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1959295322
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.521673850
Short name T630
Test name
Test status
Simulation time 344842334041 ps
CPU time 196.63 seconds
Started Aug 19 05:55:36 PM PDT 24
Finished Aug 19 05:58:53 PM PDT 24
Peak memory 202044 kb
Host smart-283e1baf-1b54-4be9-896d-84002da875a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521673850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.521673850
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2186187081
Short name T5
Test name
Test status
Simulation time 210957074653 ps
CPU time 51.13 seconds
Started Aug 19 05:55:26 PM PDT 24
Finished Aug 19 05:56:17 PM PDT 24
Peak memory 202116 kb
Host smart-70c2bf2e-e6c5-47af-b30f-17514cb48033
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186187081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2186187081
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.4086295693
Short name T188
Test name
Test status
Simulation time 93863201743 ps
CPU time 311.8 seconds
Started Aug 19 05:55:31 PM PDT 24
Finished Aug 19 06:00:43 PM PDT 24
Peak memory 202544 kb
Host smart-9acfbf75-e27d-463e-bb48-f946d564d9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086295693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.4086295693
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.478298635
Short name T438
Test name
Test status
Simulation time 25630505920 ps
CPU time 15.4 seconds
Started Aug 19 05:55:22 PM PDT 24
Finished Aug 19 05:55:37 PM PDT 24
Peak memory 202008 kb
Host smart-db0d640b-f9a6-4b1f-b444-4a3cadadd0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478298635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.478298635
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.94284200
Short name T761
Test name
Test status
Simulation time 4379477619 ps
CPU time 3.01 seconds
Started Aug 19 05:55:17 PM PDT 24
Finished Aug 19 05:55:20 PM PDT 24
Peak memory 201980 kb
Host smart-3b0af189-b3ce-4427-bce5-7c3cf81b3924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94284200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.94284200
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1868326518
Short name T454
Test name
Test status
Simulation time 5776638604 ps
CPU time 14.58 seconds
Started Aug 19 05:55:31 PM PDT 24
Finished Aug 19 05:55:45 PM PDT 24
Peak memory 201972 kb
Host smart-89726e4d-d9d8-4795-858d-c18d6d4021cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868326518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1868326518
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2520344171
Short name T487
Test name
Test status
Simulation time 81314896474 ps
CPU time 417.72 seconds
Started Aug 19 05:55:26 PM PDT 24
Finished Aug 19 06:02:24 PM PDT 24
Peak memory 210592 kb
Host smart-4f82dbee-222c-4d10-9ddb-07d7fbdb36e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520344171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2520344171
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1267753143
Short name T767
Test name
Test status
Simulation time 2966712355 ps
CPU time 8.24 seconds
Started Aug 19 05:55:36 PM PDT 24
Finished Aug 19 05:55:45 PM PDT 24
Peak memory 202272 kb
Host smart-235878f7-442d-4672-93f3-9209094e55a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267753143 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1267753143
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.473074661
Short name T575
Test name
Test status
Simulation time 550487429 ps
CPU time 0.92 seconds
Started Aug 19 05:55:35 PM PDT 24
Finished Aug 19 05:55:36 PM PDT 24
Peak memory 202004 kb
Host smart-eb03b1b4-8ead-43ea-af01-d0280f86175f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473074661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.473074661
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.557352590
Short name T315
Test name
Test status
Simulation time 537100242459 ps
CPU time 233.73 seconds
Started Aug 19 05:55:30 PM PDT 24
Finished Aug 19 05:59:24 PM PDT 24
Peak memory 202156 kb
Host smart-fb9a7bf3-8cfd-4b7e-adf2-4198d53d1ea6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557352590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.557352590
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.986827292
Short name T241
Test name
Test status
Simulation time 451604137825 ps
CPU time 556.79 seconds
Started Aug 19 05:55:41 PM PDT 24
Finished Aug 19 06:04:58 PM PDT 24
Peak memory 202148 kb
Host smart-c0185fb8-1d86-4c39-96b2-082f18709877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986827292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.986827292
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.646793520
Short name T752
Test name
Test status
Simulation time 486587706056 ps
CPU time 273.8 seconds
Started Aug 19 05:55:41 PM PDT 24
Finished Aug 19 06:00:15 PM PDT 24
Peak memory 202152 kb
Host smart-dd506855-2c58-49d4-8cb7-4a68bcf965b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646793520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.646793520
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2719051434
Short name T592
Test name
Test status
Simulation time 495967410170 ps
CPU time 81.69 seconds
Started Aug 19 05:55:19 PM PDT 24
Finished Aug 19 05:56:41 PM PDT 24
Peak memory 202160 kb
Host smart-33da5d1f-87ee-4953-b8f5-97dd2c4c5327
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719051434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2719051434
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.492440021
Short name T83
Test name
Test status
Simulation time 163726465485 ps
CPU time 66.91 seconds
Started Aug 19 05:55:32 PM PDT 24
Finished Aug 19 05:56:39 PM PDT 24
Peak memory 202308 kb
Host smart-aac6ba8f-9772-47e3-86bf-b2a12e493416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492440021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.492440021
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1556091668
Short name T2
Test name
Test status
Simulation time 322096746365 ps
CPU time 728.62 seconds
Started Aug 19 05:55:38 PM PDT 24
Finished Aug 19 06:07:47 PM PDT 24
Peak memory 202124 kb
Host smart-ab59569c-e485-46f7-a5b6-8c29df59d796
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556091668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1556091668
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2934781793
Short name T264
Test name
Test status
Simulation time 194911104730 ps
CPU time 106.96 seconds
Started Aug 19 05:55:39 PM PDT 24
Finished Aug 19 05:57:26 PM PDT 24
Peak memory 202180 kb
Host smart-befb52d2-3911-4cd4-b9c7-e4867ca16343
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934781793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2934781793
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3228854019
Short name T613
Test name
Test status
Simulation time 202021851745 ps
CPU time 122.38 seconds
Started Aug 19 05:55:30 PM PDT 24
Finished Aug 19 05:57:33 PM PDT 24
Peak memory 202328 kb
Host smart-d9baa994-e31b-4b62-ae5c-cf67887a44c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228854019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3228854019
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.929896714
Short name T681
Test name
Test status
Simulation time 108503985073 ps
CPU time 400.02 seconds
Started Aug 19 05:55:50 PM PDT 24
Finished Aug 19 06:02:30 PM PDT 24
Peak memory 202400 kb
Host smart-4f9d0fbd-13ad-45fc-82a6-20d1d8079c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929896714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.929896714
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.836629826
Short name T682
Test name
Test status
Simulation time 25783751551 ps
CPU time 26.74 seconds
Started Aug 19 05:55:41 PM PDT 24
Finished Aug 19 05:56:08 PM PDT 24
Peak memory 202008 kb
Host smart-df6434bd-9b2d-4f44-b4e3-306b7eaba4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836629826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.836629826
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2241182317
Short name T773
Test name
Test status
Simulation time 4555572332 ps
CPU time 6.19 seconds
Started Aug 19 05:55:48 PM PDT 24
Finished Aug 19 05:55:54 PM PDT 24
Peak memory 201960 kb
Host smart-a772be14-c72a-4bee-a53e-ea1204861b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241182317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2241182317
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1903768114
Short name T597
Test name
Test status
Simulation time 5823301940 ps
CPU time 3.31 seconds
Started Aug 19 05:55:21 PM PDT 24
Finished Aug 19 05:55:25 PM PDT 24
Peak memory 201988 kb
Host smart-c7d89cc5-0a93-4952-9f1d-ce62fa7d75bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903768114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1903768114
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.876935405
Short name T251
Test name
Test status
Simulation time 178523988549 ps
CPU time 105.22 seconds
Started Aug 19 05:55:44 PM PDT 24
Finished Aug 19 05:57:29 PM PDT 24
Peak memory 202140 kb
Host smart-8c58185b-2efb-4547-b725-736e6bd8b13e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876935405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
876935405
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1633983479
Short name T64
Test name
Test status
Simulation time 527252057 ps
CPU time 1.8 seconds
Started Aug 19 05:55:45 PM PDT 24
Finished Aug 19 05:55:47 PM PDT 24
Peak memory 201992 kb
Host smart-82c1e8fe-9421-4b60-8610-bee509516a6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633983479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1633983479
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2729877574
Short name T760
Test name
Test status
Simulation time 333053022426 ps
CPU time 728.49 seconds
Started Aug 19 05:55:45 PM PDT 24
Finished Aug 19 06:07:53 PM PDT 24
Peak memory 202216 kb
Host smart-2b1c5ce4-0292-4885-8c19-d3e73f0dee8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729877574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2729877574
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3248658231
Short name T446
Test name
Test status
Simulation time 165934557610 ps
CPU time 375.79 seconds
Started Aug 19 05:55:47 PM PDT 24
Finished Aug 19 06:02:03 PM PDT 24
Peak memory 202168 kb
Host smart-e3f6ff47-3ad3-4633-92dc-36f6d57afeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248658231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3248658231
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.487700978
Short name T413
Test name
Test status
Simulation time 162056589068 ps
CPU time 99.15 seconds
Started Aug 19 05:55:40 PM PDT 24
Finished Aug 19 05:57:20 PM PDT 24
Peak memory 202176 kb
Host smart-93ab82b2-f884-4ded-a156-3949b1de0f05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=487700978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.487700978
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3079585708
Short name T706
Test name
Test status
Simulation time 162025941009 ps
CPU time 97.83 seconds
Started Aug 19 05:55:49 PM PDT 24
Finished Aug 19 05:57:27 PM PDT 24
Peak memory 202100 kb
Host smart-f7186cef-43a8-4119-96d9-af0f356d5793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079585708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3079585708
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3763874114
Short name T456
Test name
Test status
Simulation time 324272307481 ps
CPU time 199.3 seconds
Started Aug 19 05:55:51 PM PDT 24
Finished Aug 19 05:59:10 PM PDT 24
Peak memory 202080 kb
Host smart-297c6273-4d3f-4ad8-b379-37f1eb92b3de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763874114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3763874114
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.292208825
Short name T651
Test name
Test status
Simulation time 186373582350 ps
CPU time 200.75 seconds
Started Aug 19 05:55:50 PM PDT 24
Finished Aug 19 05:59:11 PM PDT 24
Peak memory 202136 kb
Host smart-1231d1e4-f07d-44df-a534-b2027391c6f3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292208825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.292208825
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2442689688
Short name T433
Test name
Test status
Simulation time 119088696331 ps
CPU time 588.07 seconds
Started Aug 19 05:55:43 PM PDT 24
Finished Aug 19 06:05:31 PM PDT 24
Peak memory 202408 kb
Host smart-aadb77c1-fdc6-444a-a5ef-050a84f5ce96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442689688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2442689688
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1234910216
Short name T131
Test name
Test status
Simulation time 30193026721 ps
CPU time 71.1 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 05:56:40 PM PDT 24
Peak memory 201980 kb
Host smart-7c21cfb4-a7fb-4124-8e9d-9a37764b3ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234910216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1234910216
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.1922187768
Short name T569
Test name
Test status
Simulation time 3362921026 ps
CPU time 4.25 seconds
Started Aug 19 05:55:40 PM PDT 24
Finished Aug 19 05:55:44 PM PDT 24
Peak memory 201948 kb
Host smart-2ecb58de-969c-4efc-b21b-2ed85253c58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922187768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1922187768
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2846936844
Short name T572
Test name
Test status
Simulation time 5663428637 ps
CPU time 5.29 seconds
Started Aug 19 05:55:41 PM PDT 24
Finished Aug 19 05:55:46 PM PDT 24
Peak memory 201964 kb
Host smart-f3078d78-86ef-4c57-8132-604ba290b5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846936844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2846936844
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.548176558
Short name T7
Test name
Test status
Simulation time 300164305042 ps
CPU time 964.41 seconds
Started Aug 19 05:55:32 PM PDT 24
Finished Aug 19 06:11:37 PM PDT 24
Peak memory 210616 kb
Host smart-4e49b502-5670-4ac7-a415-505222fc1010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548176558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
548176558
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.648835831
Short name T591
Test name
Test status
Simulation time 3023598712 ps
CPU time 9.28 seconds
Started Aug 19 05:55:39 PM PDT 24
Finished Aug 19 05:55:48 PM PDT 24
Peak memory 210480 kb
Host smart-b188fd19-0189-4dfb-ac3d-16ed25efd87b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648835831 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.648835831
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2552122800
Short name T741
Test name
Test status
Simulation time 483062373 ps
CPU time 1.14 seconds
Started Aug 19 05:55:44 PM PDT 24
Finished Aug 19 05:55:45 PM PDT 24
Peak memory 202008 kb
Host smart-18dd7ca8-aa1f-4db1-a284-5c0c51b5db3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552122800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2552122800
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1258075842
Short name T657
Test name
Test status
Simulation time 336448360026 ps
CPU time 317.3 seconds
Started Aug 19 05:55:38 PM PDT 24
Finished Aug 19 06:00:55 PM PDT 24
Peak memory 202212 kb
Host smart-931c288b-440f-449a-b062-966fa83fe290
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258075842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1258075842
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1990442589
Short name T261
Test name
Test status
Simulation time 552894847865 ps
CPU time 1343.25 seconds
Started Aug 19 05:55:43 PM PDT 24
Finished Aug 19 06:18:06 PM PDT 24
Peak memory 202180 kb
Host smart-640c3151-b7ec-4ce9-af97-843d639b6468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990442589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1990442589
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1386572947
Short name T148
Test name
Test status
Simulation time 161911916931 ps
CPU time 188.13 seconds
Started Aug 19 05:55:34 PM PDT 24
Finished Aug 19 05:58:43 PM PDT 24
Peak memory 202160 kb
Host smart-c0b26eb8-41bb-4698-b0d5-a30a665073f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386572947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1386572947
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2595776776
Short name T501
Test name
Test status
Simulation time 165897431314 ps
CPU time 189.46 seconds
Started Aug 19 05:55:50 PM PDT 24
Finished Aug 19 05:59:00 PM PDT 24
Peak memory 202172 kb
Host smart-42731dbe-1757-4721-835e-882e211e21ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595776776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2595776776
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1627949850
Short name T515
Test name
Test status
Simulation time 489136275597 ps
CPU time 716.4 seconds
Started Aug 19 05:55:35 PM PDT 24
Finished Aug 19 06:07:32 PM PDT 24
Peak memory 202176 kb
Host smart-cc4e47ba-cf6c-46dc-ad14-5954e7bf2327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627949850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1627949850
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2255269466
Short name T432
Test name
Test status
Simulation time 164633087224 ps
CPU time 34.3 seconds
Started Aug 19 05:55:38 PM PDT 24
Finished Aug 19 05:56:13 PM PDT 24
Peak memory 202132 kb
Host smart-4d029480-5b51-4829-8638-199ef32c73b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255269466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2255269466
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3227579556
Short name T249
Test name
Test status
Simulation time 365504346060 ps
CPU time 383.21 seconds
Started Aug 19 05:55:33 PM PDT 24
Finished Aug 19 06:01:57 PM PDT 24
Peak memory 202148 kb
Host smart-b1ff21a4-6c59-412a-8640-1e964dba5ccb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227579556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3227579556
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1681015440
Short name T521
Test name
Test status
Simulation time 398555260606 ps
CPU time 144.53 seconds
Started Aug 19 05:55:43 PM PDT 24
Finished Aug 19 05:58:07 PM PDT 24
Peak memory 202148 kb
Host smart-59aee8c2-d4e4-4111-86de-6eacd975558e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681015440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1681015440
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3362681203
Short name T86
Test name
Test status
Simulation time 39683133865 ps
CPU time 5.2 seconds
Started Aug 19 05:55:35 PM PDT 24
Finished Aug 19 05:55:40 PM PDT 24
Peak memory 201996 kb
Host smart-aaa7884e-df91-4efb-a90f-c6d90d841cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362681203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3362681203
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2114831694
Short name T642
Test name
Test status
Simulation time 3330390101 ps
CPU time 2.81 seconds
Started Aug 19 05:55:44 PM PDT 24
Finished Aug 19 05:55:47 PM PDT 24
Peak memory 201956 kb
Host smart-eccba06c-3797-4e41-9f8d-a94a7af5d0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114831694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2114831694
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2669515566
Short name T535
Test name
Test status
Simulation time 5969863319 ps
CPU time 15.98 seconds
Started Aug 19 05:55:28 PM PDT 24
Finished Aug 19 05:55:45 PM PDT 24
Peak memory 201972 kb
Host smart-fff6f3ab-d1bc-406c-9d94-a07b577f218a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669515566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2669515566
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2515930961
Short name T158
Test name
Test status
Simulation time 512249563049 ps
CPU time 569.86 seconds
Started Aug 19 05:55:35 PM PDT 24
Finished Aug 19 06:05:05 PM PDT 24
Peak memory 210588 kb
Host smart-24ddccc7-f5a4-4fdf-9731-38db2734c6a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515930961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2515930961
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.458240171
Short name T301
Test name
Test status
Simulation time 7084008283 ps
CPU time 14.54 seconds
Started Aug 19 05:55:41 PM PDT 24
Finished Aug 19 05:55:56 PM PDT 24
Peak memory 210740 kb
Host smart-31ccc894-bea7-43c9-b2c1-bca40941b242
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458240171 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.458240171
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3718553462
Short name T673
Test name
Test status
Simulation time 464471898 ps
CPU time 1.22 seconds
Started Aug 19 05:55:48 PM PDT 24
Finished Aug 19 05:55:49 PM PDT 24
Peak memory 201940 kb
Host smart-204a8dcb-9285-4810-b963-c77f923d6d42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718553462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3718553462
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1967088116
Short name T320
Test name
Test status
Simulation time 161489232851 ps
CPU time 26.11 seconds
Started Aug 19 05:55:41 PM PDT 24
Finished Aug 19 05:56:07 PM PDT 24
Peak memory 202148 kb
Host smart-66209602-3505-47b7-887a-c428faedf436
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967088116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1967088116
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.4120535830
Short name T460
Test name
Test status
Simulation time 168290852730 ps
CPU time 390.15 seconds
Started Aug 19 05:55:50 PM PDT 24
Finished Aug 19 06:02:21 PM PDT 24
Peak memory 202188 kb
Host smart-06ae1070-30a4-4e48-9987-1e879fec4279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120535830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.4120535830
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1661217048
Short name T317
Test name
Test status
Simulation time 492690966340 ps
CPU time 288.28 seconds
Started Aug 19 05:55:48 PM PDT 24
Finished Aug 19 06:00:36 PM PDT 24
Peak memory 202044 kb
Host smart-4576497f-0d6e-45b1-8ba1-7b844f7205d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661217048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1661217048
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1975539958
Short name T94
Test name
Test status
Simulation time 490017239948 ps
CPU time 1208.74 seconds
Started Aug 19 05:55:49 PM PDT 24
Finished Aug 19 06:15:57 PM PDT 24
Peak memory 202192 kb
Host smart-0a55678b-9650-47dd-9fea-c26dfe786200
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975539958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1975539958
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.241806629
Short name T235
Test name
Test status
Simulation time 486710471020 ps
CPU time 536.23 seconds
Started Aug 19 05:55:48 PM PDT 24
Finished Aug 19 06:04:44 PM PDT 24
Peak memory 201996 kb
Host smart-a4e3f70b-e9fb-47ce-b31d-43ead8c8fa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241806629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.241806629
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3720049171
Short name T664
Test name
Test status
Simulation time 335303835646 ps
CPU time 492.71 seconds
Started Aug 19 05:55:39 PM PDT 24
Finished Aug 19 06:03:52 PM PDT 24
Peak memory 202128 kb
Host smart-443c0feb-6288-4ee2-afc1-a513ffee148e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720049171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3720049171
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1311845544
Short name T793
Test name
Test status
Simulation time 362110296027 ps
CPU time 206.64 seconds
Started Aug 19 05:55:48 PM PDT 24
Finished Aug 19 05:59:15 PM PDT 24
Peak memory 202216 kb
Host smart-1c405a84-c4b8-42ea-8ea6-989403730cc6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311845544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1311845544
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3653418823
Short name T374
Test name
Test status
Simulation time 413015144919 ps
CPU time 577.2 seconds
Started Aug 19 05:55:41 PM PDT 24
Finished Aug 19 06:05:18 PM PDT 24
Peak memory 202140 kb
Host smart-9d13894d-ac43-495a-8439-67933c80f41a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653418823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3653418823
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.4065875552
Short name T795
Test name
Test status
Simulation time 97700149721 ps
CPU time 376.28 seconds
Started Aug 19 05:55:53 PM PDT 24
Finished Aug 19 06:02:09 PM PDT 24
Peak memory 202088 kb
Host smart-bf0c7760-5cc6-43fa-bd11-6b5b06332aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065875552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.4065875552
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1415018257
Short name T728
Test name
Test status
Simulation time 29179615682 ps
CPU time 70.51 seconds
Started Aug 19 05:55:40 PM PDT 24
Finished Aug 19 05:56:51 PM PDT 24
Peak memory 201996 kb
Host smart-6219e68c-a594-4ecb-b5de-4932151cdd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415018257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1415018257
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2707155016
Short name T567
Test name
Test status
Simulation time 3184832901 ps
CPU time 2.58 seconds
Started Aug 19 05:55:42 PM PDT 24
Finished Aug 19 05:55:44 PM PDT 24
Peak memory 201964 kb
Host smart-f800cca3-2e67-4a9c-9cf5-325241067526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707155016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2707155016
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.37448751
Short name T527
Test name
Test status
Simulation time 6066334864 ps
CPU time 13.58 seconds
Started Aug 19 05:55:44 PM PDT 24
Finished Aug 19 05:55:57 PM PDT 24
Peak memory 201996 kb
Host smart-834030af-e688-4b6c-a587-8a13cd93f397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37448751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.37448751
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2259977627
Short name T236
Test name
Test status
Simulation time 168667957798 ps
CPU time 54.72 seconds
Started Aug 19 05:55:40 PM PDT 24
Finished Aug 19 05:56:35 PM PDT 24
Peak memory 202208 kb
Host smart-2eac4edd-41e4-4525-a88b-a1a0ab91e9e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259977627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2259977627
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1269129983
Short name T24
Test name
Test status
Simulation time 4650250493 ps
CPU time 3.95 seconds
Started Aug 19 05:55:47 PM PDT 24
Finished Aug 19 05:55:51 PM PDT 24
Peak memory 202112 kb
Host smart-80f1b640-5eae-4fac-b2d9-36e36122b72c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269129983 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1269129983
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.885189523
Short name T366
Test name
Test status
Simulation time 325658676 ps
CPU time 0.99 seconds
Started Aug 19 05:54:56 PM PDT 24
Finished Aug 19 05:54:57 PM PDT 24
Peak memory 201984 kb
Host smart-e5feebfc-022a-4035-a39e-3ff21667abc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885189523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.885189523
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2857725140
Short name T271
Test name
Test status
Simulation time 496487174417 ps
CPU time 1098.11 seconds
Started Aug 19 05:54:47 PM PDT 24
Finished Aug 19 06:13:05 PM PDT 24
Peak memory 202156 kb
Host smart-1460e847-e432-4e30-8c95-13f0b1405194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857725140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2857725140
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2169679191
Short name T796
Test name
Test status
Simulation time 165224307529 ps
CPU time 100.57 seconds
Started Aug 19 05:54:53 PM PDT 24
Finished Aug 19 05:56:34 PM PDT 24
Peak memory 202124 kb
Host smart-16591fdd-a50f-4d5a-8d3b-1976a9c1661f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169679191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2169679191
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.928087881
Short name T162
Test name
Test status
Simulation time 495717048467 ps
CPU time 275.94 seconds
Started Aug 19 05:54:53 PM PDT 24
Finished Aug 19 05:59:29 PM PDT 24
Peak memory 202176 kb
Host smart-1d41c053-3268-4581-bb33-d17b7fa3b066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928087881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.928087881
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.188357729
Short name T437
Test name
Test status
Simulation time 165024820612 ps
CPU time 238.49 seconds
Started Aug 19 05:55:03 PM PDT 24
Finished Aug 19 05:59:01 PM PDT 24
Peak memory 202124 kb
Host smart-b9d248b4-0a8b-4a11-8c56-05da8b39d34d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=188357729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.188357729
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.4265233600
Short name T536
Test name
Test status
Simulation time 174281969358 ps
CPU time 193.61 seconds
Started Aug 19 05:55:02 PM PDT 24
Finished Aug 19 05:58:15 PM PDT 24
Peak memory 202132 kb
Host smart-d9f5d15c-61c7-4ae4-9876-613673a42e42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265233600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.4265233600
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.4256990250
Short name T393
Test name
Test status
Simulation time 608834290972 ps
CPU time 668.25 seconds
Started Aug 19 05:54:45 PM PDT 24
Finished Aug 19 06:05:53 PM PDT 24
Peak memory 202172 kb
Host smart-cedb8b5f-2d69-48a2-927a-7ff4cd976246
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256990250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.4256990250
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2139108180
Short name T725
Test name
Test status
Simulation time 111796052982 ps
CPU time 424.46 seconds
Started Aug 19 05:55:01 PM PDT 24
Finished Aug 19 06:02:06 PM PDT 24
Peak memory 202452 kb
Host smart-bc55cae5-aacb-45f4-b8c6-d885726fd360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139108180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2139108180
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2494062663
Short name T184
Test name
Test status
Simulation time 36216465157 ps
CPU time 79 seconds
Started Aug 19 05:54:47 PM PDT 24
Finished Aug 19 05:56:07 PM PDT 24
Peak memory 201968 kb
Host smart-6cc70b0f-d97a-4551-a9d2-f670512dd54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494062663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2494062663
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.182160191
Short name T481
Test name
Test status
Simulation time 4287134017 ps
CPU time 5.59 seconds
Started Aug 19 05:55:00 PM PDT 24
Finished Aug 19 05:55:06 PM PDT 24
Peak memory 201976 kb
Host smart-2e620e93-e5b8-4616-b13b-6c24bbdea974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182160191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.182160191
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3489762007
Short name T62
Test name
Test status
Simulation time 8193992406 ps
CPU time 5.66 seconds
Started Aug 19 05:54:58 PM PDT 24
Finished Aug 19 05:55:04 PM PDT 24
Peak memory 218516 kb
Host smart-f8a079b8-e90f-40bb-a712-6c8b8ff9601a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489762007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3489762007
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3828568185
Short name T534
Test name
Test status
Simulation time 5938303110 ps
CPU time 14.66 seconds
Started Aug 19 05:55:02 PM PDT 24
Finished Aug 19 05:55:16 PM PDT 24
Peak memory 201996 kb
Host smart-5f7b2d6e-1155-4e26-ab93-1a84b730cabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828568185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3828568185
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.536219332
Short name T234
Test name
Test status
Simulation time 498730794312 ps
CPU time 274.74 seconds
Started Aug 19 05:54:51 PM PDT 24
Finished Aug 19 05:59:26 PM PDT 24
Peak memory 202132 kb
Host smart-fbd3d0d7-865f-4458-890d-f875d7c741e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536219332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.536219332
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1108934197
Short name T340
Test name
Test status
Simulation time 18579079933 ps
CPU time 27.56 seconds
Started Aug 19 05:54:54 PM PDT 24
Finished Aug 19 05:55:21 PM PDT 24
Peak memory 217940 kb
Host smart-52140e20-1d92-4fb8-b70b-4b3885529056
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108934197 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1108934197
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2056624645
Short name T710
Test name
Test status
Simulation time 555841942 ps
CPU time 0.89 seconds
Started Aug 19 05:55:49 PM PDT 24
Finished Aug 19 05:55:50 PM PDT 24
Peak memory 201968 kb
Host smart-e01fa2ed-ddb7-4b35-865a-552fc179d07e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056624645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2056624645
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1370498761
Short name T245
Test name
Test status
Simulation time 204194853158 ps
CPU time 496.73 seconds
Started Aug 19 05:55:53 PM PDT 24
Finished Aug 19 06:04:10 PM PDT 24
Peak memory 202220 kb
Host smart-66e976f1-4503-48cc-a86b-a3bdab931228
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370498761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1370498761
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1544074774
Short name T674
Test name
Test status
Simulation time 417512892383 ps
CPU time 117.36 seconds
Started Aug 19 05:55:46 PM PDT 24
Finished Aug 19 05:57:43 PM PDT 24
Peak memory 202136 kb
Host smart-a2949121-bc04-4ab4-a500-dccb3f3468cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544074774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1544074774
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3938062696
Short name T260
Test name
Test status
Simulation time 489293239468 ps
CPU time 139.43 seconds
Started Aug 19 05:55:47 PM PDT 24
Finished Aug 19 05:58:07 PM PDT 24
Peak memory 202144 kb
Host smart-8e92c122-5467-4e81-b366-0a374c71618e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938062696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3938062696
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2437483052
Short name T595
Test name
Test status
Simulation time 163701767677 ps
CPU time 91.77 seconds
Started Aug 19 05:55:52 PM PDT 24
Finished Aug 19 05:57:24 PM PDT 24
Peak memory 202204 kb
Host smart-4fee79fb-9a33-4910-9b38-3577ebe5935a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437483052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2437483052
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2399862717
Short name T132
Test name
Test status
Simulation time 162146061016 ps
CPU time 68.82 seconds
Started Aug 19 05:55:42 PM PDT 24
Finished Aug 19 05:56:51 PM PDT 24
Peak memory 202144 kb
Host smart-59b8d13c-010c-49f0-a66a-0412bcc6e360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399862717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2399862717
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.713139253
Short name T382
Test name
Test status
Simulation time 494323033673 ps
CPU time 1097.64 seconds
Started Aug 19 05:55:51 PM PDT 24
Finished Aug 19 06:14:09 PM PDT 24
Peak memory 202152 kb
Host smart-e04007fb-1e91-4817-ab43-b78cc21aaffc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=713139253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.713139253
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.694092844
Short name T779
Test name
Test status
Simulation time 191742386880 ps
CPU time 70.06 seconds
Started Aug 19 05:55:50 PM PDT 24
Finished Aug 19 05:57:01 PM PDT 24
Peak memory 202144 kb
Host smart-04914cfd-f83d-4c95-86e8-622ede46dd9c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694092844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.694092844
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3375414964
Short name T589
Test name
Test status
Simulation time 600141314535 ps
CPU time 1412.31 seconds
Started Aug 19 05:55:52 PM PDT 24
Finished Aug 19 06:19:24 PM PDT 24
Peak memory 202284 kb
Host smart-9d847555-40a9-476e-b7a8-b5d86f133324
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375414964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3375414964
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1126180164
Short name T339
Test name
Test status
Simulation time 126986151368 ps
CPU time 509.92 seconds
Started Aug 19 05:55:46 PM PDT 24
Finished Aug 19 06:04:16 PM PDT 24
Peak memory 202388 kb
Host smart-b30717ce-20af-454a-abc0-f9f83a472bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126180164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1126180164
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2809735929
Short name T430
Test name
Test status
Simulation time 39568253703 ps
CPU time 15.44 seconds
Started Aug 19 05:55:54 PM PDT 24
Finished Aug 19 05:56:10 PM PDT 24
Peak memory 201220 kb
Host smart-77b85833-f815-42d1-91c0-6d6285d40a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809735929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2809735929
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3397827129
Short name T670
Test name
Test status
Simulation time 4523763702 ps
CPU time 5.94 seconds
Started Aug 19 05:55:43 PM PDT 24
Finished Aug 19 05:55:49 PM PDT 24
Peak memory 201980 kb
Host smart-880b0f1f-b468-4357-992f-0f309794f52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397827129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3397827129
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3489793789
Short name T185
Test name
Test status
Simulation time 5917065152 ps
CPU time 3.64 seconds
Started Aug 19 05:55:48 PM PDT 24
Finished Aug 19 05:55:52 PM PDT 24
Peak memory 201976 kb
Host smart-5b26c6a2-87a9-45f1-906f-44e9ec1fcc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489793789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3489793789
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3516478958
Short name T686
Test name
Test status
Simulation time 216993637621 ps
CPU time 244.84 seconds
Started Aug 19 05:55:51 PM PDT 24
Finished Aug 19 05:59:56 PM PDT 24
Peak memory 202164 kb
Host smart-456fa8a3-3b17-40fa-a920-74cc844e7a24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516478958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3516478958
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.260241038
Short name T12
Test name
Test status
Simulation time 2842274040 ps
CPU time 8.97 seconds
Started Aug 19 05:55:51 PM PDT 24
Finished Aug 19 05:56:00 PM PDT 24
Peak memory 210484 kb
Host smart-8220c894-3dd3-484a-a788-2b542108ae29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260241038 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.260241038
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.269688347
Short name T401
Test name
Test status
Simulation time 530076094 ps
CPU time 1.8 seconds
Started Aug 19 05:55:52 PM PDT 24
Finished Aug 19 05:55:54 PM PDT 24
Peak memory 201964 kb
Host smart-7fae44d4-16b6-4e86-92b5-51ca46fc96d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269688347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.269688347
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.878954057
Short name T305
Test name
Test status
Simulation time 493890626401 ps
CPU time 1038.97 seconds
Started Aug 19 05:55:43 PM PDT 24
Finished Aug 19 06:13:02 PM PDT 24
Peak memory 202144 kb
Host smart-421be676-b662-48a2-95f7-8808cbbbe01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878954057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.878954057
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1249342440
Short name T418
Test name
Test status
Simulation time 485506502520 ps
CPU time 1132.75 seconds
Started Aug 19 05:55:40 PM PDT 24
Finished Aug 19 06:14:33 PM PDT 24
Peak memory 202164 kb
Host smart-e160eea4-09e0-4fdf-9a87-3e76d57b6291
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249342440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1249342440
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.876737176
Short name T121
Test name
Test status
Simulation time 165430073870 ps
CPU time 96.39 seconds
Started Aug 19 05:55:49 PM PDT 24
Finished Aug 19 05:57:25 PM PDT 24
Peak memory 202164 kb
Host smart-16bfedab-d5fc-4ef9-a2fe-6dfd3c205f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876737176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.876737176
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2597588342
Short name T765
Test name
Test status
Simulation time 497517988063 ps
CPU time 306.52 seconds
Started Aug 19 05:55:51 PM PDT 24
Finished Aug 19 06:00:58 PM PDT 24
Peak memory 202072 kb
Host smart-31357c84-346c-4d60-b54e-c8c61736aad4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597588342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2597588342
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.389725484
Short name T661
Test name
Test status
Simulation time 182744589537 ps
CPU time 192.3 seconds
Started Aug 19 05:55:55 PM PDT 24
Finished Aug 19 05:59:07 PM PDT 24
Peak memory 202228 kb
Host smart-98fc78de-61bf-4d43-969e-712edfe0d218
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389725484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.389725484
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2717419677
Short name T21
Test name
Test status
Simulation time 609319797850 ps
CPU time 189.5 seconds
Started Aug 19 05:55:49 PM PDT 24
Finished Aug 19 05:58:59 PM PDT 24
Peak memory 202080 kb
Host smart-15182dfb-bd22-4fee-8c00-15b301da6e69
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717419677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2717419677
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.664522224
Short name T187
Test name
Test status
Simulation time 69006011301 ps
CPU time 315.72 seconds
Started Aug 19 05:55:50 PM PDT 24
Finished Aug 19 06:01:06 PM PDT 24
Peak memory 202392 kb
Host smart-267ea6b7-6393-43ca-bded-ac08aa94bc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664522224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.664522224
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.250897539
Short name T709
Test name
Test status
Simulation time 22475670466 ps
CPU time 49.62 seconds
Started Aug 19 05:55:41 PM PDT 24
Finished Aug 19 05:56:31 PM PDT 24
Peak memory 202004 kb
Host smart-5dd288d2-7068-44b7-a15c-d4d15c903249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250897539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.250897539
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.72461777
Short name T584
Test name
Test status
Simulation time 4020451286 ps
CPU time 8.31 seconds
Started Aug 19 05:55:53 PM PDT 24
Finished Aug 19 05:56:01 PM PDT 24
Peak memory 201672 kb
Host smart-675d2bdf-6315-44f1-8a86-a4dfe5bbd573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72461777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.72461777
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2011038926
Short name T442
Test name
Test status
Simulation time 6003488122 ps
CPU time 8.84 seconds
Started Aug 19 05:55:50 PM PDT 24
Finished Aug 19 05:55:59 PM PDT 24
Peak memory 201976 kb
Host smart-bec18f60-9e1c-4fbf-b678-bf5fca5bb949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011038926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2011038926
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3447917006
Short name T227
Test name
Test status
Simulation time 183301250129 ps
CPU time 208.4 seconds
Started Aug 19 05:55:49 PM PDT 24
Finished Aug 19 05:59:17 PM PDT 24
Peak memory 202232 kb
Host smart-7dd4e39a-e895-49b8-a3ee-47e217f7ba70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447917006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3447917006
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3584512629
Short name T13
Test name
Test status
Simulation time 10595228341 ps
CPU time 3.64 seconds
Started Aug 19 05:55:46 PM PDT 24
Finished Aug 19 05:55:50 PM PDT 24
Peak memory 202356 kb
Host smart-0ea4f8e7-cf30-4925-bb49-4730ea912a9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584512629 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3584512629
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2369504571
Short name T477
Test name
Test status
Simulation time 469177559 ps
CPU time 0.83 seconds
Started Aug 19 05:55:49 PM PDT 24
Finished Aug 19 05:55:50 PM PDT 24
Peak memory 201968 kb
Host smart-6dc95448-cf40-4fa6-8a90-f24559b4c73c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369504571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2369504571
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3469607453
Short name T506
Test name
Test status
Simulation time 326885640294 ps
CPU time 58.61 seconds
Started Aug 19 05:55:49 PM PDT 24
Finished Aug 19 05:56:47 PM PDT 24
Peak memory 202204 kb
Host smart-2a40d6de-87cc-460b-ac11-9f3c04d05d99
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469607453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3469607453
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.4271670974
Short name T278
Test name
Test status
Simulation time 169929834207 ps
CPU time 108.45 seconds
Started Aug 19 05:55:50 PM PDT 24
Finished Aug 19 05:57:39 PM PDT 24
Peak memory 202248 kb
Host smart-6ff627c7-341a-41b3-bdad-a1cc1bad21d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271670974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.4271670974
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.810648736
Short name T586
Test name
Test status
Simulation time 164421807220 ps
CPU time 97.34 seconds
Started Aug 19 05:55:52 PM PDT 24
Finished Aug 19 05:57:29 PM PDT 24
Peak memory 202180 kb
Host smart-45f75b4d-86d7-46a1-8764-f2a5d814ff79
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=810648736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.810648736
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2463361234
Short name T287
Test name
Test status
Simulation time 494821253671 ps
CPU time 590.79 seconds
Started Aug 19 05:55:51 PM PDT 24
Finished Aug 19 06:05:42 PM PDT 24
Peak memory 202148 kb
Host smart-7fdbe2de-6124-4268-a38e-8e36b7371256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463361234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2463361234
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1259905366
Short name T420
Test name
Test status
Simulation time 498714742033 ps
CPU time 1066.52 seconds
Started Aug 19 05:55:44 PM PDT 24
Finished Aug 19 06:13:31 PM PDT 24
Peak memory 202112 kb
Host smart-c66facee-2b5f-4c6e-b926-3d2e0ace97bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259905366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1259905366
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2416709843
Short name T247
Test name
Test status
Simulation time 183504949953 ps
CPU time 395.6 seconds
Started Aug 19 05:55:50 PM PDT 24
Finished Aug 19 06:02:26 PM PDT 24
Peak memory 202168 kb
Host smart-612ccd8b-bfdd-45ac-94da-d361817aeb12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416709843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2416709843
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3818688023
Short name T398
Test name
Test status
Simulation time 406065392635 ps
CPU time 827.05 seconds
Started Aug 19 05:55:52 PM PDT 24
Finished Aug 19 06:09:40 PM PDT 24
Peak memory 202148 kb
Host smart-39f32e54-c54b-4e7a-8b7f-ef0b8eb2a27c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818688023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3818688023
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.442236020
Short name T344
Test name
Test status
Simulation time 128218605669 ps
CPU time 620.55 seconds
Started Aug 19 05:55:48 PM PDT 24
Finished Aug 19 06:06:09 PM PDT 24
Peak memory 202404 kb
Host smart-2be45cde-a34a-49fd-9938-30b533f8852f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442236020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.442236020
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2269178946
Short name T517
Test name
Test status
Simulation time 41558787626 ps
CPU time 14.36 seconds
Started Aug 19 05:55:54 PM PDT 24
Finished Aug 19 05:56:09 PM PDT 24
Peak memory 201976 kb
Host smart-41392ea5-9c96-4a95-a7e3-423fb8979845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269178946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2269178946
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3946183775
Short name T78
Test name
Test status
Simulation time 3577373570 ps
CPU time 2.49 seconds
Started Aug 19 05:55:51 PM PDT 24
Finished Aug 19 05:55:54 PM PDT 24
Peak memory 201980 kb
Host smart-455b7c39-a0a9-469a-87f2-23978172dc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946183775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3946183775
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3458089373
Short name T721
Test name
Test status
Simulation time 5758158736 ps
CPU time 12.92 seconds
Started Aug 19 05:55:42 PM PDT 24
Finished Aug 19 05:55:55 PM PDT 24
Peak memory 201988 kb
Host smart-7a1dac61-1d24-43e2-bf0d-12307e8f5d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458089373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3458089373
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1335489179
Short name T548
Test name
Test status
Simulation time 144629134398 ps
CPU time 305.31 seconds
Started Aug 19 05:55:51 PM PDT 24
Finished Aug 19 06:00:56 PM PDT 24
Peak memory 202412 kb
Host smart-88c01f37-58a8-49fe-bded-4e7266390d5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335489179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1335489179
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2911603844
Short name T183
Test name
Test status
Simulation time 394101326 ps
CPU time 1.45 seconds
Started Aug 19 05:56:21 PM PDT 24
Finished Aug 19 05:56:23 PM PDT 24
Peak memory 201960 kb
Host smart-8020b4c9-7bda-4231-affb-682bb1192e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911603844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2911603844
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.155311815
Short name T149
Test name
Test status
Simulation time 517740221052 ps
CPU time 280.21 seconds
Started Aug 19 05:55:55 PM PDT 24
Finished Aug 19 06:00:35 PM PDT 24
Peak memory 202132 kb
Host smart-6d34477a-b245-4174-8898-5a2d78a7792d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155311815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.155311815
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.4104561612
Short name T128
Test name
Test status
Simulation time 343745417875 ps
CPU time 211.98 seconds
Started Aug 19 05:55:52 PM PDT 24
Finished Aug 19 05:59:24 PM PDT 24
Peak memory 202148 kb
Host smart-116d924a-7aaf-4810-aea8-ddf01342a083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104561612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.4104561612
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.4250199525
Short name T363
Test name
Test status
Simulation time 492853539056 ps
CPU time 1127.86 seconds
Started Aug 19 05:55:58 PM PDT 24
Finished Aug 19 06:14:46 PM PDT 24
Peak memory 202188 kb
Host smart-6cacb374-a154-46ac-8dbb-8259ee7a95fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250199525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.4250199525
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.138322539
Short name T698
Test name
Test status
Simulation time 155949521883 ps
CPU time 289.62 seconds
Started Aug 19 05:55:51 PM PDT 24
Finished Aug 19 06:00:41 PM PDT 24
Peak memory 202164 kb
Host smart-a2ea7db0-876a-47e2-88af-bb06eaf8030f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138322539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.138322539
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.406374327
Short name T784
Test name
Test status
Simulation time 495513932387 ps
CPU time 304.28 seconds
Started Aug 19 05:55:51 PM PDT 24
Finished Aug 19 06:00:56 PM PDT 24
Peak memory 202164 kb
Host smart-48708549-cf7a-4e16-946b-4821e1d54338
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=406374327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.406374327
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2823210335
Short name T127
Test name
Test status
Simulation time 546031622897 ps
CPU time 1181.23 seconds
Started Aug 19 05:55:53 PM PDT 24
Finished Aug 19 06:15:34 PM PDT 24
Peak memory 202172 kb
Host smart-ee5fa1c8-3824-4a5d-b041-a8567863a78b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823210335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2823210335
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.407825062
Short name T762
Test name
Test status
Simulation time 194218264869 ps
CPU time 116.1 seconds
Started Aug 19 05:55:54 PM PDT 24
Finished Aug 19 05:57:50 PM PDT 24
Peak memory 202148 kb
Host smart-f99b50a5-c47f-4ac2-acc9-132c3637c442
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407825062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.407825062
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3618980341
Short name T36
Test name
Test status
Simulation time 105249351040 ps
CPU time 565.95 seconds
Started Aug 19 05:55:51 PM PDT 24
Finished Aug 19 06:05:17 PM PDT 24
Peak memory 202400 kb
Host smart-6c8aea48-689d-4035-8ef9-d23f1c84cc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618980341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3618980341
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2670762300
Short name T423
Test name
Test status
Simulation time 40921697452 ps
CPU time 17.37 seconds
Started Aug 19 05:55:54 PM PDT 24
Finished Aug 19 05:56:12 PM PDT 24
Peak memory 201976 kb
Host smart-a9de655d-885e-42b3-bfeb-aac781212600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670762300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2670762300
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1327831895
Short name T531
Test name
Test status
Simulation time 2904192673 ps
CPU time 1.91 seconds
Started Aug 19 05:55:54 PM PDT 24
Finished Aug 19 05:55:56 PM PDT 24
Peak memory 201976 kb
Host smart-6bb07744-5229-4afe-ae44-ee7626f21d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327831895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1327831895
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.151496544
Short name T783
Test name
Test status
Simulation time 5786596283 ps
CPU time 7.67 seconds
Started Aug 19 05:55:47 PM PDT 24
Finished Aug 19 05:55:55 PM PDT 24
Peak memory 201972 kb
Host smart-9236f29f-4633-49b2-b5e2-4265d7524022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151496544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.151496544
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.710954842
Short name T31
Test name
Test status
Simulation time 130329549700 ps
CPU time 538.83 seconds
Started Aug 19 05:55:59 PM PDT 24
Finished Aug 19 06:04:58 PM PDT 24
Peak memory 202400 kb
Host smart-1ce73573-55ca-4987-8974-22db92929c73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710954842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
710954842
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3959235859
Short name T717
Test name
Test status
Simulation time 16650900929 ps
CPU time 25.22 seconds
Started Aug 19 05:55:51 PM PDT 24
Finished Aug 19 05:56:17 PM PDT 24
Peak memory 210504 kb
Host smart-aa2d98ac-6f6d-4d5a-bb50-256746777d3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959235859 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3959235859
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1945546631
Short name T668
Test name
Test status
Simulation time 468954588 ps
CPU time 0.86 seconds
Started Aug 19 05:55:53 PM PDT 24
Finished Aug 19 05:55:54 PM PDT 24
Peak memory 201988 kb
Host smart-2c606e7a-6ad4-4c9e-9d04-9b0355cba6c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945546631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1945546631
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.363915250
Short name T331
Test name
Test status
Simulation time 514990201944 ps
CPU time 554.43 seconds
Started Aug 19 05:56:00 PM PDT 24
Finished Aug 19 06:05:15 PM PDT 24
Peak memory 202156 kb
Host smart-940fcb89-7076-4119-b1f6-744f20e5984c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363915250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.363915250
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.695526916
Short name T314
Test name
Test status
Simulation time 496102458936 ps
CPU time 856.86 seconds
Started Aug 19 05:55:50 PM PDT 24
Finished Aug 19 06:10:07 PM PDT 24
Peak memory 202168 kb
Host smart-a0e2ad35-a7a5-4cb0-8789-218743e16d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695526916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.695526916
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.4081861164
Short name T499
Test name
Test status
Simulation time 324670742101 ps
CPU time 370.39 seconds
Started Aug 19 05:55:45 PM PDT 24
Finished Aug 19 06:01:55 PM PDT 24
Peak memory 202108 kb
Host smart-3fcc88ba-95fc-4af0-98bd-5c81d20a0243
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081861164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.4081861164
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3615235763
Short name T137
Test name
Test status
Simulation time 326043231177 ps
CPU time 58.54 seconds
Started Aug 19 05:55:51 PM PDT 24
Finished Aug 19 05:56:50 PM PDT 24
Peak memory 201948 kb
Host smart-73a5622a-3392-42d2-bb5a-a80c89479bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615235763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3615235763
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.449409774
Short name T160
Test name
Test status
Simulation time 493418266479 ps
CPU time 487.75 seconds
Started Aug 19 05:55:55 PM PDT 24
Finished Aug 19 06:04:03 PM PDT 24
Peak memory 202136 kb
Host smart-4840ffa6-346f-43de-9cb1-9ab67bd9ff7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=449409774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.449409774
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.4292707370
Short name T223
Test name
Test status
Simulation time 186307881873 ps
CPU time 45.46 seconds
Started Aug 19 05:55:57 PM PDT 24
Finished Aug 19 05:56:42 PM PDT 24
Peak memory 202140 kb
Host smart-30e86ff1-7e2d-442d-940f-5377fbaed2d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292707370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.4292707370
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3495522109
Short name T473
Test name
Test status
Simulation time 401660860383 ps
CPU time 154.03 seconds
Started Aug 19 05:55:58 PM PDT 24
Finished Aug 19 05:58:32 PM PDT 24
Peak memory 202140 kb
Host smart-a2b31e2e-c325-499d-8cdc-1debaeb5a938
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495522109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3495522109
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3370557008
Short name T518
Test name
Test status
Simulation time 127903557146 ps
CPU time 532.38 seconds
Started Aug 19 05:55:57 PM PDT 24
Finished Aug 19 06:04:50 PM PDT 24
Peak memory 202440 kb
Host smart-247c0619-04d8-4b3f-b3fb-eb3071ad0315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370557008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3370557008
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3664330831
Short name T373
Test name
Test status
Simulation time 37470334320 ps
CPU time 87.44 seconds
Started Aug 19 05:55:52 PM PDT 24
Finished Aug 19 05:57:20 PM PDT 24
Peak memory 201980 kb
Host smart-52929995-b38f-4c94-9c42-70858d03e628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664330831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3664330831
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.4252513216
Short name T549
Test name
Test status
Simulation time 4659746748 ps
CPU time 11.64 seconds
Started Aug 19 05:56:01 PM PDT 24
Finished Aug 19 05:56:13 PM PDT 24
Peak memory 201988 kb
Host smart-ae29d713-9db8-4526-91c3-988dc05daf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252513216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.4252513216
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3892210895
Short name T358
Test name
Test status
Simulation time 5845523109 ps
CPU time 5.31 seconds
Started Aug 19 05:55:51 PM PDT 24
Finished Aug 19 05:55:56 PM PDT 24
Peak memory 201980 kb
Host smart-5fd7a613-b0eb-4298-8a09-24d0ac6867d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892210895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3892210895
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.582366351
Short name T676
Test name
Test status
Simulation time 126076017985 ps
CPU time 623.18 seconds
Started Aug 19 05:55:53 PM PDT 24
Finished Aug 19 06:06:17 PM PDT 24
Peak memory 202412 kb
Host smart-006a5b77-d239-4dcd-9dc7-6e7f28941248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582366351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
582366351
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3602222522
Short name T290
Test name
Test status
Simulation time 17492221931 ps
CPU time 26.07 seconds
Started Aug 19 05:56:02 PM PDT 24
Finished Aug 19 05:56:28 PM PDT 24
Peak memory 210804 kb
Host smart-fc3fc66f-190f-4ef3-b9cf-5397b7c1b4db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602222522 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3602222522
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1523668972
Short name T764
Test name
Test status
Simulation time 325781234 ps
CPU time 1.44 seconds
Started Aug 19 05:56:01 PM PDT 24
Finished Aug 19 05:56:02 PM PDT 24
Peak memory 202000 kb
Host smart-78773ded-a54b-4594-9a50-94c4001d1efd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523668972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1523668972
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3148534381
Short name T780
Test name
Test status
Simulation time 478220266022 ps
CPU time 624.43 seconds
Started Aug 19 05:55:59 PM PDT 24
Finished Aug 19 06:06:24 PM PDT 24
Peak memory 202172 kb
Host smart-e66b6828-2269-48ca-90b6-e8308e94ceea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148534381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3148534381
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.93350293
Short name T546
Test name
Test status
Simulation time 163925432090 ps
CPU time 54.94 seconds
Started Aug 19 05:55:59 PM PDT 24
Finished Aug 19 05:56:54 PM PDT 24
Peak memory 202140 kb
Host smart-74323120-b136-4313-b42e-f6155c42bcc8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=93350293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt
_fixed.93350293
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.811400974
Short name T69
Test name
Test status
Simulation time 502072085588 ps
CPU time 276.82 seconds
Started Aug 19 05:56:04 PM PDT 24
Finished Aug 19 06:00:41 PM PDT 24
Peak memory 202108 kb
Host smart-5f417108-ba3b-4594-afea-09ae28159f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811400974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.811400974
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1503486150
Short name T392
Test name
Test status
Simulation time 161402480640 ps
CPU time 186.39 seconds
Started Aug 19 05:55:53 PM PDT 24
Finished Aug 19 05:59:00 PM PDT 24
Peak memory 202112 kb
Host smart-6ebaf1f6-6005-44fd-83a2-bbe33e51bf1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503486150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1503486150
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.526182271
Short name T699
Test name
Test status
Simulation time 172191266388 ps
CPU time 187.89 seconds
Started Aug 19 05:56:00 PM PDT 24
Finished Aug 19 05:59:08 PM PDT 24
Peak memory 202200 kb
Host smart-5ef4e712-49e9-450c-9d53-8e00aae62d21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526182271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.526182271
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3340905109
Short name T791
Test name
Test status
Simulation time 199425966827 ps
CPU time 236.2 seconds
Started Aug 19 05:55:57 PM PDT 24
Finished Aug 19 05:59:53 PM PDT 24
Peak memory 202116 kb
Host smart-72d8bf78-f674-4f3f-b855-daeba2a77e28
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340905109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3340905109
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1546716104
Short name T190
Test name
Test status
Simulation time 120205452370 ps
CPU time 627.63 seconds
Started Aug 19 05:55:56 PM PDT 24
Finished Aug 19 06:06:24 PM PDT 24
Peak memory 202388 kb
Host smart-45dc352f-6339-49da-8576-a4257272e381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546716104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1546716104
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1331888802
Short name T565
Test name
Test status
Simulation time 24490508141 ps
CPU time 13.05 seconds
Started Aug 19 05:56:00 PM PDT 24
Finished Aug 19 05:56:13 PM PDT 24
Peak memory 201968 kb
Host smart-e1e229e7-90e5-4700-88bd-698bfb8897cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331888802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1331888802
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2488453450
Short name T182
Test name
Test status
Simulation time 3250201212 ps
CPU time 3.95 seconds
Started Aug 19 05:55:55 PM PDT 24
Finished Aug 19 05:55:59 PM PDT 24
Peak memory 201620 kb
Host smart-45db602f-c485-447c-808c-0c10237ee270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488453450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2488453450
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3163689472
Short name T444
Test name
Test status
Simulation time 5705362225 ps
CPU time 14.87 seconds
Started Aug 19 05:55:57 PM PDT 24
Finished Aug 19 05:56:12 PM PDT 24
Peak memory 201968 kb
Host smart-7f531b76-eecb-4fc6-a672-a6e5450e1779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163689472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3163689472
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3517731861
Short name T751
Test name
Test status
Simulation time 2149539988 ps
CPU time 9.36 seconds
Started Aug 19 05:55:54 PM PDT 24
Finished Aug 19 05:56:04 PM PDT 24
Peak memory 209856 kb
Host smart-6e8c21a9-eb0f-48d4-adc7-ea5cd7108157
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517731861 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3517731861
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.464114775
Short name T671
Test name
Test status
Simulation time 318110977 ps
CPU time 0.8 seconds
Started Aug 19 05:56:02 PM PDT 24
Finished Aug 19 05:56:03 PM PDT 24
Peak memory 202008 kb
Host smart-74a2485d-e697-4183-aa64-b3a98a853110
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464114775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.464114775
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.640328700
Short name T152
Test name
Test status
Simulation time 503552215583 ps
CPU time 103.98 seconds
Started Aug 19 05:56:02 PM PDT 24
Finished Aug 19 05:57:46 PM PDT 24
Peak memory 202148 kb
Host smart-53965098-6819-468a-ba84-53cab494e755
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640328700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.640328700
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3027527927
Short name T329
Test name
Test status
Simulation time 373186237125 ps
CPU time 167.83 seconds
Started Aug 19 05:56:00 PM PDT 24
Finished Aug 19 05:58:48 PM PDT 24
Peak memory 202192 kb
Host smart-62ad8781-d3b2-4d08-b74e-06b9d03f4d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027527927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3027527927
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1551300371
Short name T491
Test name
Test status
Simulation time 327938670850 ps
CPU time 761.26 seconds
Started Aug 19 05:56:01 PM PDT 24
Finished Aug 19 06:08:42 PM PDT 24
Peak memory 202128 kb
Host smart-766d1b95-3253-4c63-b5ed-baa0878fac44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551300371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1551300371
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.886431991
Short name T713
Test name
Test status
Simulation time 323750371729 ps
CPU time 191.27 seconds
Started Aug 19 05:56:03 PM PDT 24
Finished Aug 19 05:59:15 PM PDT 24
Peak memory 202036 kb
Host smart-e0b6876e-850f-49d2-bf6b-7337bc824e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886431991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.886431991
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3765008990
Short name T541
Test name
Test status
Simulation time 500557020508 ps
CPU time 305.5 seconds
Started Aug 19 05:56:03 PM PDT 24
Finished Aug 19 06:01:08 PM PDT 24
Peak memory 202128 kb
Host smart-51f03475-1efa-4ac1-aa37-7b81ed398a41
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765008990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3765008990
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1495512050
Short name T620
Test name
Test status
Simulation time 173882584781 ps
CPU time 387.82 seconds
Started Aug 19 05:56:03 PM PDT 24
Finished Aug 19 06:02:31 PM PDT 24
Peak memory 202132 kb
Host smart-18e298a1-f068-4578-85ae-71d54f055445
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495512050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1495512050
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.783183064
Short name T483
Test name
Test status
Simulation time 395873515533 ps
CPU time 173.5 seconds
Started Aug 19 05:56:00 PM PDT 24
Finished Aug 19 05:58:53 PM PDT 24
Peak memory 202176 kb
Host smart-6242a0f8-53aa-4a75-8c5c-f85334cb8cdc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783183064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.783183064
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2709940571
Short name T566
Test name
Test status
Simulation time 96567200219 ps
CPU time 527.45 seconds
Started Aug 19 05:56:05 PM PDT 24
Finished Aug 19 06:04:53 PM PDT 24
Peak memory 202440 kb
Host smart-70f5883a-439e-4fe2-9fb2-d8d180396f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709940571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2709940571
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2410127850
Short name T357
Test name
Test status
Simulation time 45506144459 ps
CPU time 95.44 seconds
Started Aug 19 05:56:03 PM PDT 24
Finished Aug 19 05:57:39 PM PDT 24
Peak memory 201980 kb
Host smart-cf43860d-4e42-4b74-b454-249e6d1a8836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410127850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2410127850
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1499919606
Short name T476
Test name
Test status
Simulation time 4429113695 ps
CPU time 11.12 seconds
Started Aug 19 05:56:05 PM PDT 24
Finished Aug 19 05:56:16 PM PDT 24
Peak memory 202008 kb
Host smart-e4e39b7b-e784-44a1-bc9e-4c3f3e6ec65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499919606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1499919606
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3084248549
Short name T704
Test name
Test status
Simulation time 5870123836 ps
CPU time 4.89 seconds
Started Aug 19 05:56:05 PM PDT 24
Finished Aug 19 05:56:10 PM PDT 24
Peak memory 201976 kb
Host smart-7c2e09a0-055c-43d7-8e0f-3e32ac205d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084248549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3084248549
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3661677042
Short name T76
Test name
Test status
Simulation time 440801472967 ps
CPU time 530.45 seconds
Started Aug 19 05:56:02 PM PDT 24
Finished Aug 19 06:04:53 PM PDT 24
Peak memory 213604 kb
Host smart-be1f4be3-b8bc-49ab-bfce-9235ee91103b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661677042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3661677042
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3590207391
Short name T27
Test name
Test status
Simulation time 38471883151 ps
CPU time 14.38 seconds
Started Aug 19 05:56:05 PM PDT 24
Finished Aug 19 05:56:19 PM PDT 24
Peak memory 218080 kb
Host smart-17016703-03dd-4801-beb3-2e4acaf0f819
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590207391 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3590207391
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.532955618
Short name T688
Test name
Test status
Simulation time 508062177 ps
CPU time 1.54 seconds
Started Aug 19 05:56:02 PM PDT 24
Finished Aug 19 05:56:04 PM PDT 24
Peak memory 201992 kb
Host smart-47cd19de-5d13-48d2-93d9-32448bb026b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532955618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.532955618
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2499730988
Short name T667
Test name
Test status
Simulation time 167075571873 ps
CPU time 25.24 seconds
Started Aug 19 05:56:06 PM PDT 24
Finished Aug 19 05:56:31 PM PDT 24
Peak memory 202216 kb
Host smart-41b92eb1-f376-4980-9ed2-92fbcfb8d503
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499730988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2499730988
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3875860813
Short name T211
Test name
Test status
Simulation time 182723921546 ps
CPU time 382.33 seconds
Started Aug 19 05:56:03 PM PDT 24
Finished Aug 19 06:02:26 PM PDT 24
Peak memory 202152 kb
Host smart-70b91017-9efa-4c05-aa57-4beb86f2a75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875860813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3875860813
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1349747133
Short name T136
Test name
Test status
Simulation time 161799632391 ps
CPU time 36.63 seconds
Started Aug 19 05:56:02 PM PDT 24
Finished Aug 19 05:56:38 PM PDT 24
Peak memory 202160 kb
Host smart-2588f13e-9a21-4b29-8d81-fa3b0619c994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349747133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1349747133
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2072371664
Short name T583
Test name
Test status
Simulation time 493976500730 ps
CPU time 312.66 seconds
Started Aug 19 05:56:04 PM PDT 24
Finished Aug 19 06:01:17 PM PDT 24
Peak memory 202124 kb
Host smart-7064cef4-d32b-4a24-b6e8-8bf3eddc2ce3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072371664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2072371664
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3642734907
Short name T632
Test name
Test status
Simulation time 488444030720 ps
CPU time 787.24 seconds
Started Aug 19 05:56:03 PM PDT 24
Finished Aug 19 06:09:10 PM PDT 24
Peak memory 202176 kb
Host smart-ad5f988f-31a5-4c05-a2d9-eba8ed4dba30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642734907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3642734907
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1861174520
Short name T520
Test name
Test status
Simulation time 168042707490 ps
CPU time 107.39 seconds
Started Aug 19 05:56:02 PM PDT 24
Finished Aug 19 05:57:50 PM PDT 24
Peak memory 202160 kb
Host smart-92d68332-01c7-434a-98e6-4f3e46a9a305
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861174520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1861174520
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.741459581
Short name T494
Test name
Test status
Simulation time 621307476385 ps
CPU time 358.62 seconds
Started Aug 19 05:56:00 PM PDT 24
Finished Aug 19 06:01:59 PM PDT 24
Peak memory 202156 kb
Host smart-9abd78a0-04cf-4645-a1df-f38c18d03809
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741459581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.741459581
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.4013585544
Short name T653
Test name
Test status
Simulation time 108796607958 ps
CPU time 382.57 seconds
Started Aug 19 05:56:02 PM PDT 24
Finished Aug 19 06:02:25 PM PDT 24
Peak memory 202440 kb
Host smart-d29a5354-d057-4666-9b2e-868017115ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013585544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.4013585544
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.107780744
Short name T523
Test name
Test status
Simulation time 28217278152 ps
CPU time 5.27 seconds
Started Aug 19 05:56:03 PM PDT 24
Finished Aug 19 05:56:09 PM PDT 24
Peak memory 202004 kb
Host smart-2fd30f2e-bbe8-4589-bfed-6042f8f4958a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107780744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.107780744
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.477083678
Short name T587
Test name
Test status
Simulation time 4929206682 ps
CPU time 10.57 seconds
Started Aug 19 05:56:01 PM PDT 24
Finished Aug 19 05:56:12 PM PDT 24
Peak memory 201968 kb
Host smart-34bd5cb1-e507-40f8-8b23-1695b43608aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477083678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.477083678
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2932233607
Short name T368
Test name
Test status
Simulation time 5696737357 ps
CPU time 13.97 seconds
Started Aug 19 05:56:03 PM PDT 24
Finished Aug 19 05:56:17 PM PDT 24
Peak memory 201952 kb
Host smart-3be22ac2-8079-4074-ba14-124fbfcf2f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932233607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2932233607
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.596379248
Short name T594
Test name
Test status
Simulation time 12769326718 ps
CPU time 8.84 seconds
Started Aug 19 05:56:02 PM PDT 24
Finished Aug 19 05:56:11 PM PDT 24
Peak memory 202156 kb
Host smart-fe3fd244-573d-4a5f-874b-8e6ac29c632a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596379248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
596379248
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1324992701
Short name T15
Test name
Test status
Simulation time 3239464551 ps
CPU time 5.8 seconds
Started Aug 19 05:56:02 PM PDT 24
Finished Aug 19 05:56:08 PM PDT 24
Peak memory 202116 kb
Host smart-a3bc991e-5e9a-496d-b6ea-65ab6b01d162
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324992701 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1324992701
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.212106489
Short name T720
Test name
Test status
Simulation time 353505950 ps
CPU time 0.83 seconds
Started Aug 19 05:56:19 PM PDT 24
Finished Aug 19 05:56:20 PM PDT 24
Peak memory 202004 kb
Host smart-a145dbed-4a77-4e58-a145-e576e22f609d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212106489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.212106489
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2771380848
Short name T220
Test name
Test status
Simulation time 330166914701 ps
CPU time 599.6 seconds
Started Aug 19 05:56:17 PM PDT 24
Finished Aug 19 06:06:17 PM PDT 24
Peak memory 202220 kb
Host smart-9b491d2e-b171-4608-87e2-4643584c13c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771380848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2771380848
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.175754087
Short name T292
Test name
Test status
Simulation time 328794501854 ps
CPU time 762.47 seconds
Started Aug 19 05:56:19 PM PDT 24
Finished Aug 19 06:09:02 PM PDT 24
Peak memory 202220 kb
Host smart-df934308-5d44-426f-8206-5ea897e72d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175754087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.175754087
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2061599131
Short name T387
Test name
Test status
Simulation time 163289786678 ps
CPU time 62.94 seconds
Started Aug 19 05:56:18 PM PDT 24
Finished Aug 19 05:57:21 PM PDT 24
Peak memory 202148 kb
Host smart-fbaa5b03-a41c-43d5-ab7b-d830c5562a13
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061599131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2061599131
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2614565003
Short name T560
Test name
Test status
Simulation time 490127683030 ps
CPU time 292.78 seconds
Started Aug 19 05:56:02 PM PDT 24
Finished Aug 19 06:00:55 PM PDT 24
Peak memory 202208 kb
Host smart-dee4362b-d13d-4134-9bc4-f435020966bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614565003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2614565003
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1262679625
Short name T562
Test name
Test status
Simulation time 328448596623 ps
CPU time 204.47 seconds
Started Aug 19 05:56:02 PM PDT 24
Finished Aug 19 05:59:27 PM PDT 24
Peak memory 202164 kb
Host smart-3174ba4a-f07e-4630-86c1-6573cfdf33ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262679625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1262679625
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3813244677
Short name T65
Test name
Test status
Simulation time 579987699631 ps
CPU time 361.85 seconds
Started Aug 19 05:56:18 PM PDT 24
Finished Aug 19 06:02:20 PM PDT 24
Peak memory 202152 kb
Host smart-4d30c059-c86a-46fc-8d82-df5bd76bb599
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813244677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3813244677
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3354065311
Short name T407
Test name
Test status
Simulation time 90867067752 ps
CPU time 338.02 seconds
Started Aug 19 05:56:18 PM PDT 24
Finished Aug 19 06:01:56 PM PDT 24
Peak memory 202384 kb
Host smart-4cb378f3-8c94-42d7-9d3a-e8eca0827fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354065311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3354065311
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2097620556
Short name T598
Test name
Test status
Simulation time 27627895269 ps
CPU time 30.9 seconds
Started Aug 19 05:56:18 PM PDT 24
Finished Aug 19 05:56:49 PM PDT 24
Peak memory 201996 kb
Host smart-6aacb7c5-b006-4518-b3fa-1ff840895af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097620556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2097620556
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1376370472
Short name T556
Test name
Test status
Simulation time 4831478372 ps
CPU time 2.94 seconds
Started Aug 19 05:56:20 PM PDT 24
Finished Aug 19 05:56:23 PM PDT 24
Peak memory 202000 kb
Host smart-2ad8a4af-03be-4bd7-bacf-f45e9447374d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376370472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1376370472
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1736118386
Short name T377
Test name
Test status
Simulation time 6234550182 ps
CPU time 1.65 seconds
Started Aug 19 05:56:04 PM PDT 24
Finished Aug 19 05:56:06 PM PDT 24
Peak memory 201988 kb
Host smart-9d5c2def-a6d9-4fab-9496-210500d8775c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736118386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1736118386
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3594360670
Short name T323
Test name
Test status
Simulation time 710330425671 ps
CPU time 27.94 seconds
Started Aug 19 05:56:19 PM PDT 24
Finished Aug 19 05:56:47 PM PDT 24
Peak memory 211956 kb
Host smart-126af0f8-22c7-4ab9-ba2e-a3b9c0de4873
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594360670 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3594360670
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2841990073
Short name T458
Test name
Test status
Simulation time 424256667 ps
CPU time 1.08 seconds
Started Aug 19 05:56:23 PM PDT 24
Finished Aug 19 05:56:24 PM PDT 24
Peak memory 202036 kb
Host smart-33a22160-e711-44ff-ba29-efb17dc50941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841990073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2841990073
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.4234900612
Short name T333
Test name
Test status
Simulation time 338721256035 ps
CPU time 361.39 seconds
Started Aug 19 05:56:19 PM PDT 24
Finished Aug 19 06:02:21 PM PDT 24
Peak memory 202164 kb
Host smart-0f99c360-4f01-4600-8863-4a4a3a63c2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234900612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.4234900612
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.4177328978
Short name T478
Test name
Test status
Simulation time 167448387290 ps
CPU time 185.15 seconds
Started Aug 19 05:56:19 PM PDT 24
Finished Aug 19 05:59:24 PM PDT 24
Peak memory 202116 kb
Host smart-b3892756-e773-45df-bd4e-22f1fd6f59c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177328978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.4177328978
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2362476905
Short name T659
Test name
Test status
Simulation time 333289661231 ps
CPU time 206.83 seconds
Started Aug 19 05:56:17 PM PDT 24
Finished Aug 19 05:59:44 PM PDT 24
Peak memory 202164 kb
Host smart-1415c96a-c67f-4dbc-b740-560af1ceea37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362476905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2362476905
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1380686804
Short name T445
Test name
Test status
Simulation time 319087440276 ps
CPU time 187.22 seconds
Started Aug 19 05:56:18 PM PDT 24
Finished Aug 19 05:59:25 PM PDT 24
Peak memory 202236 kb
Host smart-32904405-969b-4909-b56b-c966bede3a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380686804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1380686804
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3543740085
Short name T580
Test name
Test status
Simulation time 162271382789 ps
CPU time 70.36 seconds
Started Aug 19 05:56:19 PM PDT 24
Finished Aug 19 05:57:30 PM PDT 24
Peak memory 202116 kb
Host smart-fde14952-1046-4c72-b7d2-f7daf31961da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543740085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3543740085
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3771321396
Short name T564
Test name
Test status
Simulation time 397093232592 ps
CPU time 414.29 seconds
Started Aug 19 05:56:26 PM PDT 24
Finished Aug 19 06:03:20 PM PDT 24
Peak memory 202144 kb
Host smart-847a0072-dd71-476d-85a1-85826095eb33
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771321396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3771321396
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1327065340
Short name T196
Test name
Test status
Simulation time 87126071955 ps
CPU time 434.08 seconds
Started Aug 19 05:56:22 PM PDT 24
Finished Aug 19 06:03:37 PM PDT 24
Peak memory 202368 kb
Host smart-ad7a8d3b-581b-4948-9779-024e0e34aedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327065340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1327065340
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1846463624
Short name T563
Test name
Test status
Simulation time 41949972141 ps
CPU time 24.28 seconds
Started Aug 19 05:56:23 PM PDT 24
Finished Aug 19 05:56:48 PM PDT 24
Peak memory 201968 kb
Host smart-6b042573-325e-4493-ab68-b7a1d439536b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846463624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1846463624
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1276518853
Short name T511
Test name
Test status
Simulation time 4602435033 ps
CPU time 10.5 seconds
Started Aug 19 05:56:22 PM PDT 24
Finished Aug 19 05:56:33 PM PDT 24
Peak memory 201968 kb
Host smart-cec56d10-701e-4e48-bc9e-49abbe44ff9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276518853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1276518853
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3975145879
Short name T502
Test name
Test status
Simulation time 5834825746 ps
CPU time 7.75 seconds
Started Aug 19 05:56:17 PM PDT 24
Finished Aug 19 05:56:25 PM PDT 24
Peak memory 201976 kb
Host smart-a192161c-cdae-4896-9b7c-391c48360171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975145879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3975145879
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.762278302
Short name T451
Test name
Test status
Simulation time 7725075563 ps
CPU time 19.89 seconds
Started Aug 19 05:56:22 PM PDT 24
Finished Aug 19 05:56:42 PM PDT 24
Peak memory 201992 kb
Host smart-5c8f1b34-bdbb-45e1-9ad6-72cda09d804a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762278302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
762278302
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3309929268
Short name T609
Test name
Test status
Simulation time 2813820035 ps
CPU time 8.03 seconds
Started Aug 19 05:56:22 PM PDT 24
Finished Aug 19 05:56:31 PM PDT 24
Peak memory 210520 kb
Host smart-8bbad372-f461-40fe-b3a3-d8abf3a71576
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309929268 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3309929268
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.4251310833
Short name T52
Test name
Test status
Simulation time 471544714 ps
CPU time 0.98 seconds
Started Aug 19 05:54:44 PM PDT 24
Finished Aug 19 05:54:45 PM PDT 24
Peak memory 201996 kb
Host smart-04ec793f-f7ee-4ded-a6fd-9b11efef59d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251310833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.4251310833
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3593411869
Short name T181
Test name
Test status
Simulation time 323493528140 ps
CPU time 387.03 seconds
Started Aug 19 05:54:56 PM PDT 24
Finished Aug 19 06:01:23 PM PDT 24
Peak memory 202152 kb
Host smart-9f6973b1-960d-4a36-8aa7-0a31f2afb5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593411869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3593411869
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.326453272
Short name T650
Test name
Test status
Simulation time 495157205286 ps
CPU time 286.15 seconds
Started Aug 19 05:55:03 PM PDT 24
Finished Aug 19 05:59:50 PM PDT 24
Peak memory 202176 kb
Host smart-8994ad47-ec9e-49ef-83bd-3ea41fe1f129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326453272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.326453272
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1946900963
Short name T593
Test name
Test status
Simulation time 164549943984 ps
CPU time 54.07 seconds
Started Aug 19 05:54:53 PM PDT 24
Finished Aug 19 05:55:47 PM PDT 24
Peak memory 202140 kb
Host smart-ab2a0c04-885b-48aa-b8c5-c3819a841146
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946900963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1946900963
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3847678601
Short name T328
Test name
Test status
Simulation time 495475622399 ps
CPU time 1148.48 seconds
Started Aug 19 05:55:07 PM PDT 24
Finished Aug 19 06:14:20 PM PDT 24
Peak memory 202152 kb
Host smart-768a919d-ce23-4132-9432-305dfebd40b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847678601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3847678601
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2783175110
Short name T605
Test name
Test status
Simulation time 324951680539 ps
CPU time 105.65 seconds
Started Aug 19 05:54:53 PM PDT 24
Finished Aug 19 05:56:39 PM PDT 24
Peak memory 202152 kb
Host smart-070587d9-b4d9-4730-9b90-2a6e63c9612b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783175110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2783175110
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3110420856
Short name T155
Test name
Test status
Simulation time 709821247744 ps
CPU time 410.5 seconds
Started Aug 19 05:55:03 PM PDT 24
Finished Aug 19 06:01:54 PM PDT 24
Peak memory 202180 kb
Host smart-659ac913-5685-4f23-a7fb-cba4a3034a98
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110420856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3110420856
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1062206879
Short name T372
Test name
Test status
Simulation time 412523993841 ps
CPU time 996.38 seconds
Started Aug 19 05:55:06 PM PDT 24
Finished Aug 19 06:11:43 PM PDT 24
Peak memory 202144 kb
Host smart-bde66591-7318-499a-83cd-b4f4de3e1c73
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062206879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1062206879
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2767756619
Short name T191
Test name
Test status
Simulation time 123410415431 ps
CPU time 677.68 seconds
Started Aug 19 05:54:43 PM PDT 24
Finished Aug 19 06:06:01 PM PDT 24
Peak memory 202572 kb
Host smart-60416815-3aa0-498f-b8e7-add12a9752d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767756619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2767756619
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.650400567
Short name T707
Test name
Test status
Simulation time 22550691368 ps
CPU time 13.05 seconds
Started Aug 19 05:54:35 PM PDT 24
Finished Aug 19 05:54:48 PM PDT 24
Peak memory 202004 kb
Host smart-59ddd3c4-b9df-4e7b-a092-c2b61746bbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650400567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.650400567
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3458593703
Short name T118
Test name
Test status
Simulation time 4506991842 ps
CPU time 10.51 seconds
Started Aug 19 05:54:45 PM PDT 24
Finished Aug 19 05:54:55 PM PDT 24
Peak memory 201980 kb
Host smart-739ba853-bb8e-4cd0-8c28-dbc0c6eed166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458593703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3458593703
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3543748557
Short name T45
Test name
Test status
Simulation time 3885537058 ps
CPU time 10.2 seconds
Started Aug 19 05:54:36 PM PDT 24
Finished Aug 19 05:54:46 PM PDT 24
Peak memory 217380 kb
Host smart-567ee143-431a-485c-aec9-c94dc4cb35f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543748557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3543748557
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2296366737
Short name T380
Test name
Test status
Simulation time 5824469275 ps
CPU time 3.24 seconds
Started Aug 19 05:54:55 PM PDT 24
Finished Aug 19 05:54:59 PM PDT 24
Peak memory 201980 kb
Host smart-91ec474f-9684-4c2f-becf-214fba2f0565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296366737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2296366737
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2035339650
Short name T644
Test name
Test status
Simulation time 327000452655 ps
CPU time 713.67 seconds
Started Aug 19 05:54:56 PM PDT 24
Finished Aug 19 06:06:50 PM PDT 24
Peak memory 202152 kb
Host smart-57c4f75b-9009-4e2a-9912-fcf3f7027576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035339650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2035339650
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2030589089
Short name T701
Test name
Test status
Simulation time 6320282496 ps
CPU time 12.92 seconds
Started Aug 19 05:54:48 PM PDT 24
Finished Aug 19 05:55:01 PM PDT 24
Peak memory 210456 kb
Host smart-2941412a-5f8f-4744-ae89-1f6928583b9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030589089 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2030589089
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2133710432
Short name T785
Test name
Test status
Simulation time 411661872 ps
CPU time 1.09 seconds
Started Aug 19 05:56:23 PM PDT 24
Finished Aug 19 05:56:24 PM PDT 24
Peak memory 201996 kb
Host smart-adba01ee-98e0-464a-9ed6-7701fceffe88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133710432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2133710432
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.4125025801
Short name T254
Test name
Test status
Simulation time 330647008681 ps
CPU time 642.7 seconds
Started Aug 19 05:56:27 PM PDT 24
Finished Aug 19 06:07:10 PM PDT 24
Peak memory 202228 kb
Host smart-711b0720-7080-4b0a-ab8a-12288cd03b66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125025801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.4125025801
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3643370319
Short name T304
Test name
Test status
Simulation time 164129848671 ps
CPU time 105.71 seconds
Started Aug 19 05:56:25 PM PDT 24
Finished Aug 19 05:58:11 PM PDT 24
Peak memory 202144 kb
Host smart-c9ca0a34-d05b-4f84-abbf-7acd32bd1f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643370319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3643370319
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2685634428
Short name T84
Test name
Test status
Simulation time 326737239537 ps
CPU time 281.92 seconds
Started Aug 19 05:56:26 PM PDT 24
Finished Aug 19 06:01:08 PM PDT 24
Peak memory 202196 kb
Host smart-a73c9ed2-d8c8-4d96-bf4e-d0225dc06ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685634428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2685634428
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2280371694
Short name T634
Test name
Test status
Simulation time 337764456965 ps
CPU time 744.35 seconds
Started Aug 19 05:56:24 PM PDT 24
Finished Aug 19 06:08:48 PM PDT 24
Peak memory 202208 kb
Host smart-74ae7d6a-ad11-493e-a57f-108f77d79369
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280371694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2280371694
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3106761226
Short name T746
Test name
Test status
Simulation time 167399897297 ps
CPU time 410.21 seconds
Started Aug 19 05:56:23 PM PDT 24
Finished Aug 19 06:03:13 PM PDT 24
Peak memory 202172 kb
Host smart-4f646578-9956-433e-8507-7120467b0005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106761226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3106761226
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1357158354
Short name T649
Test name
Test status
Simulation time 157768912938 ps
CPU time 28.94 seconds
Started Aug 19 05:56:23 PM PDT 24
Finished Aug 19 05:56:52 PM PDT 24
Peak memory 202152 kb
Host smart-ac295141-b3ef-483a-bdbd-cad21485ee2d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357158354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1357158354
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.4124647968
Short name T298
Test name
Test status
Simulation time 531102818289 ps
CPU time 289.3 seconds
Started Aug 19 05:56:19 PM PDT 24
Finished Aug 19 06:01:08 PM PDT 24
Peak memory 202200 kb
Host smart-543758e4-bc7c-40d6-931f-e686984365a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124647968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.4124647968
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1435721707
Short name T719
Test name
Test status
Simulation time 207333603307 ps
CPU time 442.09 seconds
Started Aug 19 05:56:24 PM PDT 24
Finished Aug 19 06:03:46 PM PDT 24
Peak memory 202148 kb
Host smart-9f1a6070-0506-444b-956e-e09eaac76f99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435721707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1435721707
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2626311931
Short name T621
Test name
Test status
Simulation time 79561006032 ps
CPU time 257.15 seconds
Started Aug 19 05:56:22 PM PDT 24
Finished Aug 19 06:00:40 PM PDT 24
Peak memory 202396 kb
Host smart-872eb8da-d16c-4eb2-bfe9-a279cb40da08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626311931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2626311931
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2838184951
Short name T346
Test name
Test status
Simulation time 30639296866 ps
CPU time 28.4 seconds
Started Aug 19 05:56:23 PM PDT 24
Finished Aug 19 05:56:52 PM PDT 24
Peak memory 201968 kb
Host smart-35218e50-3b10-49ab-a559-0be77ef8f963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838184951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2838184951
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2662985482
Short name T663
Test name
Test status
Simulation time 4185914614 ps
CPU time 3.25 seconds
Started Aug 19 05:56:24 PM PDT 24
Finished Aug 19 05:56:28 PM PDT 24
Peak memory 200776 kb
Host smart-0f0989dd-bfeb-49ef-b1bd-e8402a8bbb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662985482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2662985482
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3190778026
Short name T493
Test name
Test status
Simulation time 5852180476 ps
CPU time 3.96 seconds
Started Aug 19 05:56:23 PM PDT 24
Finished Aug 19 05:56:27 PM PDT 24
Peak memory 201996 kb
Host smart-54ad9219-cd4f-40f1-8fac-fb6174d12d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190778026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3190778026
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3833957188
Short name T34
Test name
Test status
Simulation time 448522251948 ps
CPU time 407.62 seconds
Started Aug 19 05:56:22 PM PDT 24
Finished Aug 19 06:03:10 PM PDT 24
Peak memory 210628 kb
Host smart-d60efaef-ef29-47f9-987d-cb7c86c07043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833957188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3833957188
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2341726994
Short name T472
Test name
Test status
Simulation time 7565254904 ps
CPU time 5.31 seconds
Started Aug 19 05:56:27 PM PDT 24
Finished Aug 19 05:56:32 PM PDT 24
Peak memory 210460 kb
Host smart-dd268f69-c592-4515-8592-ab41a283379d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341726994 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2341726994
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.290588106
Short name T692
Test name
Test status
Simulation time 550671322 ps
CPU time 0.72 seconds
Started Aug 19 05:56:32 PM PDT 24
Finished Aug 19 05:56:33 PM PDT 24
Peak memory 201992 kb
Host smart-6c340b03-971a-4308-8a26-423b4e524739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290588106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.290588106
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3768917903
Short name T282
Test name
Test status
Simulation time 169629910593 ps
CPU time 345.18 seconds
Started Aug 19 05:56:21 PM PDT 24
Finished Aug 19 06:02:07 PM PDT 24
Peak memory 202216 kb
Host smart-d4eaf278-9248-47f7-937a-83ca9377d2ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768917903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3768917903
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1832865635
Short name T90
Test name
Test status
Simulation time 358219223295 ps
CPU time 186.62 seconds
Started Aug 19 05:56:25 PM PDT 24
Finished Aug 19 05:59:32 PM PDT 24
Peak memory 202152 kb
Host smart-6f156a9d-1cfe-4323-a61e-58f1a42aad00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832865635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1832865635
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2464967700
Short name T139
Test name
Test status
Simulation time 340749245348 ps
CPU time 566.8 seconds
Started Aug 19 05:56:32 PM PDT 24
Finished Aug 19 06:05:59 PM PDT 24
Peak memory 202188 kb
Host smart-af1d84e7-8910-4b9c-b19f-846538083551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464967700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2464967700
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.4191127954
Short name T656
Test name
Test status
Simulation time 327357005091 ps
CPU time 206.9 seconds
Started Aug 19 05:56:23 PM PDT 24
Finished Aug 19 05:59:50 PM PDT 24
Peak memory 202144 kb
Host smart-dd3b5f19-8169-4d87-8b3c-429d257427cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191127954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.4191127954
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.859602903
Short name T658
Test name
Test status
Simulation time 477985939623 ps
CPU time 1039.96 seconds
Started Aug 19 05:56:22 PM PDT 24
Finished Aug 19 06:13:42 PM PDT 24
Peak memory 202132 kb
Host smart-0769b078-04be-4326-a21b-64a293981330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859602903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.859602903
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3720176352
Short name T529
Test name
Test status
Simulation time 341603018262 ps
CPU time 373.19 seconds
Started Aug 19 05:56:23 PM PDT 24
Finished Aug 19 06:02:36 PM PDT 24
Peak memory 202140 kb
Host smart-c4337f43-0553-4d60-9be5-7f707cb6eb80
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720176352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3720176352
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1344503080
Short name T6
Test name
Test status
Simulation time 569076707224 ps
CPU time 341.01 seconds
Started Aug 19 05:56:25 PM PDT 24
Finished Aug 19 06:02:06 PM PDT 24
Peak memory 202164 kb
Host smart-4948cc0e-18c0-4e48-9468-a27cb2e2857c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344503080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1344503080
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1572197536
Short name T772
Test name
Test status
Simulation time 202433271910 ps
CPU time 457.66 seconds
Started Aug 19 05:56:25 PM PDT 24
Finished Aug 19 06:04:03 PM PDT 24
Peak memory 202148 kb
Host smart-9a3a68ed-bbef-4c19-a1fa-6d53045b1b05
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572197536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1572197536
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3391763680
Short name T631
Test name
Test status
Simulation time 114439674170 ps
CPU time 579.12 seconds
Started Aug 19 05:56:23 PM PDT 24
Finished Aug 19 06:06:03 PM PDT 24
Peak memory 202416 kb
Host smart-f3e62220-b13a-43e7-acf9-b323b42edd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391763680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3391763680
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3286775905
Short name T370
Test name
Test status
Simulation time 25994598945 ps
CPU time 15.18 seconds
Started Aug 19 05:56:22 PM PDT 24
Finished Aug 19 05:56:37 PM PDT 24
Peak memory 201992 kb
Host smart-9bf4850e-eb1e-4be0-9cc9-004375ffd68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286775905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3286775905
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2818031586
Short name T705
Test name
Test status
Simulation time 5332431275 ps
CPU time 2.19 seconds
Started Aug 19 05:56:25 PM PDT 24
Finished Aug 19 05:56:27 PM PDT 24
Peak memory 201976 kb
Host smart-553585d3-d29d-4748-8e51-72542d45ba4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818031586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2818031586
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.419912861
Short name T799
Test name
Test status
Simulation time 5913468170 ps
CPU time 16.11 seconds
Started Aug 19 05:56:25 PM PDT 24
Finished Aug 19 05:56:41 PM PDT 24
Peak memory 201996 kb
Host smart-af585449-6709-41bc-87e5-d22e2c468435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419912861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.419912861
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.886209400
Short name T87
Test name
Test status
Simulation time 167499151842 ps
CPU time 100.33 seconds
Started Aug 19 05:56:35 PM PDT 24
Finished Aug 19 05:58:15 PM PDT 24
Peak memory 202232 kb
Host smart-c90b89cb-64d5-4573-8238-d74d085e84d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886209400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
886209400
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.556614830
Short name T687
Test name
Test status
Simulation time 12089050202 ps
CPU time 15.62 seconds
Started Aug 19 05:56:31 PM PDT 24
Finished Aug 19 05:56:47 PM PDT 24
Peak memory 210496 kb
Host smart-c050a13c-8b68-4c8e-b86d-32631d0a6fdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556614830 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.556614830
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.695786935
Short name T389
Test name
Test status
Simulation time 508834929 ps
CPU time 0.87 seconds
Started Aug 19 05:56:38 PM PDT 24
Finished Aug 19 05:56:39 PM PDT 24
Peak memory 201992 kb
Host smart-ce4870a6-ad4b-4580-b068-a9a1da3f7556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695786935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.695786935
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.816495794
Short name T141
Test name
Test status
Simulation time 202343730889 ps
CPU time 39.98 seconds
Started Aug 19 05:56:33 PM PDT 24
Finished Aug 19 05:57:13 PM PDT 24
Peak memory 202172 kb
Host smart-abb2f446-1380-4dba-9417-5ef3d8cb1377
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816495794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati
ng.816495794
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1826374304
Short name T226
Test name
Test status
Simulation time 171861572865 ps
CPU time 365.99 seconds
Started Aug 19 05:56:34 PM PDT 24
Finished Aug 19 06:02:41 PM PDT 24
Peak memory 202216 kb
Host smart-a7f2aa4a-bba6-4c5b-89ea-0294f974a239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826374304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1826374304
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2182013302
Short name T321
Test name
Test status
Simulation time 164068695959 ps
CPU time 347.84 seconds
Started Aug 19 05:56:35 PM PDT 24
Finished Aug 19 06:02:23 PM PDT 24
Peak memory 202188 kb
Host smart-5a6110c6-fa5d-4227-86be-9d94c90a3232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182013302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2182013302
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1453767626
Short name T703
Test name
Test status
Simulation time 332003852944 ps
CPU time 411.75 seconds
Started Aug 19 05:56:35 PM PDT 24
Finished Aug 19 06:03:27 PM PDT 24
Peak memory 202160 kb
Host smart-68d9d785-272d-40bb-b433-e9f882f029e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453767626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1453767626
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.463911616
Short name T774
Test name
Test status
Simulation time 323522211185 ps
CPU time 384.74 seconds
Started Aug 19 05:56:35 PM PDT 24
Finished Aug 19 06:03:00 PM PDT 24
Peak memory 202148 kb
Host smart-21053e54-f915-42ff-984c-19469e95d6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463911616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.463911616
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.768240396
Short name T410
Test name
Test status
Simulation time 492917694636 ps
CPU time 290.16 seconds
Started Aug 19 05:56:35 PM PDT 24
Finished Aug 19 06:01:25 PM PDT 24
Peak memory 202100 kb
Host smart-7e6311ce-68fd-47f5-b7b2-689f8be251a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=768240396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.768240396
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1168112615
Short name T790
Test name
Test status
Simulation time 188530622980 ps
CPU time 413.79 seconds
Started Aug 19 05:56:34 PM PDT 24
Finished Aug 19 06:03:28 PM PDT 24
Peak memory 202144 kb
Host smart-7288d61d-f001-42d7-b97a-7c5a8acb900e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168112615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1168112615
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3461921409
Short name T202
Test name
Test status
Simulation time 103502945172 ps
CPU time 318.87 seconds
Started Aug 19 05:56:35 PM PDT 24
Finished Aug 19 06:01:54 PM PDT 24
Peak memory 202392 kb
Host smart-22c607b1-21c8-4daf-87da-5ca7b580d4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461921409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3461921409
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3442177133
Short name T379
Test name
Test status
Simulation time 38786339933 ps
CPU time 84.39 seconds
Started Aug 19 05:56:42 PM PDT 24
Finished Aug 19 05:58:06 PM PDT 24
Peak memory 201932 kb
Host smart-47f910df-1f21-4005-adef-282b93176572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442177133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3442177133
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.499619628
Short name T489
Test name
Test status
Simulation time 4924441886 ps
CPU time 3.78 seconds
Started Aug 19 05:56:36 PM PDT 24
Finished Aug 19 05:56:39 PM PDT 24
Peak memory 201988 kb
Host smart-2f4ec3ed-3d80-497f-9d81-f3dd93509ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499619628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.499619628
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2314836272
Short name T403
Test name
Test status
Simulation time 5756479695 ps
CPU time 7.18 seconds
Started Aug 19 05:56:35 PM PDT 24
Finished Aug 19 05:56:42 PM PDT 24
Peak memory 201968 kb
Host smart-0940a36a-2441-42a7-ac8f-eb3951266fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314836272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2314836272
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1568359442
Short name T16
Test name
Test status
Simulation time 28853488088 ps
CPU time 15.13 seconds
Started Aug 19 05:56:35 PM PDT 24
Finished Aug 19 05:56:50 PM PDT 24
Peak memory 210460 kb
Host smart-5f20a422-9f24-483a-a73a-b9fd5d82fecf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568359442 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1568359442
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.681761338
Short name T467
Test name
Test status
Simulation time 481237391 ps
CPU time 1.63 seconds
Started Aug 19 05:56:45 PM PDT 24
Finished Aug 19 05:56:47 PM PDT 24
Peak memory 202132 kb
Host smart-626c08f1-14c9-48de-9042-e08f87b8c2d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681761338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.681761338
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2574508852
Short name T691
Test name
Test status
Simulation time 332511341748 ps
CPU time 400.75 seconds
Started Aug 19 05:56:39 PM PDT 24
Finished Aug 19 06:03:19 PM PDT 24
Peak memory 202200 kb
Host smart-d042db45-4ecc-4d25-824a-4a9c4065929c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574508852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2574508852
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.422212431
Short name T147
Test name
Test status
Simulation time 497745878056 ps
CPU time 371.47 seconds
Started Aug 19 05:56:31 PM PDT 24
Finished Aug 19 06:02:43 PM PDT 24
Peak memory 202192 kb
Host smart-07632704-6096-4def-a591-18a692b1e35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422212431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.422212431
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2244592620
Short name T599
Test name
Test status
Simulation time 160797672850 ps
CPU time 198.48 seconds
Started Aug 19 05:56:36 PM PDT 24
Finished Aug 19 05:59:55 PM PDT 24
Peak memory 202164 kb
Host smart-97d1ff2d-94e3-42a8-8e40-8a3817040a45
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244592620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2244592620
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.388280696
Short name T171
Test name
Test status
Simulation time 159075936757 ps
CPU time 29.65 seconds
Started Aug 19 05:56:35 PM PDT 24
Finished Aug 19 05:57:04 PM PDT 24
Peak memory 202156 kb
Host smart-44344dcb-d1e2-4fa6-9277-27d4e9638309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388280696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.388280696
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3279037527
Short name T440
Test name
Test status
Simulation time 496828670277 ps
CPU time 248.48 seconds
Started Aug 19 05:56:34 PM PDT 24
Finished Aug 19 06:00:43 PM PDT 24
Peak memory 202112 kb
Host smart-4f181361-72b9-4ea2-a339-393828e1cabf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279037527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3279037527
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.26880123
Short name T788
Test name
Test status
Simulation time 557605618041 ps
CPU time 322.9 seconds
Started Aug 19 05:56:34 PM PDT 24
Finished Aug 19 06:01:57 PM PDT 24
Peak memory 202172 kb
Host smart-eadde6cd-fb5a-4e56-af7b-21c5f59cd342
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26880123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_w
akeup.26880123
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1899270145
Short name T436
Test name
Test status
Simulation time 607292605478 ps
CPU time 1074.2 seconds
Started Aug 19 05:56:35 PM PDT 24
Finished Aug 19 06:14:29 PM PDT 24
Peak memory 202284 kb
Host smart-6679a2bc-558a-4789-ad53-df83446270ab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899270145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1899270145
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.396694775
Short name T77
Test name
Test status
Simulation time 89611878329 ps
CPU time 369.81 seconds
Started Aug 19 05:56:45 PM PDT 24
Finished Aug 19 06:02:55 PM PDT 24
Peak memory 202440 kb
Host smart-9547db0e-0b24-4246-b239-eee8c6353475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396694775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.396694775
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.4273856895
Short name T488
Test name
Test status
Simulation time 44680700764 ps
CPU time 21.15 seconds
Started Aug 19 05:56:40 PM PDT 24
Finished Aug 19 05:57:01 PM PDT 24
Peak memory 202016 kb
Host smart-d6a25ab7-6ea5-4ae0-aed3-564fe336ccc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273856895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.4273856895
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2184152937
Short name T495
Test name
Test status
Simulation time 3745422540 ps
CPU time 9.9 seconds
Started Aug 19 05:56:34 PM PDT 24
Finished Aug 19 05:56:44 PM PDT 24
Peak memory 202004 kb
Host smart-c61cbcf4-4b66-4a21-a864-434d075f0ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184152937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2184152937
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1585270434
Short name T530
Test name
Test status
Simulation time 5555217955 ps
CPU time 7.28 seconds
Started Aug 19 05:56:34 PM PDT 24
Finished Aug 19 05:56:41 PM PDT 24
Peak memory 201972 kb
Host smart-6269c607-796b-464e-8c0d-d88294ea2646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585270434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1585270434
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1089339418
Short name T144
Test name
Test status
Simulation time 186016327686 ps
CPU time 116.2 seconds
Started Aug 19 05:56:43 PM PDT 24
Finished Aug 19 05:58:39 PM PDT 24
Peak memory 202172 kb
Host smart-2aa1abff-d8ec-4292-afe9-b8b6568b1255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089339418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1089339418
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2522307518
Short name T151
Test name
Test status
Simulation time 1623082901 ps
CPU time 4.69 seconds
Started Aug 19 05:56:46 PM PDT 24
Finished Aug 19 05:56:51 PM PDT 24
Peak memory 202028 kb
Host smart-28fb8965-64f6-4de3-bbfa-9265f27002af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522307518 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2522307518
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.578337479
Short name T365
Test name
Test status
Simulation time 494977472 ps
CPU time 1.12 seconds
Started Aug 19 05:56:41 PM PDT 24
Finished Aug 19 05:56:42 PM PDT 24
Peak memory 201952 kb
Host smart-f2b494a1-8eb6-42f6-9b8f-2e44b27ee5a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578337479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.578337479
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.353702292
Short name T257
Test name
Test status
Simulation time 492098519867 ps
CPU time 755.06 seconds
Started Aug 19 05:56:44 PM PDT 24
Finished Aug 19 06:09:19 PM PDT 24
Peak memory 202208 kb
Host smart-c6d73669-1b30-4da3-b9b7-02a6c441b4ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353702292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.353702292
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.620375951
Short name T697
Test name
Test status
Simulation time 387463946390 ps
CPU time 203.57 seconds
Started Aug 19 05:56:42 PM PDT 24
Finished Aug 19 06:00:05 PM PDT 24
Peak memory 202164 kb
Host smart-00af31ce-80df-4454-96d5-2aa0cf937c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620375951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.620375951
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.399583287
Short name T749
Test name
Test status
Simulation time 494082943889 ps
CPU time 71.28 seconds
Started Aug 19 05:56:46 PM PDT 24
Finished Aug 19 05:57:58 PM PDT 24
Peak memory 202160 kb
Host smart-254bd432-9e03-4fe5-9a9e-bd951598751d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=399583287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.399583287
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3115324195
Short name T253
Test name
Test status
Simulation time 496633997102 ps
CPU time 195.8 seconds
Started Aug 19 05:56:40 PM PDT 24
Finished Aug 19 05:59:56 PM PDT 24
Peak memory 202144 kb
Host smart-327c6337-f3e1-40fc-99b5-7589e4dbe31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115324195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3115324195
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3579534397
Short name T512
Test name
Test status
Simulation time 328527260593 ps
CPU time 173.86 seconds
Started Aug 19 05:56:45 PM PDT 24
Finished Aug 19 05:59:39 PM PDT 24
Peak memory 202284 kb
Host smart-48628fc4-c7e0-4cdc-91f1-54eae8e4e62f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579534397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3579534397
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.4214299785
Short name T308
Test name
Test status
Simulation time 376601784690 ps
CPU time 237.93 seconds
Started Aug 19 05:56:43 PM PDT 24
Finished Aug 19 06:00:41 PM PDT 24
Peak memory 202192 kb
Host smart-15f043bf-cf1c-4f3c-8bce-7dea3cb51d41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214299785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.4214299785
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1471112021
Short name T617
Test name
Test status
Simulation time 200987066832 ps
CPU time 210.12 seconds
Started Aug 19 05:56:45 PM PDT 24
Finished Aug 19 06:00:16 PM PDT 24
Peak memory 202112 kb
Host smart-c2057041-bb04-4f81-bd7e-55b70c3b1fec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471112021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1471112021
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.671261651
Short name T32
Test name
Test status
Simulation time 78918523426 ps
CPU time 416 seconds
Started Aug 19 05:57:22 PM PDT 24
Finished Aug 19 06:04:18 PM PDT 24
Peak memory 202404 kb
Host smart-701597a3-4144-41d0-9944-34f7d7ef73b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671261651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.671261651
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.846585908
Short name T435
Test name
Test status
Simulation time 28427681890 ps
CPU time 65.95 seconds
Started Aug 19 05:56:42 PM PDT 24
Finished Aug 19 05:57:48 PM PDT 24
Peak memory 202008 kb
Host smart-f30e4e4f-bfd6-4fac-80bc-6e263e3dce74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846585908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.846585908
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1288251127
Short name T396
Test name
Test status
Simulation time 3098905961 ps
CPU time 2.43 seconds
Started Aug 19 05:56:44 PM PDT 24
Finished Aug 19 05:56:47 PM PDT 24
Peak memory 201972 kb
Host smart-0f1eb97b-60ad-478a-a5ec-72029234a88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288251127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1288251127
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3747131791
Short name T655
Test name
Test status
Simulation time 5847187873 ps
CPU time 13.89 seconds
Started Aug 19 05:56:46 PM PDT 24
Finished Aug 19 05:57:00 PM PDT 24
Peak memory 201988 kb
Host smart-4f01d782-bbe2-4810-949a-5e096acc0a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747131791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3747131791
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2964527569
Short name T519
Test name
Test status
Simulation time 24370561853 ps
CPU time 4.18 seconds
Started Aug 19 05:56:45 PM PDT 24
Finished Aug 19 05:56:49 PM PDT 24
Peak memory 202004 kb
Host smart-5e986433-d3da-41f8-8537-de1b4daaee66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964527569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2964527569
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3171374213
Short name T745
Test name
Test status
Simulation time 325729380 ps
CPU time 0.98 seconds
Started Aug 19 05:56:57 PM PDT 24
Finished Aug 19 05:56:58 PM PDT 24
Peak memory 201956 kb
Host smart-db194d01-208e-43a5-93c3-f42532f95c22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171374213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3171374213
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2984230736
Short name T633
Test name
Test status
Simulation time 484730654779 ps
CPU time 268.18 seconds
Started Aug 19 05:56:52 PM PDT 24
Finished Aug 19 06:01:21 PM PDT 24
Peak memory 202184 kb
Host smart-bc5011dc-cbd1-46ab-8d2e-f3fdde9b5f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984230736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2984230736
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3307995897
Short name T319
Test name
Test status
Simulation time 326819698391 ps
CPU time 182.96 seconds
Started Aug 19 05:56:43 PM PDT 24
Finished Aug 19 05:59:46 PM PDT 24
Peak memory 202188 kb
Host smart-858276d9-e5dc-48b5-b76e-b62c3cefd90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307995897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3307995897
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2174634794
Short name T145
Test name
Test status
Simulation time 495763229155 ps
CPU time 183.48 seconds
Started Aug 19 05:56:42 PM PDT 24
Finished Aug 19 05:59:46 PM PDT 24
Peak memory 202136 kb
Host smart-d2a82e4a-e45c-43be-bc97-708ed03c65e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174634794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2174634794
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2937787234
Short name T177
Test name
Test status
Simulation time 156516378365 ps
CPU time 350.01 seconds
Started Aug 19 05:56:42 PM PDT 24
Finished Aug 19 06:02:32 PM PDT 24
Peak memory 202140 kb
Host smart-335459a3-a56c-4345-8a8d-1e5a57854b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937787234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2937787234
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1829005190
Short name T748
Test name
Test status
Simulation time 494749493864 ps
CPU time 125.93 seconds
Started Aug 19 05:56:46 PM PDT 24
Finished Aug 19 05:58:52 PM PDT 24
Peak memory 202116 kb
Host smart-a7b4fb8c-c2f3-4542-8533-9cc969afab03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829005190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1829005190
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3846074358
Short name T309
Test name
Test status
Simulation time 167258224397 ps
CPU time 85.09 seconds
Started Aug 19 05:56:45 PM PDT 24
Finished Aug 19 05:58:10 PM PDT 24
Peak memory 202168 kb
Host smart-f1bf6a16-4e13-4aea-89b9-f7826fe203b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846074358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3846074358
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2428823825
Short name T395
Test name
Test status
Simulation time 589068563994 ps
CPU time 951.07 seconds
Started Aug 19 05:56:46 PM PDT 24
Finished Aug 19 06:12:37 PM PDT 24
Peak memory 202144 kb
Host smart-510d1695-c0f7-40c4-b8dc-608b964c4f91
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428823825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2428823825
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3626305343
Short name T195
Test name
Test status
Simulation time 111802949826 ps
CPU time 614.68 seconds
Started Aug 19 05:56:57 PM PDT 24
Finished Aug 19 06:07:12 PM PDT 24
Peak memory 202468 kb
Host smart-56f395ac-d89b-45ce-bf0e-d15567a76f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626305343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3626305343
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.675347910
Short name T91
Test name
Test status
Simulation time 34916295931 ps
CPU time 36.26 seconds
Started Aug 19 05:56:52 PM PDT 24
Finished Aug 19 05:57:28 PM PDT 24
Peak memory 201972 kb
Host smart-3a1005ff-4b5c-4281-85c0-301360607459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675347910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.675347910
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.495040399
Short name T486
Test name
Test status
Simulation time 5401713507 ps
CPU time 2.21 seconds
Started Aug 19 05:56:56 PM PDT 24
Finished Aug 19 05:56:58 PM PDT 24
Peak memory 201972 kb
Host smart-bbaba16d-f5fe-4014-9787-4ed87717b881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495040399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.495040399
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1368521207
Short name T452
Test name
Test status
Simulation time 5945174634 ps
CPU time 12.81 seconds
Started Aug 19 05:56:44 PM PDT 24
Finished Aug 19 05:56:57 PM PDT 24
Peak memory 201988 kb
Host smart-8ca2ea97-38a0-4876-920e-42463bda672b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368521207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1368521207
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2915835995
Short name T622
Test name
Test status
Simulation time 32040644039 ps
CPU time 7.5 seconds
Started Aug 19 05:56:57 PM PDT 24
Finished Aug 19 05:57:04 PM PDT 24
Peak memory 202300 kb
Host smart-7429b43d-16bd-49e8-abf4-f26f79b2aa27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915835995 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2915835995
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.4276719095
Short name T504
Test name
Test status
Simulation time 526242768 ps
CPU time 1 seconds
Started Aug 19 05:57:01 PM PDT 24
Finished Aug 19 05:57:02 PM PDT 24
Peak memory 201992 kb
Host smart-d539779b-7fb1-4e6d-99f4-13220c81a6d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276719095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.4276719095
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1040998270
Short name T157
Test name
Test status
Simulation time 166629833185 ps
CPU time 38.67 seconds
Started Aug 19 05:56:52 PM PDT 24
Finished Aug 19 05:57:31 PM PDT 24
Peak memory 202184 kb
Host smart-5bf05e92-15ad-45c0-9faf-c925564ee2c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040998270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1040998270
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.12123037
Short name T638
Test name
Test status
Simulation time 529453556831 ps
CPU time 596.39 seconds
Started Aug 19 05:56:50 PM PDT 24
Finished Aug 19 06:06:47 PM PDT 24
Peak memory 202208 kb
Host smart-02ff46d3-126f-4530-bf8a-e7b33b16ec73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12123037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.12123037
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3232354566
Short name T262
Test name
Test status
Simulation time 493140243729 ps
CPU time 310.36 seconds
Started Aug 19 05:56:56 PM PDT 24
Finished Aug 19 06:02:07 PM PDT 24
Peak memory 202204 kb
Host smart-1244c67c-54ba-4ba7-a7c9-3568af220b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232354566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3232354566
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.327531025
Short name T700
Test name
Test status
Simulation time 168015588907 ps
CPU time 380.21 seconds
Started Aug 19 05:56:52 PM PDT 24
Finished Aug 19 06:03:12 PM PDT 24
Peak memory 202164 kb
Host smart-9721a44d-c66b-47d5-9379-a5410e863f3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=327531025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.327531025
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1373590797
Short name T276
Test name
Test status
Simulation time 163347825424 ps
CPU time 62.66 seconds
Started Aug 19 05:56:57 PM PDT 24
Finished Aug 19 05:57:59 PM PDT 24
Peak memory 202116 kb
Host smart-47590b19-95d9-4297-abb6-b7f53fe79056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373590797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1373590797
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1132859645
Short name T397
Test name
Test status
Simulation time 491924948602 ps
CPU time 295.22 seconds
Started Aug 19 05:56:51 PM PDT 24
Finished Aug 19 06:01:47 PM PDT 24
Peak memory 202156 kb
Host smart-ef05b876-8b7e-4afd-8bb8-b073d7b315c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132859645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1132859645
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2707782013
Short name T582
Test name
Test status
Simulation time 593465714139 ps
CPU time 315.54 seconds
Started Aug 19 05:56:52 PM PDT 24
Finished Aug 19 06:02:07 PM PDT 24
Peak memory 202132 kb
Host smart-56b05063-f040-4242-b3e1-bf46f3cacfb6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707782013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2707782013
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3059905291
Short name T601
Test name
Test status
Simulation time 123904417154 ps
CPU time 422.91 seconds
Started Aug 19 05:56:52 PM PDT 24
Finished Aug 19 06:03:55 PM PDT 24
Peak memory 202388 kb
Host smart-dff7a921-7f23-4f3f-9361-68c5c330e40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059905291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3059905291
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3863942274
Short name T375
Test name
Test status
Simulation time 37977456497 ps
CPU time 91.09 seconds
Started Aug 19 05:56:57 PM PDT 24
Finished Aug 19 05:58:28 PM PDT 24
Peak memory 201960 kb
Host smart-446fee43-cd24-4f4d-bc53-164793590e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863942274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3863942274
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3963115670
Short name T463
Test name
Test status
Simulation time 4648192743 ps
CPU time 3.17 seconds
Started Aug 19 05:56:52 PM PDT 24
Finished Aug 19 05:56:55 PM PDT 24
Peak memory 201960 kb
Host smart-c90f012e-5198-43b4-8802-01a8240284b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963115670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3963115670
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2968654067
Short name T579
Test name
Test status
Simulation time 5906850778 ps
CPU time 4.48 seconds
Started Aug 19 05:56:57 PM PDT 24
Finished Aug 19 05:57:01 PM PDT 24
Peak memory 201972 kb
Host smart-ec39eb28-3c69-4013-91d4-5a71f6bcff6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968654067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2968654067
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1864936624
Short name T731
Test name
Test status
Simulation time 514910033170 ps
CPU time 617.86 seconds
Started Aug 19 05:57:01 PM PDT 24
Finished Aug 19 06:07:19 PM PDT 24
Peak memory 202160 kb
Host smart-5b211b82-829d-42e8-8c13-dc969962ba90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864936624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1864936624
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2357927506
Short name T19
Test name
Test status
Simulation time 9843784847 ps
CPU time 11.7 seconds
Started Aug 19 05:57:01 PM PDT 24
Finished Aug 19 05:57:13 PM PDT 24
Peak memory 210564 kb
Host smart-3cdaf2b0-a82f-42a6-97b7-120816b9969a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357927506 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2357927506
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2713789534
Short name T672
Test name
Test status
Simulation time 377515146 ps
CPU time 1.4 seconds
Started Aug 19 05:57:11 PM PDT 24
Finished Aug 19 05:57:12 PM PDT 24
Peak memory 201996 kb
Host smart-4c705ec9-275c-4c32-9ca7-04b2f2d4156f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713789534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2713789534
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2476041319
Short name T330
Test name
Test status
Simulation time 327891562560 ps
CPU time 725.78 seconds
Started Aug 19 05:57:02 PM PDT 24
Finished Aug 19 06:09:08 PM PDT 24
Peak memory 202156 kb
Host smart-0ae0b68b-b4c4-4227-a18e-161095c5422a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476041319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2476041319
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2078765632
Short name T666
Test name
Test status
Simulation time 165748516345 ps
CPU time 105.59 seconds
Started Aug 19 05:57:00 PM PDT 24
Finished Aug 19 05:58:46 PM PDT 24
Peak memory 202140 kb
Host smart-131c2943-da1f-4c10-8d4c-f12c1c37064a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078765632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2078765632
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3966106264
Short name T459
Test name
Test status
Simulation time 165954016873 ps
CPU time 98.14 seconds
Started Aug 19 05:56:59 PM PDT 24
Finished Aug 19 05:58:38 PM PDT 24
Peak memory 202116 kb
Host smart-36897d74-149a-438a-8fd6-b6243aba6a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966106264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3966106264
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2584478430
Short name T159
Test name
Test status
Simulation time 165245632161 ps
CPU time 204.36 seconds
Started Aug 19 05:57:41 PM PDT 24
Finished Aug 19 06:01:06 PM PDT 24
Peak memory 202184 kb
Host smart-d90c5e08-ffec-4475-bf2f-d272a46a8e77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584478430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2584478430
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3834998726
Short name T291
Test name
Test status
Simulation time 485945552578 ps
CPU time 1151.6 seconds
Started Aug 19 05:57:01 PM PDT 24
Finished Aug 19 06:16:13 PM PDT 24
Peak memory 202144 kb
Host smart-8885df31-bf16-4a36-a423-39282dcbbddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834998726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3834998726
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.342561935
Short name T777
Test name
Test status
Simulation time 332449568728 ps
CPU time 184.71 seconds
Started Aug 19 05:57:04 PM PDT 24
Finished Aug 19 06:00:09 PM PDT 24
Peak memory 202128 kb
Host smart-868695d5-fb89-4207-a106-78d662ca3309
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=342561935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.342561935
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.4006196413
Short name T221
Test name
Test status
Simulation time 190635934160 ps
CPU time 455.58 seconds
Started Aug 19 05:57:00 PM PDT 24
Finished Aug 19 06:04:36 PM PDT 24
Peak memory 202216 kb
Host smart-8b9d65cb-fa9e-40ca-ae72-50a1eb9cd10b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006196413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.4006196413
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3579131514
Short name T381
Test name
Test status
Simulation time 395444522665 ps
CPU time 954.89 seconds
Started Aug 19 05:57:01 PM PDT 24
Finished Aug 19 06:12:56 PM PDT 24
Peak memory 202164 kb
Host smart-9b223095-f154-483a-8a71-b8308c7592b3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579131514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3579131514
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.372579487
Short name T623
Test name
Test status
Simulation time 23548069879 ps
CPU time 54.59 seconds
Started Aug 19 05:57:01 PM PDT 24
Finished Aug 19 05:57:56 PM PDT 24
Peak memory 202004 kb
Host smart-978eb051-2921-4372-9e79-205a70994a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372579487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.372579487
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3313833239
Short name T794
Test name
Test status
Simulation time 4773517009 ps
CPU time 3.86 seconds
Started Aug 19 05:57:01 PM PDT 24
Finished Aug 19 05:57:05 PM PDT 24
Peak memory 201976 kb
Host smart-483a7550-c006-44c0-ab8a-5b9cf4c59510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313833239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3313833239
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3373511157
Short name T351
Test name
Test status
Simulation time 5876705469 ps
CPU time 8.01 seconds
Started Aug 19 05:57:01 PM PDT 24
Finished Aug 19 05:57:09 PM PDT 24
Peak memory 201968 kb
Host smart-bca969d8-f65b-45df-8f07-5a06558cccb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373511157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3373511157
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3187651265
Short name T311
Test name
Test status
Simulation time 375155572384 ps
CPU time 792.99 seconds
Started Aug 19 05:57:01 PM PDT 24
Finished Aug 19 06:10:14 PM PDT 24
Peak memory 202148 kb
Host smart-7fc52e61-0654-4d85-85ca-23a57581f635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187651265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3187651265
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2114895961
Short name T702
Test name
Test status
Simulation time 71253206028 ps
CPU time 13.37 seconds
Started Aug 19 05:57:01 PM PDT 24
Finished Aug 19 05:57:14 PM PDT 24
Peak memory 210712 kb
Host smart-420fd864-4245-4789-ae19-789d3c11ca40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114895961 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2114895961
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.594533665
Short name T628
Test name
Test status
Simulation time 350323399 ps
CPU time 0.74 seconds
Started Aug 19 05:57:13 PM PDT 24
Finished Aug 19 05:57:14 PM PDT 24
Peak memory 201968 kb
Host smart-30beb3cb-c154-4662-b371-c1c1a3dbcc30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594533665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.594533665
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3030601535
Short name T306
Test name
Test status
Simulation time 507849658613 ps
CPU time 1224.68 seconds
Started Aug 19 05:57:11 PM PDT 24
Finished Aug 19 06:17:36 PM PDT 24
Peak memory 202152 kb
Host smart-d3c1f085-d70d-493f-8241-0792b4d436ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030601535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3030601535
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3930400420
Short name T237
Test name
Test status
Simulation time 513660613346 ps
CPU time 597.69 seconds
Started Aug 19 05:57:12 PM PDT 24
Finished Aug 19 06:07:10 PM PDT 24
Peak memory 202172 kb
Host smart-e5388c71-76f3-43da-a4e3-a8bc357a5889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930400420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3930400420
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1544432281
Short name T293
Test name
Test status
Simulation time 485604109489 ps
CPU time 90.98 seconds
Started Aug 19 05:57:12 PM PDT 24
Finished Aug 19 05:58:44 PM PDT 24
Peak memory 202172 kb
Host smart-9935bca2-1b41-43eb-8419-b94f51e3da95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544432281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1544432281
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3661205105
Short name T490
Test name
Test status
Simulation time 486526956636 ps
CPU time 160.5 seconds
Started Aug 19 05:57:11 PM PDT 24
Finished Aug 19 05:59:52 PM PDT 24
Peak memory 202108 kb
Host smart-f9a7e849-707e-4a26-a4f8-8f1620813644
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661205105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3661205105
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1839465604
Short name T509
Test name
Test status
Simulation time 487317040331 ps
CPU time 652.28 seconds
Started Aug 19 05:57:11 PM PDT 24
Finished Aug 19 06:08:03 PM PDT 24
Peak memory 202212 kb
Host smart-2c27bd5f-1957-412f-ba56-c95e4ebb31e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839465604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1839465604
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1523628
Short name T307
Test name
Test status
Simulation time 176752747137 ps
CPU time 419.34 seconds
Started Aug 19 05:57:13 PM PDT 24
Finished Aug 19 06:04:12 PM PDT 24
Peak memory 202172 kb
Host smart-816c23e4-1211-48bc-a848-9327790a84da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wa
keup.1523628
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.96500572
Short name T643
Test name
Test status
Simulation time 623855425846 ps
CPU time 670.09 seconds
Started Aug 19 05:57:11 PM PDT 24
Finished Aug 19 06:08:22 PM PDT 24
Peak memory 202156 kb
Host smart-71bef80a-2ce4-4c1b-90db-c8e8b67f739d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96500572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.a
dc_ctrl_filters_wakeup_fixed.96500572
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.4275376958
Short name T192
Test name
Test status
Simulation time 138305655008 ps
CPU time 488.02 seconds
Started Aug 19 05:57:11 PM PDT 24
Finished Aug 19 06:05:19 PM PDT 24
Peak memory 202376 kb
Host smart-25d1f1b2-f9da-4c17-bc34-96fd2641ab78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275376958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.4275376958
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.212010154
Short name T740
Test name
Test status
Simulation time 43181338544 ps
CPU time 27.04 seconds
Started Aug 19 05:57:11 PM PDT 24
Finished Aug 19 05:57:38 PM PDT 24
Peak memory 201984 kb
Host smart-61422005-bf72-4915-b300-e90fe62f943b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212010154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.212010154
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.234993870
Short name T359
Test name
Test status
Simulation time 4714621794 ps
CPU time 6.26 seconds
Started Aug 19 05:57:10 PM PDT 24
Finished Aug 19 05:57:16 PM PDT 24
Peak memory 201984 kb
Host smart-1dff1caa-a349-4094-b41d-0d080d57c768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234993870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.234993870
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3973464505
Short name T356
Test name
Test status
Simulation time 5724072640 ps
CPU time 13.88 seconds
Started Aug 19 05:57:12 PM PDT 24
Finished Aug 19 05:57:26 PM PDT 24
Peak memory 201972 kb
Host smart-54a0ea32-ad75-4c34-9661-88cfd45af41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973464505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3973464505
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.744943649
Short name T17
Test name
Test status
Simulation time 2713994610 ps
CPU time 9.83 seconds
Started Aug 19 05:57:11 PM PDT 24
Finished Aug 19 05:57:21 PM PDT 24
Peak memory 210564 kb
Host smart-b8382ec7-1934-49de-849f-6bfc6246f251
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744943649 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.744943649
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3554936448
Short name T678
Test name
Test status
Simulation time 330397041 ps
CPU time 0.83 seconds
Started Aug 19 05:57:21 PM PDT 24
Finished Aug 19 05:57:22 PM PDT 24
Peak memory 202004 kb
Host smart-2e5c49f8-d16a-4e33-aa34-d9a5c3c71d21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554936448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3554936448
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3638038142
Short name T231
Test name
Test status
Simulation time 351504031400 ps
CPU time 122.3 seconds
Started Aug 19 05:57:22 PM PDT 24
Finished Aug 19 05:59:24 PM PDT 24
Peak memory 202212 kb
Host smart-56ed1635-c065-4ad6-90b4-115e65c747a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638038142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3638038142
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3244941532
Short name T272
Test name
Test status
Simulation time 507476877023 ps
CPU time 1125.48 seconds
Started Aug 19 05:57:23 PM PDT 24
Finished Aug 19 06:16:09 PM PDT 24
Peak memory 202216 kb
Host smart-35bb5f2b-f873-497c-b77c-962f852d6724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244941532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3244941532
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.4207669594
Short name T557
Test name
Test status
Simulation time 326616483509 ps
CPU time 178.52 seconds
Started Aug 19 05:57:18 PM PDT 24
Finished Aug 19 06:00:17 PM PDT 24
Peak memory 202124 kb
Host smart-e2bb72b5-4e88-440b-97d8-15251b3b63cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207669594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.4207669594
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1905461167
Short name T624
Test name
Test status
Simulation time 323332467101 ps
CPU time 738.21 seconds
Started Aug 19 05:57:11 PM PDT 24
Finished Aug 19 06:09:29 PM PDT 24
Peak memory 202156 kb
Host smart-88d1b7a2-b8df-44a5-8761-781ec21de853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905461167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1905461167
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2879440139
Short name T778
Test name
Test status
Simulation time 162124145527 ps
CPU time 101.48 seconds
Started Aug 19 05:57:10 PM PDT 24
Finished Aug 19 05:58:52 PM PDT 24
Peak memory 202152 kb
Host smart-52e9bf35-f6e7-463e-975e-ee7a57c4b7b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879440139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2879440139
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2413407557
Short name T739
Test name
Test status
Simulation time 622125583535 ps
CPU time 1344.18 seconds
Started Aug 19 05:57:21 PM PDT 24
Finished Aug 19 06:19:46 PM PDT 24
Peak memory 202132 kb
Host smart-870dfc23-f296-4a1a-ae98-d6ed4c7db926
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413407557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2413407557
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3220515513
Short name T612
Test name
Test status
Simulation time 95170875297 ps
CPU time 524.45 seconds
Started Aug 19 05:57:20 PM PDT 24
Finished Aug 19 06:06:04 PM PDT 24
Peak memory 202432 kb
Host smart-56d6f863-cbbc-480e-8efe-478c2af901d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220515513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3220515513
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2977601547
Short name T415
Test name
Test status
Simulation time 38897995305 ps
CPU time 45.36 seconds
Started Aug 19 05:57:22 PM PDT 24
Finished Aug 19 05:58:07 PM PDT 24
Peak memory 201976 kb
Host smart-4f85d93d-3611-477e-a1be-5876743521c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977601547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2977601547
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.910040162
Short name T421
Test name
Test status
Simulation time 3336180358 ps
CPU time 1.64 seconds
Started Aug 19 05:57:24 PM PDT 24
Finished Aug 19 05:57:25 PM PDT 24
Peak memory 201944 kb
Host smart-dc99bb2e-b42a-4449-b0b1-0b452b0cb3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910040162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.910040162
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1039930711
Short name T522
Test name
Test status
Simulation time 5644940448 ps
CPU time 7.67 seconds
Started Aug 19 05:57:12 PM PDT 24
Finished Aug 19 05:57:19 PM PDT 24
Peak memory 201956 kb
Host smart-3d963bcd-5ad8-44c3-a8fb-b5655114c2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039930711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1039930711
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1617439874
Short name T174
Test name
Test status
Simulation time 710061939805 ps
CPU time 839.28 seconds
Started Aug 19 05:57:21 PM PDT 24
Finished Aug 19 06:11:21 PM PDT 24
Peak memory 202156 kb
Host smart-6f9350ee-02f3-4daf-b41c-7290f7f2dc4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617439874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1617439874
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2728062016
Short name T637
Test name
Test status
Simulation time 2131212045 ps
CPU time 8.72 seconds
Started Aug 19 05:57:21 PM PDT 24
Finished Aug 19 05:57:30 PM PDT 24
Peak memory 202028 kb
Host smart-a9836193-c500-47f4-8414-a14289e8f779
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728062016 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2728062016
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1340076027
Short name T590
Test name
Test status
Simulation time 338449956 ps
CPU time 0.85 seconds
Started Aug 19 05:54:45 PM PDT 24
Finished Aug 19 05:54:46 PM PDT 24
Peak memory 202140 kb
Host smart-f1c84adc-d51c-4552-8286-93681d4701c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340076027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1340076027
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.416382859
Short name T585
Test name
Test status
Simulation time 183740461891 ps
CPU time 196.97 seconds
Started Aug 19 05:55:03 PM PDT 24
Finished Aug 19 05:58:20 PM PDT 24
Peak memory 202164 kb
Host smart-73c8e00e-3da2-4ece-a41d-07e7bd14df29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416382859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.416382859
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1248705792
Short name T730
Test name
Test status
Simulation time 162997849634 ps
CPU time 104.33 seconds
Started Aug 19 05:54:53 PM PDT 24
Finished Aug 19 05:56:38 PM PDT 24
Peak memory 202152 kb
Host smart-c7b95231-98b4-4fa4-8186-f6cc515919de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248705792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1248705792
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1708375714
Short name T652
Test name
Test status
Simulation time 169161570439 ps
CPU time 107.11 seconds
Started Aug 19 05:55:02 PM PDT 24
Finished Aug 19 05:56:50 PM PDT 24
Peak memory 202132 kb
Host smart-ea075771-8a6c-436b-ac73-350ee6d43376
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708375714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1708375714
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2489566746
Short name T425
Test name
Test status
Simulation time 328583374967 ps
CPU time 280.55 seconds
Started Aug 19 05:55:01 PM PDT 24
Finished Aug 19 05:59:41 PM PDT 24
Peak memory 202128 kb
Host smart-81e081f2-819f-42eb-a404-9ffdfe66762f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489566746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2489566746
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2804797323
Short name T533
Test name
Test status
Simulation time 336549762274 ps
CPU time 203.12 seconds
Started Aug 19 05:55:05 PM PDT 24
Finished Aug 19 05:58:28 PM PDT 24
Peak memory 202124 kb
Host smart-f5adf522-4c2e-4d60-8241-0614e721e788
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804797323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2804797323
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.712265209
Short name T316
Test name
Test status
Simulation time 368493745072 ps
CPU time 867.4 seconds
Started Aug 19 05:55:03 PM PDT 24
Finished Aug 19 06:09:30 PM PDT 24
Peak memory 202156 kb
Host smart-ed2610fe-4066-4ae8-ab2b-a1ba74d6a73b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712265209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.712265209
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.237731015
Short name T88
Test name
Test status
Simulation time 391583259910 ps
CPU time 609.62 seconds
Started Aug 19 05:54:53 PM PDT 24
Finished Aug 19 06:05:03 PM PDT 24
Peak memory 202156 kb
Host smart-9482a015-770d-4b7f-9cfb-5976276a7603
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237731015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.237731015
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2172876511
Short name T197
Test name
Test status
Simulation time 110216865200 ps
CPU time 478.67 seconds
Started Aug 19 05:54:56 PM PDT 24
Finished Aug 19 06:02:54 PM PDT 24
Peak memory 202392 kb
Host smart-fe8725ca-adc5-41c3-b8e0-efa39ae163d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172876511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2172876511
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.52538049
Short name T639
Test name
Test status
Simulation time 34862961458 ps
CPU time 73.41 seconds
Started Aug 19 05:55:06 PM PDT 24
Finished Aug 19 05:56:20 PM PDT 24
Peak memory 201944 kb
Host smart-8d40a4a8-fa43-4c5d-9209-4310a9ee7cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52538049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.52538049
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1727668992
Short name T732
Test name
Test status
Simulation time 4250686985 ps
CPU time 11.52 seconds
Started Aug 19 05:54:57 PM PDT 24
Finished Aug 19 05:55:09 PM PDT 24
Peak memory 201972 kb
Host smart-2ca89ab1-ebea-45cd-83b8-d53da1c2f4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727668992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1727668992
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1787227564
Short name T786
Test name
Test status
Simulation time 5679421838 ps
CPU time 7.12 seconds
Started Aug 19 05:55:13 PM PDT 24
Finished Aug 19 05:55:20 PM PDT 24
Peak memory 201952 kb
Host smart-bffb2749-bd03-416d-8356-bb1f2080cb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787227564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1787227564
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.50541739
Short name T600
Test name
Test status
Simulation time 7031727629 ps
CPU time 9.44 seconds
Started Aug 19 05:54:47 PM PDT 24
Finished Aug 19 05:54:57 PM PDT 24
Peak memory 201972 kb
Host smart-27ab5e5a-2e40-4e17-a069-4c117a15d883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50541739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.50541739
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.745581725
Short name T735
Test name
Test status
Simulation time 469539418 ps
CPU time 1.16 seconds
Started Aug 19 05:55:05 PM PDT 24
Finished Aug 19 05:55:07 PM PDT 24
Peak memory 202008 kb
Host smart-d929539e-389a-41df-9694-904277a79ae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745581725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.745581725
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3273597943
Short name T648
Test name
Test status
Simulation time 172338125713 ps
CPU time 51.26 seconds
Started Aug 19 05:55:12 PM PDT 24
Finished Aug 19 05:56:04 PM PDT 24
Peak memory 202248 kb
Host smart-e290cb1f-15da-4264-bc4c-13b9aaff041c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273597943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3273597943
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.149510738
Short name T447
Test name
Test status
Simulation time 161087955819 ps
CPU time 174.82 seconds
Started Aug 19 05:55:07 PM PDT 24
Finished Aug 19 05:58:02 PM PDT 24
Peak memory 202192 kb
Host smart-6f98147a-0daa-498e-8a4d-8f9147091f03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=149510738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.149510738
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2830202219
Short name T233
Test name
Test status
Simulation time 162277276490 ps
CPU time 89.31 seconds
Started Aug 19 05:54:54 PM PDT 24
Finished Aug 19 05:56:23 PM PDT 24
Peak memory 202160 kb
Host smart-3dc201d4-65bb-4f64-b4c4-810aada856be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830202219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2830202219
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3887554978
Short name T352
Test name
Test status
Simulation time 487338952793 ps
CPU time 1198.02 seconds
Started Aug 19 05:54:49 PM PDT 24
Finished Aug 19 06:14:47 PM PDT 24
Peak memory 202124 kb
Host smart-7e92c7d4-fa73-43d7-b23c-a1c830e2b160
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887554978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3887554978
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.808848618
Short name T205
Test name
Test status
Simulation time 170134968255 ps
CPU time 407.36 seconds
Started Aug 19 05:55:06 PM PDT 24
Finished Aug 19 06:01:54 PM PDT 24
Peak memory 202196 kb
Host smart-e2a836dd-8c1a-4ee7-adff-555d855d5d1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808848618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.808848618
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4040618597
Short name T85
Test name
Test status
Simulation time 200148773330 ps
CPU time 490.25 seconds
Started Aug 19 05:55:05 PM PDT 24
Finished Aug 19 06:03:15 PM PDT 24
Peak memory 202148 kb
Host smart-be10aa70-df87-4218-a6bb-998091d3b92c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040618597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.4040618597
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.4174890261
Short name T712
Test name
Test status
Simulation time 95701038136 ps
CPU time 502.24 seconds
Started Aug 19 05:55:17 PM PDT 24
Finished Aug 19 06:03:39 PM PDT 24
Peak memory 202416 kb
Host smart-76e97538-3607-4043-b27e-3d375da20872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174890261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.4174890261
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.238420370
Short name T402
Test name
Test status
Simulation time 28560323992 ps
CPU time 35.01 seconds
Started Aug 19 05:55:09 PM PDT 24
Finished Aug 19 05:55:44 PM PDT 24
Peak memory 201980 kb
Host smart-4c8a3932-4a29-4c8e-8b9b-06b71fd1df2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238420370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.238420370
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1097566441
Short name T763
Test name
Test status
Simulation time 3383716238 ps
CPU time 2.36 seconds
Started Aug 19 05:55:15 PM PDT 24
Finished Aug 19 05:55:18 PM PDT 24
Peak memory 201956 kb
Host smart-02ed4a87-fbea-4c04-b3b7-7d720465ca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097566441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1097566441
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1006795821
Short name T75
Test name
Test status
Simulation time 6163710461 ps
CPU time 3.95 seconds
Started Aug 19 05:54:55 PM PDT 24
Finished Aug 19 05:54:59 PM PDT 24
Peak memory 201976 kb
Host smart-2bf6e088-f542-46b4-93c8-ef8338504075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006795821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1006795821
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3127748378
Short name T288
Test name
Test status
Simulation time 506424255252 ps
CPU time 710.77 seconds
Started Aug 19 05:55:06 PM PDT 24
Finished Aug 19 06:06:57 PM PDT 24
Peak memory 202180 kb
Host smart-9f8d910f-1fa3-40cf-906d-df093d4716cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127748378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3127748378
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3311858943
Short name T428
Test name
Test status
Simulation time 1835871852 ps
CPU time 5.06 seconds
Started Aug 19 05:55:06 PM PDT 24
Finished Aug 19 05:55:11 PM PDT 24
Peak memory 202016 kb
Host smart-e713a328-492c-43b3-8944-3903fbbb5e49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311858943 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3311858943
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.281512600
Short name T371
Test name
Test status
Simulation time 508830605 ps
CPU time 0.93 seconds
Started Aug 19 05:55:13 PM PDT 24
Finished Aug 19 05:55:15 PM PDT 24
Peak memory 201980 kb
Host smart-1eecdbec-bd08-4c8b-85ca-d72ac26a93c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281512600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.281512600
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1634038286
Short name T324
Test name
Test status
Simulation time 299237564963 ps
CPU time 549.83 seconds
Started Aug 19 05:55:07 PM PDT 24
Finished Aug 19 06:04:17 PM PDT 24
Peak memory 202156 kb
Host smart-15c38e00-2caf-4bc1-bc39-7b2670b19503
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634038286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1634038286
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2866931333
Short name T8
Test name
Test status
Simulation time 164360787234 ps
CPU time 68 seconds
Started Aug 19 05:55:17 PM PDT 24
Finished Aug 19 05:56:25 PM PDT 24
Peak memory 202148 kb
Host smart-4199ed4d-82c9-47e3-8108-fcb803c155be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866931333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2866931333
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3525950382
Short name T654
Test name
Test status
Simulation time 168660088377 ps
CPU time 107.01 seconds
Started Aug 19 05:55:00 PM PDT 24
Finished Aug 19 05:56:47 PM PDT 24
Peak memory 202140 kb
Host smart-dfbb9c58-de11-4950-8360-0b7fdc24352b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525950382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3525950382
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.4217157798
Short name T122
Test name
Test status
Simulation time 324598227289 ps
CPU time 774.54 seconds
Started Aug 19 05:55:05 PM PDT 24
Finished Aug 19 06:08:00 PM PDT 24
Peak memory 202148 kb
Host smart-cea79317-ae68-4f84-9535-c7557e403da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217157798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.4217157798
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2567010645
Short name T180
Test name
Test status
Simulation time 162025272355 ps
CPU time 181.16 seconds
Started Aug 19 05:54:58 PM PDT 24
Finished Aug 19 05:57:59 PM PDT 24
Peak memory 202116 kb
Host smart-c2ee7aaa-3bbb-4ff9-9aa8-4718aabaf0f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567010645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2567010645
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2865963099
Short name T179
Test name
Test status
Simulation time 192648313944 ps
CPU time 108.97 seconds
Started Aug 19 05:55:07 PM PDT 24
Finished Aug 19 05:56:56 PM PDT 24
Peak memory 202176 kb
Host smart-c921c363-54bd-4b69-ac2c-7ee64b9da7c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865963099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2865963099
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2178193327
Short name T386
Test name
Test status
Simulation time 603069460213 ps
CPU time 1435.17 seconds
Started Aug 19 05:55:08 PM PDT 24
Finished Aug 19 06:19:03 PM PDT 24
Peak memory 202156 kb
Host smart-b3098245-649d-412c-989b-6a79c45c4e64
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178193327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2178193327
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.911399921
Short name T434
Test name
Test status
Simulation time 28682486725 ps
CPU time 17.5 seconds
Started Aug 19 05:55:02 PM PDT 24
Finished Aug 19 05:55:19 PM PDT 24
Peak memory 202004 kb
Host smart-5f1bd942-f2f0-4b67-ae27-fb426a6cebb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911399921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.911399921
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.4124427900
Short name T364
Test name
Test status
Simulation time 3297050924 ps
CPU time 2.82 seconds
Started Aug 19 05:55:07 PM PDT 24
Finished Aug 19 05:55:09 PM PDT 24
Peak memory 201924 kb
Host smart-15238e08-7e73-47de-86d1-0f544b339d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124427900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.4124427900
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.678816505
Short name T619
Test name
Test status
Simulation time 5771545934 ps
CPU time 4.29 seconds
Started Aug 19 05:55:08 PM PDT 24
Finished Aug 19 05:55:12 PM PDT 24
Peak memory 202000 kb
Host smart-83bf2f4b-c32f-4ebf-9b47-6a8ddc89de83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678816505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.678816505
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1646902215
Short name T610
Test name
Test status
Simulation time 413572272056 ps
CPU time 1342.06 seconds
Started Aug 19 05:55:06 PM PDT 24
Finished Aug 19 06:17:29 PM PDT 24
Peak memory 210576 kb
Host smart-8946cd64-0d95-4d4b-bf30-18c8decc4bda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646902215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1646902215
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3733055470
Short name T492
Test name
Test status
Simulation time 354215071 ps
CPU time 1.14 seconds
Started Aug 19 05:55:11 PM PDT 24
Finished Aug 19 05:55:13 PM PDT 24
Peak memory 201988 kb
Host smart-1a5e7336-0ede-4fe4-8810-e9459f54ff87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733055470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3733055470
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.364169374
Short name T750
Test name
Test status
Simulation time 344422345798 ps
CPU time 141.88 seconds
Started Aug 19 05:55:10 PM PDT 24
Finished Aug 19 05:57:32 PM PDT 24
Peak memory 202184 kb
Host smart-8fa019b4-f310-4d3c-9dc4-4e2e16613c23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364169374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.364169374
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3747432794
Short name T242
Test name
Test status
Simulation time 561981095232 ps
CPU time 168.61 seconds
Started Aug 19 05:55:10 PM PDT 24
Finished Aug 19 05:57:59 PM PDT 24
Peak memory 202204 kb
Host smart-a939c75a-ece1-43ad-9dcf-917bd666e6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747432794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3747432794
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.14585022
Short name T318
Test name
Test status
Simulation time 495590084562 ps
CPU time 576.86 seconds
Started Aug 19 05:55:12 PM PDT 24
Finished Aug 19 06:04:49 PM PDT 24
Peak memory 202168 kb
Host smart-73c0b84f-0859-4cdc-8f4d-e674380c01ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14585022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.14585022
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3476011245
Short name T134
Test name
Test status
Simulation time 320634963063 ps
CPU time 171.64 seconds
Started Aug 19 05:55:07 PM PDT 24
Finished Aug 19 05:57:58 PM PDT 24
Peak memory 202140 kb
Host smart-9099c0c1-8d86-457c-83d3-2d47d57406e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476011245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3476011245
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.955165130
Short name T146
Test name
Test status
Simulation time 326060546775 ps
CPU time 340.66 seconds
Started Aug 19 05:54:55 PM PDT 24
Finished Aug 19 06:00:36 PM PDT 24
Peak memory 202152 kb
Host smart-9cd2b30e-dc66-483d-9988-b89749b175f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955165130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.955165130
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.145923826
Short name T551
Test name
Test status
Simulation time 160593862643 ps
CPU time 95.2 seconds
Started Aug 19 05:55:07 PM PDT 24
Finished Aug 19 05:56:43 PM PDT 24
Peak memory 202140 kb
Host smart-157a63d7-eb03-49d2-ba5a-2424f2e940d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=145923826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.145923826
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1641395207
Short name T284
Test name
Test status
Simulation time 532220602680 ps
CPU time 611.42 seconds
Started Aug 19 05:55:12 PM PDT 24
Finished Aug 19 06:05:23 PM PDT 24
Peak memory 202128 kb
Host smart-9e8c8d72-f7b4-46e9-94aa-bdece556ed0b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641395207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1641395207
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.6542555
Short name T759
Test name
Test status
Simulation time 579815412655 ps
CPU time 1212.68 seconds
Started Aug 19 05:54:59 PM PDT 24
Finished Aug 19 06:15:12 PM PDT 24
Peak memory 202172 kb
Host smart-21526318-3219-4f53-879d-11605b0ba922
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6542555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc
_ctrl_filters_wakeup_fixed.6542555
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.664820303
Short name T199
Test name
Test status
Simulation time 92454252137 ps
CPU time 460.84 seconds
Started Aug 19 05:55:05 PM PDT 24
Finished Aug 19 06:02:46 PM PDT 24
Peak memory 202412 kb
Host smart-2a3508a2-656d-40d3-b430-92bb8a0fbfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664820303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.664820303
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2904779471
Short name T441
Test name
Test status
Simulation time 46706895012 ps
CPU time 109.65 seconds
Started Aug 19 05:55:06 PM PDT 24
Finished Aug 19 05:56:56 PM PDT 24
Peak memory 202028 kb
Host smart-ec41382c-1fc5-4a20-b2ad-cf43648195bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904779471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2904779471
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.4094777318
Short name T618
Test name
Test status
Simulation time 4179831193 ps
CPU time 5.2 seconds
Started Aug 19 05:55:15 PM PDT 24
Finished Aug 19 05:55:21 PM PDT 24
Peak memory 201976 kb
Host smart-17c4d9c8-f33d-4d24-ae83-337dd8379537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094777318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.4094777318
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3927875978
Short name T419
Test name
Test status
Simulation time 5929542222 ps
CPU time 14.5 seconds
Started Aug 19 05:55:04 PM PDT 24
Finished Aug 19 05:55:19 PM PDT 24
Peak memory 201992 kb
Host smart-cea429f0-21a3-498f-a292-aa4c0b3308e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927875978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3927875978
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3051981090
Short name T388
Test name
Test status
Simulation time 35826194800 ps
CPU time 85.8 seconds
Started Aug 19 05:55:07 PM PDT 24
Finished Aug 19 05:56:32 PM PDT 24
Peak memory 201956 kb
Host smart-820af185-bfdc-4e28-b016-d8fcf9a1c52a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051981090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3051981090
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3497564097
Short name T539
Test name
Test status
Simulation time 2362711782 ps
CPU time 3.75 seconds
Started Aug 19 05:55:31 PM PDT 24
Finished Aug 19 05:55:35 PM PDT 24
Peak memory 202116 kb
Host smart-22f86ecb-3b87-421e-b252-06fb8345b5ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497564097 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3497564097
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3915283892
Short name T753
Test name
Test status
Simulation time 342991029 ps
CPU time 1.48 seconds
Started Aug 19 05:55:13 PM PDT 24
Finished Aug 19 05:55:14 PM PDT 24
Peak memory 201984 kb
Host smart-f5fe4f03-e146-454e-9792-031391a67df5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915283892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3915283892
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1943828516
Short name T568
Test name
Test status
Simulation time 162205351991 ps
CPU time 393.56 seconds
Started Aug 19 05:55:08 PM PDT 24
Finished Aug 19 06:01:42 PM PDT 24
Peak memory 202172 kb
Host smart-edd305e3-f549-4183-ae98-0b927b22a48c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943828516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1943828516
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3640283753
Short name T222
Test name
Test status
Simulation time 164037674464 ps
CPU time 370.01 seconds
Started Aug 19 05:55:02 PM PDT 24
Finished Aug 19 06:01:12 PM PDT 24
Peak memory 202156 kb
Host smart-22c889ed-5a78-4f84-a681-1a6bbb965547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640283753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3640283753
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.915069933
Short name T429
Test name
Test status
Simulation time 330910090274 ps
CPU time 424.43 seconds
Started Aug 19 05:55:11 PM PDT 24
Finished Aug 19 06:02:16 PM PDT 24
Peak memory 202336 kb
Host smart-0bc2f8aa-d1e3-41cc-bf06-082ac46a7ade
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=915069933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.915069933
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1650432576
Short name T259
Test name
Test status
Simulation time 326879822922 ps
CPU time 745.62 seconds
Started Aug 19 05:55:06 PM PDT 24
Finished Aug 19 06:07:32 PM PDT 24
Peak memory 202136 kb
Host smart-ce6b3286-af14-4510-854a-f5f181d5e0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650432576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1650432576
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2898402346
Short name T602
Test name
Test status
Simulation time 498414143386 ps
CPU time 1140.39 seconds
Started Aug 19 05:54:58 PM PDT 24
Finished Aug 19 06:13:59 PM PDT 24
Peak memory 202100 kb
Host smart-5e885a7e-909b-4c9e-ac26-4f48a30b0eed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898402346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2898402346
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1319073466
Short name T281
Test name
Test status
Simulation time 408990853891 ps
CPU time 195.2 seconds
Started Aug 19 05:55:04 PM PDT 24
Finished Aug 19 05:58:19 PM PDT 24
Peak memory 202160 kb
Host smart-a661fc65-9873-4550-91f4-0e7f2a9f6900
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319073466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1319073466
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2796876504
Short name T768
Test name
Test status
Simulation time 125060980598 ps
CPU time 441.37 seconds
Started Aug 19 05:55:09 PM PDT 24
Finished Aug 19 06:02:30 PM PDT 24
Peak memory 202404 kb
Host smart-a9759e74-cc3a-48ba-affe-a9bebb4674a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796876504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2796876504
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3890840926
Short name T742
Test name
Test status
Simulation time 25089807191 ps
CPU time 4.38 seconds
Started Aug 19 05:55:07 PM PDT 24
Finished Aug 19 05:55:11 PM PDT 24
Peak memory 201976 kb
Host smart-4eeb4ab1-9aae-4a4f-92eb-98c907ca4e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890840926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3890840926
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1066019780
Short name T554
Test name
Test status
Simulation time 3286749137 ps
CPU time 4.73 seconds
Started Aug 19 05:55:05 PM PDT 24
Finished Aug 19 05:55:10 PM PDT 24
Peak memory 201976 kb
Host smart-2f17ce11-75d5-4f1e-aac4-9436b597f318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066019780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1066019780
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.71484679
Short name T376
Test name
Test status
Simulation time 5701754567 ps
CPU time 3.93 seconds
Started Aug 19 05:54:58 PM PDT 24
Finished Aug 19 05:55:02 PM PDT 24
Peak memory 202000 kb
Host smart-58b92b6c-78c7-4575-8f40-40fcef0ef277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71484679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.71484679
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3793449669
Short name T744
Test name
Test status
Simulation time 95610258403 ps
CPU time 399.56 seconds
Started Aug 19 05:55:05 PM PDT 24
Finished Aug 19 06:01:45 PM PDT 24
Peak memory 202392 kb
Host smart-e4c9a8dc-2c48-4e8a-a2f8-7486536c18ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793449669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3793449669
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3316297375
Short name T683
Test name
Test status
Simulation time 256864725648 ps
CPU time 8.1 seconds
Started Aug 19 05:55:08 PM PDT 24
Finished Aug 19 05:55:16 PM PDT 24
Peak memory 202280 kb
Host smart-a40d2f21-643b-45f2-9e14-572fb18972ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316297375 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3316297375
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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