Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5513	1			T3	20		T4	7		T6	14
testmodes[AdcCtrlTestmodeNormal]	4324	1			T4	7		T5	1		T6	6
testmodes[AdcCtrlTestmodeLowpower]	4836	1			T5	1		T11	16		T12	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2878	1			T3	19		T4	3		T6	9
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1404	1			T4	3		T6	4		T7	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1112	1			T13	1		T26	1		T14	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1354	1			T4	4		T6	4		T7	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1491	1			T4	3		T6	2		T7	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1146	1			T12	1		T14	1		T55	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1154	1			T26	1		T14	2		T57	14
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1093	1			T5	1		T12	1		T13	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2342	1			T11	15		T12	2		T26	17