Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22619

1

T3

20

T4

14

T5

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

16690

1

T3

20

T4

14

T5

1

auto[ADC_CTRL_FILTER_COND_OUT]

5929

1

T5

1

T14

5

T16

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16750

1

T3

20

T4

14

T5

2

auto[1]

5869

1

T12

5

T13

6

T15

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18774

1

T3

20

T4

14

T5

2

auto[1]

3845

1

T13

2

T14

1

T18

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2	1			T196	1		T218	1		-	-
values[1]	640	1			T19	13		T41	15		T79	11
values[2]	583	1			T159	24		T139	12		T161	5
values[3]	691	1			T15	4		T41	14		T138	9
values[4]	711	1			T5	1		T12	5		T55	20
values[5]	534	1			T68	13		T140	1		T151	12
values[6]	742	1			T17	12		T21	8		T54	7
values[7]	635	1			T13	6		T14	5		T55	26
values[8]	645	1			T137	1		T219	1		T141	9
values[9]	3617	1			T16	1		T31	1		T18	19
minimum	13819	1			T3	20		T4	14		T5	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	838	1			T19	13		T159	24		T79	11
values[1]	2762	1			T16	1		T18	19		T41	15
values[2]	743	1			T12	5		T41	14		T150	10
values[3]	674	1			T5	1		T15	4		T55	20
values[4]	639	1			T17	12		T68	22		T136	27
values[5]	700	1			T14	5		T21	8		T54	7
values[6]	723	1			T13	6		T135	27		T50	3
values[7]	571	1			T137	1		T219	1		T69	36
values[8]	969	1			T20	10		T137	1		T148	11
values[9]	178	1			T31	1		T144	20		T220	20
minimum	13822	1			T3	20		T4	14		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

4101

1

T12

1

T13

2

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T19	13		T159	14		T79	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T161	3		T221	14		T185	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T153	1		T222	1		T194	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1631	1			T16	1		T18	2		T41	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	5		T150	1		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T41	14		T69	2		T153	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T15	4		T154	1		T223	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T5	1		T55	12		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T68	12		T153	1		T34	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T17	12		T136	15		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T21	8		T49	3		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	4		T54	4		T55	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	4		T135	12		T50	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T141	9		T151	10		T160	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T137	1		T219	1		T225	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T69	16		T184	1		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T137	1		T148	1		T68	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T20	1		T52	2		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T31	1		T144	1		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T144	11		T220	11		T227	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13720	1			T3	20		T4	14		T5	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T159	10		T79	10		T143	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T161	2		T221	14		T185	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T153	1		T194	17		T228	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	958	1			T18	17		T229	14		T139	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T150	9		T160	2		T221	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T69	1		T153	10		T33	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T154	1		T223	12		T230	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T55	8		T199	8		T151	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T68	10		T153	1		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T136	12		T151	12		T178	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T49	1		T180	17		T187	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T14	1		T54	3		T55	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	2		T135	15		T168	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T160	8		T231	1		T156	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T225	16		T194	14		T168	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T69	20		T189	13		T232	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T148	10		T51	1		T225	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T20	9		T52	1		T144	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T144	1		T190	10		T233	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T144	7		T220	9		T227	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T78	1		T79	1		T217	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	9	39	81.25	9

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum , values[0]]	*	--	--	4

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T196	1		T218	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T19	13		T79	1		T234	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T41	15		T221	14		T185	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T159	14		T32	1		T163	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T139	1		T161	3		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T15	4		T221	2		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T41	14		T138	9		T69	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T12	5		T150	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	1		T55	12		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T68	5		T153	1		T34	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T140	1		T151	3		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T21	8		T49	3		T68	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T17	12		T54	4		T136	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	4		T135	12		T50	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	4		T55	15		T151	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T137	1		T219	1		T225	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T141	9		T69	16		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T31	1		T137	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1832	1			T16	1		T18	2		T20	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13719	1			T3	20		T4	14		T5	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T79	10		T143	9		T153	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T221	14		T185	9		T154	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T159	10		T235	2		T191	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T139	11		T161	2		T145	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T221	7		T194	17		T236	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T69	1		T153	10		T33	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T150	9		T160	2		T154	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T55	8		T199	8		T181	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T68	8		T153	1		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T151	9		T156	11		T237	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T49	1		T68	2		T187	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T54	3		T136	12		T151	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	2		T135	15		T180	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	1		T55	11		T160	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T225	16		T194	14		T168	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T69	20		T189	13		T156	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T148	10		T51	1		T144	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1153	1			T18	17		T20	9		T229	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T19	1		T159	11		T79	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T161	3		T221	15		T185	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T153	2		T222	1		T194	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1289	1			T16	1		T18	19		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	4		T150	10		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T41	1		T69	2		T153	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	4		T154	2		T223	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T5	1		T55	9		T199	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T68	12		T153	2		T34	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T17	1		T136	13		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T21	1		T49	3		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	4		T54	4		T55	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	4		T135	17		T50	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T141	1		T151	1		T160	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T137	1		T219	1		T225	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T69	21		T184	1		T189	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T137	1		T148	11		T68	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T20	10		T52	2		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T31	1		T144	2		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T144	8		T220	10		T227	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13822	1			T3	20		T4	14		T5	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T19	12		T159	13		T234	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T161	2		T221	13		T188	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T194	15		T235	2		T191	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1300	1			T41	14		T88	20		T138	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	1		T160	3		T221	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T41	13		T69	1		T153	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T223	12		T238	8		T239	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T55	11		T151	2		T240	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T68	10		T34	1		T241	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T17	11		T136	14		T151	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T21	7		T49	1		T141	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	1		T54	3		T55	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T13	2		T135	10		T50	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T141	8		T151	9		T160	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T194	12		T242	3		T171	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T69	15		T243	8		T244	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T68	5		T51	1		T245	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T52	1		T144	10		T171	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T246	8		T233	8		T247	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T144	10		T220	10		T248	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	10	38	79.17	10

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum , values[0]]	*	--	--	4
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T196	1		T218	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T19	1		T79	11		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T41	1		T221	15		T185	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T159	11		T32	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T139	12		T161	3		T145	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	4		T221	8		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T41	1		T138	1		T69	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	4		T150	10		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T5	1		T55	9		T199	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T68	9		T153	2		T34	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T140	1		T151	10		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T21	1		T49	3		T68	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T17	1		T54	4		T136	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	4		T135	17		T50	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	4		T55	12		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T137	1		T219	1		T225	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T141	1		T69	21		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	387	1			T31	1		T137	1		T148	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1518	1			T16	1		T18	19		T20	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13819	1			T3	20		T4	14		T5	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T19	12		T234	9		T143	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T41	14		T221	13		T154	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T159	13		T163	13		T249	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T161	2		T163	14		T250	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T221	1		T251	9		T194	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T41	13		T138	8		T69	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T12	1		T160	3		T238	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T55	11		T240	12		T245	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T68	4		T34	1		T223	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T151	2		T237	21		T252	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T21	7		T49	1		T68	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T17	11		T54	3		T136	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T13	2		T135	10		T50	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	1		T55	14		T151	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T194	12		T245	10		T242	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T141	8		T69	15		T253	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T68	5		T51	1		T238	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1467	1			T88	20		T254	14		T197	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

auto[0]

4101

1

T12

1

T13

2

T14

1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22619

1

T3

20

T4

14

T5

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19124

1

T3

20

T4

14

T5

2

auto[ADC_CTRL_FILTER_COND_OUT]

3495

1

T15

4

T17

12

T19

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16755

1

T3

20

T4

14

T5

2

auto[1]

5864

1

T12

5

T15

4

T16

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18774

1

T3

20

T4

14

T5

2

auto[1]

3845

1

T13

2

T14

1

T18

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	7	1			T95	7		-	-		-	-
values[0]	50	1			T255	1		T40	1		T256	10
values[1]	571	1			T51	4		T199	9		T151	12
values[2]	613	1			T12	5		T41	14		T224	1
values[3]	650	1			T41	15		T69	36		T52	3
values[4]	662	1			T54	7		T135	20		T68	9
values[5]	560	1			T17	12		T55	20		T137	1
values[6]	761	1			T13	6		T15	4		T138	9
values[7]	724	1			T5	1		T14	5		T31	1
values[8]	2992	1			T16	1		T18	19		T88	22
values[9]	1210	1			T19	13		T20	10		T21	8
minimum	13819	1			T3	20		T4	14		T5	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	753	1			T12	5		T51	4		T199	9
values[1]	698	1			T41	14		T224	1		T139	12
values[2]	664	1			T41	15		T54	7		T135	20
values[3]	534	1			T50	3		T219	1		T152	17
values[4]	597	1			T17	12		T55	20		T137	1
values[5]	685	1			T15	4		T31	1		T138	9
values[6]	3141	1			T5	1		T13	6		T14	5
values[7]	689	1			T150	10		T151	10		T161	5
values[8]	879	1			T19	13		T20	10		T21	8
values[9]	160	1			T140	1		T160	6		T225	8
minimum	13819	1			T3	20		T4	14		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

4101

1

T12

1

T13

2

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	5		T51	3		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T199	1		T151	3		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T41	14		T224	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T184	1		T33	7		T251	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T68	7		T69	16		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T41	15		T54	4		T135	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T50	3		T219	1		T152	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T245	12		T257	11		T171	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T137	1		T221	2		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T17	12		T55	12		T151	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T31	1		T138	9		T68	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T15	4		T69	2		T221	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1717	1			T5	1		T13	4		T14	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T79	1		T219	1		T143	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T32	1		T184	1		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T150	1		T151	10		T161	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T20	1		T21	8		T55	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T19	13		T148	1		T144	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T160	4		T231	1		T258	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T140	1		T225	1		T168	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13719	1			T3	20		T4	14		T5	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T51	1		T154	1		T227	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T199	8		T151	9		T145	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T139	11		T172	23		T259	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T33	3		T186	13		T168	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T68	2		T69	20		T242	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T54	3		T135	9		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T153	1		T194	14		T230	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T245	15		T260	7		T261	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T221	7		T189	4		T262	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T55	8		T151	12		T160	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T68	8		T162	9		T189	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T69	1		T221	14		T153	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T13	2		T14	1		T18	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T79	10		T143	9		T144	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T236	2		T195	7		T263	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T150	9		T161	2		T194	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T20	9		T55	11		T135	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T148	10		T144	15		T34	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T160	2		T231	1		T98	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T225	7		T168	8		T245	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4