Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22619

1

T3

20

T4

14

T5

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19190

1

T3

20

T4

14

T5

2

auto[ADC_CTRL_FILTER_COND_OUT]

3429

1

T13

6

T17

12

T19

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16799

1

T3

20

T4

14

T5

1

auto[1]

5820

1

T5

1

T12

5

T15

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18774

1

T3

20

T4

14

T5

2

auto[1]

3845

1

T13

2

T14

1

T18

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T234	10		T248	17		-	-
values[0]	59	1			T165	1		T326	28		T291	7
values[1]	660	1			T19	13		T55	20		T137	1
values[2]	2993	1			T14	5		T16	1		T18	19
values[3]	777	1			T12	5		T17	12		T20	10
values[4]	594	1			T68	9		T161	5		T142	1
values[5]	560	1			T13	6		T54	7		T55	26
values[6]	479	1			T5	1		T50	3		T68	6
values[7]	677	1			T135	7		T68	13		T224	1
values[8]	759	1			T21	8		T41	14		T135	20
values[9]	1215	1			T15	4		T31	1		T159	24
minimum	13819	1			T3	20		T4	14		T5	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	800	1			T19	13		T41	15		T55	20
values[1]	3100	1			T12	5		T14	5		T16	1
values[2]	644	1			T137	1		T150	10		T136	27
values[3]	545	1			T17	12		T68	9		T161	5
values[4]	617	1			T13	6		T54	7		T221	9
values[5]	546	1			T5	1		T55	26		T135	7
values[6]	714	1			T21	8		T135	20		T68	13
values[7]	772	1			T41	14		T159	24		T219	1
values[8]	803	1			T15	4		T31	1		T199	9
values[9]	231	1			T234	10		T152	17		T178	11
minimum	13847	1			T3	20		T4	14		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

4101

1

T12

1

T13

2

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T55	12		T49	3		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T19	13		T41	15		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1649	1			T12	5		T14	4		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T140	1		T141	9		T69	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T137	1		T150	1		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T136	15		T180	17		T286	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T68	7		T142	1		T181	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	12		T161	3		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T54	4		T221	2		T143	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	4		T153	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	1		T55	15		T50	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T135	1		T187	17		T251	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T21	8		T151	19		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T135	11		T68	5		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T41	14		T141	10		T151	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T159	14		T219	1		T154	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T15	4		T31	1		T221	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T199	1		T184	1		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T234	10		T178	5		T163	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T152	17		T225	1		T236	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13719	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T326	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T55	8		T49	1		T148	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T52	1		T144	7		T186	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T14	1		T18	17		T20	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T69	20		T189	13		T220	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T150	9		T162	9		T288	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T136	12		T180	17		T263	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T68	2		T181	1		T154	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T161	2		T225	7		T231	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T54	3		T221	7		T143	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	2		T153	1		T144	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T55	11		T151	9		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T135	6		T187	17		T232	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T151	12		T240	1		T168	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T135	9		T68	8		T153	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T160	10		T144	14		T145	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T159	10		T154	14		T230	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T221	14		T154	1		T223	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T199	8		T225	9		T189	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T178	6		T289	1		T167	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T225	7		T236	1		T261	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T326	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T234	10		T248	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T165	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T326	17		T291	4		T175	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T55	12		T49	3		T178	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T19	13		T137	1		T144	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1666	1			T14	4		T16	1		T18	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T41	15		T140	1		T141	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	5		T20	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T17	12		T136	15		T180	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T68	7		T142	1		T181	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T161	3		T184	1		T286	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T54	4		T55	15		T151	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	4		T153	1		T185	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	1		T50	3		T68	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T144	1		T251	12		T162	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T224	1		T151	19		T240	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T135	1		T68	5		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T21	8		T41	14		T160	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T135	11		T219	1		T185	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T15	4		T31	1		T141	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	396	1			T159	14		T199	1		T152	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13719	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T248	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T326	11		T291	3		T175	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T55	8		T49	1		T178	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T144	7		T186	13		T194	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T14	1		T18	17		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T69	20		T52	1		T189	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T20	9		T150	9		T51	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T136	12		T180	17		T220	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T68	2		T181	1		T154	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T161	2		T241	12		T292	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T54	3		T55	11		T151	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	2		T153	1		T185	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T143	9		T317	11		T327	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T144	1		T162	13		T223	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T151	12		T240	1		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T135	6		T68	8		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T160	8		T144	14		T145	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T135	9		T154	14		T225	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T160	2		T221	14		T178	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T159	10		T199	8		T225	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T55	9		T49	3		T148	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T19	1		T41	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T12	4		T14	4		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T140	1		T141	1		T69	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T137	1		T150	10		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T136	13		T180	18		T286	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T68	3		T142	1		T181	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T17	1		T161	3		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T54	4		T221	8		T143	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	4		T153	2		T144	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	1		T55	12		T50	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T135	7		T187	18		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T21	1		T151	13		T240	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T135	10		T68	9		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T41	1		T141	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T159	11		T219	1		T154	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T15	4		T31	1		T221	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T199	9		T184	1		T225	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T234	1		T178	7		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T152	1		T225	8		T236	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13819	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T326	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T55	11		T49	1		T69	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T19	12		T41	14		T52	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T12	1		T14	1		T88	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T141	8		T69	15		T220	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T162	8		T169	4		T250	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T136	14		T180	16		T238	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T68	6		T236	1		T290	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T17	11		T161	2		T241	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T54	3		T221	1		T143	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	2		T245	21		T223	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T55	14		T50	1		T68	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T187	16		T251	11		T301	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T21	7		T151	18		T171	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T135	10		T68	4		T153	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T41	13		T141	9		T151	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T159	13		T154	14		T293	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T221	13		T223	1		T172	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T230	9		T40	14		T266	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T234	9		T178	4		T163	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T152	16		T236	1		T267	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T326	16		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T234	1		T248	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T165	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T326	12		T291	4		T175	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T55	9		T49	3		T178	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T19	1		T137	1		T144	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T14	4		T16	1		T18	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T41	1		T140	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	4		T20	10		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T17	1		T136	13		T180	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T68	3		T142	1		T181	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T161	3		T184	1		T286	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T54	4		T55	12		T151	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	4		T153	2		T185	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T5	1		T50	2		T68	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T144	2		T251	1		T162	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T224	1		T151	13		T240	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T135	7		T68	9		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T21	1		T41	1		T160	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T135	10		T219	1		T185	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T15	4		T31	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T159	11		T199	9		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13819	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T234	9		T248	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T326	16		T291	3		T175	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T55	11		T49	1		T178	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T19	12		T144	10		T194	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T14	1		T88	20		T254	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T41	14		T141	8		T69	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	1		T138	8		T51	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T17	11		T136	14		T180	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T68	6		T162	8		T236	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T161	2		T238	8		T241	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T54	3		T55	14		T151	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T13	2		T245	21		T253	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T50	1		T68	5		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T251	11		T162	13		T223	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T151	18		T34	1		T40	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T68	4		T153	8		T187	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T21	7		T41	13		T160	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T135	10		T154	14		T257	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T141	9		T151	9		T160	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T159	13		T152	16		T293	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

auto[0]

4101

1

T12

1

T13

2

T14

1