Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22619

1

T3

20

T4

14

T5

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

16789

1

T3

20

T4

14

T5

1

auto[ADC_CTRL_FILTER_COND_OUT]

5830

1

T5

1

T14

5

T16

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16851

1

T3

20

T4

14

T5

2

auto[1]

5768

1

T12

5

T13

6

T15

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18774

1

T3

20

T4

14

T5

2

auto[1]

3845

1

T13

2

T14

1

T18

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	312	1			T20	10		T137	1		T148	11
values[0]	2	1			T196	1		T218	1		-	-
values[1]	666	1			T19	13		T41	15		T79	11
values[2]	557	1			T159	24		T139	12		T161	5
values[3]	708	1			T15	4		T41	14		T138	9
values[4]	694	1			T5	1		T12	5		T55	20
values[5]	510	1			T17	12		T68	13		T140	1
values[6]	807	1			T14	5		T21	8		T54	7
values[7]	603	1			T13	6		T135	27		T50	3
values[8]	629	1			T137	1		T219	1		T141	9
values[9]	3312	1			T16	1		T31	1		T18	19
minimum	13819	1			T3	20		T4	14		T5	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	697	1			T19	13		T41	15		T159	24
values[1]	2731	1			T16	1		T18	19		T88	22
values[2]	764	1			T5	1		T12	5		T15	4
values[3]	662	1			T55	20		T199	9		T151	12
values[4]	598	1			T17	12		T68	22		T136	27
values[5]	737	1			T14	5		T21	8		T54	7
values[6]	682	1			T13	6		T135	27		T50	3
values[7]	574	1			T137	1		T219	1		T69	36
values[8]	1019	1			T20	10		T137	1		T148	11
values[9]	162	1			T31	1		T144	20		T220	20
minimum	13993	1			T3	20		T4	14		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

4101

1

T12

1

T13

2

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T19	13		T159	14		T32	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T41	15		T161	3		T185	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T222	1		T249	6		T228	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1612	1			T16	1		T18	2		T88	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	5		T15	4		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	1		T41	14		T69	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T154	1		T223	13		T238	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T55	12		T199	1		T151	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T68	12		T153	1		T34	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T17	12		T136	15		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T21	8		T49	3		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	4		T54	4		T55	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	4		T135	12		T50	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T141	9		T151	10		T160	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T137	1		T219	1		T225	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T69	16		T184	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T137	1		T148	1		T68	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T20	1		T52	2		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T31	1		T144	1		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T144	11		T220	11		T227	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13760	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T221	14		T304	4		T278	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T159	10		T153	1		T186	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T161	2		T185	9		T322	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T228	4		T328	2		T235	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	962	1			T18	17		T229	14		T139	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T150	9		T160	2		T221	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T69	1		T153	10		T33	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T154	1		T223	12		T230	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T55	8		T199	8		T151	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T68	10		T153	1		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T136	12		T151	12		T178	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	1		T180	17		T187	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T14	1		T54	3		T55	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	2		T135	15		T189	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T160	8		T162	13		T231	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T225	16		T194	14		T168	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T69	20		T189	13		T232	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T148	10		T51	1		T225	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T20	9		T52	1		T144	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T144	1		T190	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T144	7		T220	9		T227	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T78	1		T79	11		T143	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T221	14		T304	9		T278	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T137	1		T148	1		T144	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T20	1		T52	2		T144	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T196	1		T218	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T19	13		T79	1		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T41	15		T221	14		T185	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T159	14		T163	14		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T139	1		T161	3		T154	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	4		T221	2		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T41	14		T138	9		T69	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T12	5		T150	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	1		T55	12		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T68	5		T153	1		T34	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T17	12		T140	1		T151	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T21	8		T49	3		T68	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T14	4		T54	4		T55	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	4		T135	12		T50	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T151	10		T152	17		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T137	1		T219	1		T225	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T141	9		T69	16		T160	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T31	1		T68	6		T51	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1763	1			T16	1		T18	2		T88	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13719	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T148	10		T144	1		T225	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T20	9		T52	1		T144	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T79	10		T143	9		T153	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T221	14		T185	9		T322	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T159	10		T235	2		T191	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T139	11		T161	2		T154	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T221	7		T194	17		T236	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T69	1		T153	10		T33	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T150	9		T160	2		T154	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T55	8		T199	8		T181	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T68	8		T153	1		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T151	9		T245	15		T156	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T49	1		T68	2		T187	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	1		T54	3		T55	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	2		T135	15		T180	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T154	1		T162	13		T231	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T225	16		T194	14		T168	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T69	20		T160	8		T189	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T51	1		T186	2		T245	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1034	1			T18	17		T229	14		T200	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T19	1		T159	11		T32	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T41	1		T161	3		T185	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T222	1		T249	1		T228	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1294	1			T16	1		T18	19		T88	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	4		T15	4		T150	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	1		T41	1		T69	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T154	2		T223	13		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T55	9		T199	9		T151	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T68	12		T153	2		T34	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T17	1		T136	13		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T21	1		T49	3		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	4		T54	4		T55	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	4		T135	17		T50	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T141	1		T151	1		T160	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T137	1		T219	1		T225	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T69	21		T184	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T137	1		T148	11		T68	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T20	10		T52	2		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T31	1		T144	2		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T144	8		T220	10		T227	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13877	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T221	15		T304	10		T278	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T19	12		T159	13		T172	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T41	14		T161	2		T188	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T249	5		T235	2		T191	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1280	1			T88	20		T138	8		T254	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	1		T160	3		T221	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T41	13		T69	1		T153	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T223	12		T238	8		T239	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T55	11		T151	2		T240	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T68	10		T34	1		T241	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T17	11		T136	14		T151	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T21	7		T49	1		T141	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	1		T54	3		T55	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T135	10		T50	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T141	8		T151	9		T160	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T194	12		T245	10		T242	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T69	15		T244	12		T281	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T68	5		T51	1		T238	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T52	1		T144	10		T171	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T246	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T144	10		T220	10		T289	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T234	9		T143	12		T269	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T221	13		T304	3		T278	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T137	1		T148	11		T144	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T20	10		T52	2		T144	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T196	1		T218	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T19	1		T79	11		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T41	1		T221	15		T185	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T159	11		T163	1		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T139	12		T161	3		T154	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T15	4		T221	8		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T41	1		T138	1		T69	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	4		T150	10		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T5	1		T55	9		T199	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T68	9		T153	2		T34	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T17	1		T140	1		T151	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T21	1		T49	3		T68	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	4		T54	4		T55	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	4		T135	17		T50	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T151	1		T152	1		T154	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T137	1		T219	1		T225	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T141	1		T69	21		T160	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T31	1		T68	1		T51	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1380	1			T16	1		T18	19		T88	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13819	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T252	9		T98	5		T329	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T52	1		T144	10		T289	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T19	12		T234	9		T143	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T41	14		T221	13		T188	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T159	13		T163	13		T249	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T161	2		T154	14		T163	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T221	1		T251	20		T194	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T41	13		T138	8		T69	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T12	1		T160	3		T223	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T55	11		T240	12		T261	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T68	4		T34	1		T241	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T17	11		T151	2		T245	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T21	7		T49	1		T68	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T14	1		T54	3		T55	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T13	2		T135	10		T50	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T151	9		T152	16		T162	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T194	12		T242	3		T171	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T141	8		T69	15		T160	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T68	5		T51	1		T245	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1417	1			T88	20		T254	14		T197	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

auto[0]

4101

1

T12

1

T13

2

T14

1