Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22619

1

T3

20

T4

14

T5

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19259

1

T3

20

T4

14

T5

2

auto[ADC_CTRL_FILTER_COND_OUT]

3360

1

T14

5

T15

4

T17

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16860

1

T3

20

T4

14

T5

1

auto[1]

5759

1

T5

1

T16

1

T17

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18774

1

T3

20

T4

14

T5

2

auto[1]

3845

1

T13

2

T14

1

T18

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	204	1			T139	12		T51	4		T199	9
values[0]	14	1			T267	14		-	-		-	-
values[1]	597	1			T15	4		T135	7		T68	22
values[2]	586	1			T159	24		T79	11		T141	9
values[3]	586	1			T12	5		T219	1		T151	12
values[4]	558	1			T138	9		T150	10		T219	1
values[5]	2721	1			T13	6		T16	1		T18	19
values[6]	710	1			T5	1		T14	5		T31	1
values[7]	881	1			T17	12		T41	14		T54	7
values[8]	653	1			T68	6		T221	28		T222	1
values[9]	1290	1			T19	13		T20	10		T21	8
minimum	13819	1			T3	20		T4	14		T5	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	467	1			T15	4		T135	7		T68	9
values[1]	730	1			T12	5		T68	13		T159	24
values[2]	432	1			T219	1		T151	12		T144	2
values[3]	2845	1			T16	1		T18	19		T88	22
values[4]	541	1			T5	1		T13	6		T31	1
values[5]	878	1			T14	5		T54	7		T55	20
values[6]	739	1			T17	12		T41	14		T55	26
values[7]	625	1			T21	8		T68	6		T141	10
values[8]	1181	1			T19	13		T20	10		T135	20
values[9]	147	1			T51	4		T153	2		T154	2
minimum	14034	1			T3	20		T4	14		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

4101

1

T12

1

T13

2

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T135	1		T224	1		T136	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T15	4		T68	7		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	5		T159	14		T79	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T68	5		T219	1		T52	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T219	1		T225	1		T61	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T151	3		T144	1		T223	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1619	1			T16	1		T18	2		T88	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T138	9		T221	2		T153	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	1		T13	4		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T49	3		T50	3		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T69	16		T222	2		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T14	4		T54	4		T55	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T41	14		T55	15		T234	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T17	12		T148	1		T160	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T141	10		T162	9		T220	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T21	8		T68	6		T151	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T19	13		T135	11		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T20	1		T137	1		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T168	2		T282	6		T279	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T51	3		T153	1		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13768	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T140	1		T267	14		T260	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T135	6		T136	12		T178	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T68	2		T186	13		T240	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T159	10		T79	10		T69	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T68	8		T52	1		T187	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T225	7		T262	8		T285	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T151	9		T144	1		T223	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T18	17		T150	9		T229	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T221	7		T153	11		T154	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T13	2		T154	1		T189	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T49	1		T232	10		T190	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T69	20		T241	12		T266	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	1		T54	3		T55	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T55	11		T178	6		T145	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T148	10		T160	8		T186	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T162	9		T220	9		T330	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T151	12		T221	14		T223	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T135	9		T139	11		T160	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T20	9		T199	8		T161	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T168	23		T282	5		T279	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T51	1		T153	1		T154	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T78	1		T79	1		T181	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T260	7		T271	9		T167	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T139	1		T225	1		T170	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T51	3		T199	1		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T267	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T135	1		T224	1		T136	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T15	4		T68	12		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T159	14		T79	1		T141	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T52	2		T187	17		T251	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T12	5		T225	1		T61	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T219	1		T151	3		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T150	1		T219	1		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T138	9		T221	2		T153	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1627	1			T13	4		T16	1		T18	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T49	3		T50	3		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T5	1		T31	1		T41	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	4		T184	1		T251	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T41	14		T55	15		T69	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T17	12		T54	4		T55	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T240	1		T162	9		T220	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T68	6		T221	14		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T19	13		T135	11		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	400	1			T20	1		T21	8		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13719	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T139	11		T225	7		T156	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T51	1		T199	8		T154	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T135	6		T136	12		T181	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T68	10		T186	13		T260	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T159	10		T79	10		T69	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T52	1		T187	17		T240	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T225	7		T262	8		T213	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T151	9		T144	1		T223	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T150	9		T189	4		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T221	7		T153	11		T154	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	915	1			T13	2		T18	17		T229	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T49	1		T232	10		T190	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T266	2		T290	3		T271	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	1		T245	15		T288	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T55	11		T69	20		T178	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T54	3		T55	8		T148	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T240	1		T162	9		T220	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T221	14		T223	12		T236	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T135	9		T160	2		T143	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T20	9		T151	12		T161	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T135	7		T224	1		T136	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T15	4		T68	3		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	4		T159	11		T79	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T68	9		T219	1		T52	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T219	1		T225	8		T61	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T151	10		T144	2		T223	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T16	1		T18	19		T88	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T138	1		T221	8		T153	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	1		T13	4		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T49	3		T50	2		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T69	21		T222	2		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	4		T54	4		T55	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T41	1		T55	12		T234	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T17	1		T148	11		T160	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T141	1		T162	10		T220	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T21	1		T68	1		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T19	1		T135	10		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T20	10		T137	1		T199	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T168	25		T282	6		T279	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T51	3		T153	2		T154	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13858	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T140	1		T267	1		T260	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T136	14		T141	8		T178	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T68	6		T240	12		T172	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	1		T159	13		T69	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T68	4		T52	1		T187	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T166	12		T326	4		T323	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T151	2		T223	15		T171	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T88	20		T254	14		T197	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T138	8		T221	1		T153	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	2		T41	14		T151	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T49	1		T50	1		T163	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T69	15		T241	16		T249	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	1		T54	3		T55	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T41	13		T55	14		T234	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T17	11		T160	9		T230	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T141	9		T162	8		T220	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T21	7		T68	5		T151	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T19	12		T135	10		T160	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T161	2		T152	16		T33	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T282	5		T279	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T51	1		T271	9		T244	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T245	10		T305	15		T237	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T267	13		T271	7		T324	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T139	12		T225	8		T170	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T51	3		T199	9		T154	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T267	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T135	7		T224	1		T136	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T15	4		T68	12		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T159	11		T79	11		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T52	2		T187	18		T251	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	4		T225	8		T61	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T219	1		T151	10		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T150	10		T219	1		T189	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T138	1		T221	8		T153	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T13	4		T16	1		T18	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T49	3		T50	2		T232	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	1		T31	1		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	4		T184	1		T251	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T41	1		T55	12		T69	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T17	1		T54	4		T55	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T240	2		T162	10		T220	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T68	1		T221	15		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T19	1		T135	10		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T20	10		T21	1		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13819	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T259	7		T331	9		T332	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T51	1		T292	2		T300	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T267	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T136	14		T194	15		T245	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T68	10		T172	12		T263	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T159	13		T141	8		T69	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T52	1		T187	16		T251	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T12	1		T315	12		T333	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T151	2		T223	15		T171	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T37	2		T334	9		T166	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T138	8		T221	1		T153	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T13	2		T88	20		T254	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T49	1		T50	1		T163	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T41	14		T169	4		T249	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	1		T251	9		T245	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T41	13		T55	14		T69	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T17	11		T54	3		T55	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T162	8		T220	10		T261	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T68	5		T221	13		T223	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T19	12		T135	10		T141	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T21	7		T151	18		T161	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

auto[0]

4101

1

T12

1

T13

2

T14

1