Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22619

1

T3

20

T4

14

T5

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19624

1

T3

20

T4

14

T5

1

auto[ADC_CTRL_FILTER_COND_OUT]

2995

1

T5

1

T13

6

T15

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16880

1

T3

20

T4

14

T5

1

auto[1]

5739

1

T5

1

T12

5

T15

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18774

1

T3

20

T4

14

T5

2

auto[1]

3845

1

T13

2

T14

1

T18

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	45	1			T185	10		T270	8		T335	27
values[0]	38	1			T156	5		T191	17		T98	16
values[1]	441	1			T135	20		T161	5		T32	1
values[2]	665	1			T137	1		T50	3		T159	24
values[3]	735	1			T55	26		T135	7		T68	13
values[4]	624	1			T14	5		T17	12		T19	13
values[5]	675	1			T41	15		T136	27		T139	12
values[6]	765	1			T138	9		T69	39		T160	6
values[7]	737	1			T12	5		T55	20		T150	10
values[8]	576	1			T5	1		T148	11		T68	6
values[9]	3499	1			T13	6		T15	4		T16	1
minimum	13819	1			T3	20		T4	14		T5	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	669	1			T135	20		T50	3		T159	24
values[1]	590	1			T137	1		T51	4		T151	31
values[2]	771	1			T17	12		T21	8		T135	7
values[3]	622	1			T14	5		T19	13		T41	29
values[4]	657	1			T136	27		T139	12		T151	10
values[5]	829	1			T12	5		T138	9		T79	11
values[6]	2903	1			T16	1		T18	19		T55	20
values[7]	581	1			T5	1		T137	1		T49	4
values[8]	993	1			T15	4		T31	1		T20	10
values[9]	169	1			T13	6		T185	10		T40	1
minimum	13835	1			T3	20		T4	14		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

4101

1

T12

1

T13

2

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T161	3		T34	2		T168	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T135	11		T50	3		T159	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T154	15		T225	1		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T137	1		T51	3		T151	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T21	8		T135	1		T68	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T17	12		T141	10		T221	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	4		T41	15		T55	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T19	13		T41	14		T68	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T136	15		T151	10		T152	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T139	1		T152	17		T336	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T12	5		T138	9		T69	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T79	1		T160	4		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1615	1			T16	1		T18	2		T55	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T150	1		T68	6		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T49	3		T148	1		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T5	1		T137	1		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T31	1		T141	9		T151	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T15	4		T20	1		T54	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T185	1		T40	1		T301	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T13	4		T317	1		T262	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13730	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T32	1		T310	1		T330	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T161	2		T34	1		T168	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T135	9		T159	10		T153	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T154	14		T225	7		T260	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T51	1		T151	12		T221	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T135	6		T68	8		T52	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T221	14		T189	4		T40	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	1		T55	11		T160	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T68	2		T143	9		T178	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T136	12		T225	9		T194	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T139	11		T326	11		T294	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T69	21		T180	17		T186	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T79	10		T160	2		T33	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T18	17		T55	8		T229	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T150	9		T37	1		T220	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T49	1		T148	10		T199	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T153	1		T236	1		T289	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T151	9		T178	6		T187	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T20	9		T54	3		T144	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T185	9		T175	13		T335	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T13	2		T317	11		T262	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T330	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T185	1		T270	8		T335	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T98	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T156	1		T191	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T161	3		T231	1		T171	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T135	11		T32	1		T181	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T154	15		T225	1		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T137	1		T50	3		T159	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T55	15		T135	1		T68	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T141	10		T221	14		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	4		T21	8		T151	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T17	12		T19	13		T41	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T41	15		T136	15		T160	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T139	1		T152	17		T178	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T138	9		T69	18		T152	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T160	4		T33	7		T260	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	5		T55	12		T240	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T150	1		T224	1		T79	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T148	1		T219	1		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T5	1		T68	6		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1741	1			T16	1		T31	1		T18	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T13	4		T15	4		T20	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13719	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T185	9		T335	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T98	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T156	4		T191	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T161	2		T231	1		T230	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T135	9		T181	1		T162	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T154	14		T225	7		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T159	10		T51	1		T151	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T55	11		T135	6		T68	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T221	14		T154	1		T145	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	1		T153	10		T144	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T68	2		T143	9		T225	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T136	12		T160	8		T225	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T139	11		T178	6		T189	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T69	21		T180	17		T245	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T160	2		T33	3		T260	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T55	8		T240	13		T223	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T150	9		T79	10		T162	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T148	10		T199	8		T144	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T153	1		T37	1		T289	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1109	1			T18	17		T49	1		T229	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T13	2		T20	9		T54	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T161	3		T34	2		T168	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T135	10		T50	2		T159	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T154	15		T225	8		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T137	1		T51	3		T151	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T21	1		T135	7		T68	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T17	1		T141	1		T221	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	4		T41	1		T55	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T19	1		T41	1		T68	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T136	13		T151	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T139	12		T152	1		T336	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T12	4		T138	1		T69	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T79	11		T160	3		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T16	1		T18	19		T55	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T150	10		T68	1		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T49	3		T148	11		T199	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T5	1		T137	1		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T31	1		T141	1		T151	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T15	4		T20	10		T54	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T185	10		T40	1		T301	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T13	4		T317	12		T262	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13820	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T32	1		T310	1		T330	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T161	2		T34	1		T171	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T135	10		T50	1		T159	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T154	14		T237	10		T191	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T51	1		T151	18		T221	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T21	7		T68	4		T52	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T17	11		T141	9		T221	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T14	1		T41	14		T55	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T19	12		T41	13		T68	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T136	14		T151	9		T152	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T152	16		T258	4		T326	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T12	1		T138	8		T69	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T160	3		T33	3		T162	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T55	11		T88	20		T254	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T68	5		T37	2		T220	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T49	1		T172	9		T259	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T236	1		T163	14		T289	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T141	8		T151	2		T178	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T54	3		T188	5		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T301	10		T175	24		T270	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T13	2		T271	7		T337	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T338	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T185	10		T270	1		T335	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T98	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T156	5		T191	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T161	3		T231	2		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T135	10		T32	1		T181	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T154	15		T225	8		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T137	1		T50	2		T159	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T55	12		T135	7		T68	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T141	1		T221	15		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	4		T21	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T17	1		T19	1		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T41	1		T136	13		T160	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T139	12		T152	1		T178	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T138	1		T69	23		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T160	3		T33	7		T260	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T12	4		T55	9		T240	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T150	10		T224	1		T79	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T148	11		T219	1		T199	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T5	1		T68	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1466	1			T16	1		T31	1		T18	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	382	1			T13	4		T15	4		T20	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13819	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T270	7		T335	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T98	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T191	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T161	2		T171	13		T230	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T135	10		T162	13		T250	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T154	14		T34	1		T237	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T50	1		T159	13		T51	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T55	14		T68	4		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T141	9		T221	13		T305	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	1		T21	7		T151	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T17	11		T19	12		T41	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T41	14		T136	14		T160	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T152	16		T178	4		T257	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T138	8		T69	16		T152	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T160	3		T33	3		T258	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	1		T55	11		T240	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T162	8		T238	8		T220	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T234	9		T144	10		T267	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T68	5		T37	2		T289	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T88	20		T49	1		T254	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T13	2		T54	3		T188	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

auto[0]

4101

1

T12

1

T13

2

T14

1