Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22619

1

T3

20

T4

14

T5

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19113

1

T3

20

T4

14

T5

2

auto[ADC_CTRL_FILTER_COND_OUT]

3506

1

T15

4

T17

12

T19

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16775

1

T3

20

T4

14

T5

2

auto[1]

5844

1

T12

5

T15

4

T16

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18774

1

T3

20

T4

14

T5

2

auto[1]

3845

1

T13

2

T14

1

T18

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	292	1			T21	8		T49	4		T225	8
values[0]	29	1			T40	1		T192	28		-	-
values[1]	596	1			T51	4		T199	9		T151	12
values[2]	644	1			T12	5		T41	14		T224	1
values[3]	629	1			T41	15		T69	36		T52	3
values[4]	652	1			T54	7		T135	20		T50	3
values[5]	540	1			T17	12		T55	20		T137	1
values[6]	745	1			T13	6		T15	4		T138	9
values[7]	749	1			T5	1		T14	5		T31	1
values[8]	3010	1			T16	1		T18	19		T88	22
values[9]	914	1			T19	13		T20	10		T55	26
minimum	13819	1			T3	20		T4	14		T5	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	527	1			T12	5		T151	12		T154	2
values[1]	672	1			T41	14		T224	1		T139	12
values[2]	703	1			T41	15		T54	7		T135	20
values[3]	527	1			T50	3		T219	1		T152	17
values[4]	585	1			T17	12		T55	20		T137	1
values[5]	724	1			T13	6		T15	4		T31	1
values[6]	3113	1			T5	1		T14	5		T16	1
values[7]	659	1			T150	10		T151	10		T161	5
values[8]	938	1			T19	13		T20	10		T21	8
values[9]	123	1			T160	6		T225	8		T168	9
minimum	14048	1			T3	20		T4	14		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

4101

1

T12

1

T13

2

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	5		T154	1		T255	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T151	3		T145	1		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T41	14		T224	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T184	1		T33	7		T251	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T68	7		T69	16		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T41	15		T54	4		T135	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T50	3		T219	1		T152	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T245	12		T257	11		T171	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T137	1		T221	2		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T17	12		T55	12		T151	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	4		T31	1		T138	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T15	4		T69	2		T160	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1703	1			T5	1		T14	4		T16	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T79	1		T219	1		T143	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T32	1		T184	1		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T150	1		T151	10		T161	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T20	1		T21	8		T55	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T19	13		T148	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T160	4		T225	1		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T168	1		T245	11		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13752	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T199	1		T171	10		T220	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T154	1		T328	2		T339	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T151	9		T145	16		T240	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T139	11		T172	23		T259	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T33	3		T186	15		T40	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T68	2		T69	20		T242	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T54	3		T135	9		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T153	1		T194	14		T230	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T245	15		T260	7		T261	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T221	7		T189	4		T262	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T55	8		T151	12		T180	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	2		T68	8		T159	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T69	1		T160	8		T221	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T14	1		T18	17		T229	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T79	10		T143	9		T144	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T236	2		T195	7		T263	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T150	9		T161	2		T194	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T20	9		T55	11		T135	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T148	10		T144	15		T189	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T160	2		T225	7		T231	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T168	8		T245	8		T272	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T78	1		T79	1		T51	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T199	8		T220	9		T271	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T21	8		T49	3		T225	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T168	1		T241	17		T170	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T40	1		T192	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T51	3		T154	1		T255	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T199	1		T151	3		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	5		T41	14		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T184	1		T145	1		T33	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T69	16		T142	1		T152	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T41	15		T52	2		T251	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T50	3		T68	7		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T54	4		T135	11		T141	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T137	1		T194	13		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T17	12		T55	12		T151	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	4		T138	9		T68	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T15	4		T160	10		T221	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	1		T14	4		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T69	2		T143	13		T181	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1622	1			T16	1		T18	2		T88	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T150	1		T79	1		T219	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T20	1		T55	15		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T19	13		T148	1		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13719	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T49	1		T225	7		T288	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T168	8		T241	12		T156	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T192	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T51	1		T154	1		T227	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T199	8		T151	9		T240	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T139	11		T172	23		T228	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T145	16		T33	3		T186	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T69	20		T242	17		T236	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T52	1		T186	2		T168	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T68	2		T153	1		T266	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T54	3		T135	9		T187	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T194	14		T189	4		T230	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T55	8		T151	12		T180	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	2		T68	8		T159	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T160	8		T221	14		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T14	1		T136	12		T225	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T69	1		T143	9		T181	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T18	17		T229	14		T200	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T150	9		T79	10		T161	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T20	9		T55	11		T135	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T148	10		T144	15		T245	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	4		T154	2		T255	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T151	10		T145	17		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T41	1		T224	1		T139	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T184	1		T33	7		T251	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T68	3		T69	21		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T41	1		T54	4		T135	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T50	2		T219	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T245	16		T257	1		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T137	1		T221	8		T189	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T17	1		T55	9		T151	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	4		T31	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T15	4		T69	2		T160	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1415	1			T5	1		T14	4		T16	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T79	11		T219	1		T143	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T32	1		T184	1		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T150	10		T151	1		T161	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T20	10		T21	1		T55	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T19	1		T148	11		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T160	3		T225	8		T231	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T168	9		T245	9		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T199	9		T171	1		T220	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T12	1		T249	8		T339	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T151	2		T223	15		T166	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T41	13		T267	13		T249	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T33	3		T251	9		T238	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T68	6		T69	15		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T41	14		T54	3		T135	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T50	1		T152	16		T194	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T245	11		T257	10		T171	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T221	1		T259	7		T268	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T17	11		T55	11		T151	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T13	2		T138	8		T68	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T69	1		T160	9		T221	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T14	1		T88	20		T136	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T143	12		T144	10		T178	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T236	1		T263	11		T269	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T151	9		T161	2		T194	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T21	7		T55	14		T49	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T19	12		T144	10		T241	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T160	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T245	10		T272	6		T340	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T51	1		T172	3		T341	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T171	9		T220	10		T271	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T21	1		T49	3		T225	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T168	9		T241	13		T170	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T40	1		T192	16		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T51	3		T154	2		T255	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T199	9		T151	10		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	4		T41	1		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T184	1		T145	17		T33	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T69	21		T142	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T41	1		T52	2		T251	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T50	2		T68	3		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T54	4		T135	10		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T137	1		T194	15		T189	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T17	1		T55	9		T151	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T13	4		T138	1		T68	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T15	4		T160	9		T221	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T5	1		T14	4		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T69	2		T143	10		T181	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T16	1		T18	19		T88	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T150	10		T79	11		T219	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T20	10		T55	12		T135	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T19	1		T148	11		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13819	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T21	7		T49	1		T325	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T241	16		T271	9		T99	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T192	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T51	1		T172	3		T339	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T151	2		T223	15		T171	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	1		T41	13		T267	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T33	3		T251	9		T238	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T69	15		T152	13		T242	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T41	14		T52	1		T251	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T50	1		T68	6		T152	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T54	3		T135	10		T141	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T194	12		T230	9		T259	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T17	11		T55	11		T151	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	2		T138	8		T68	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T160	9		T221	13		T234	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	1		T136	14		T240	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T69	1		T143	12		T274	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T88	20		T254	14		T141	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T151	9		T161	2		T144	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T55	14		T68	5		T160	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T19	12		T144	10		T245	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

auto[0]

4101

1

T12

1

T13

2

T14

1