Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22619

1

T3

20

T4

14

T5

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19611

1

T3

20

T4

14

T5

1

auto[ADC_CTRL_FILTER_COND_OUT]

3008

1

T5

1

T13

6

T17

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16964

1

T3

20

T4

14

T5

1

auto[1]

5655

1

T5

1

T12

5

T14

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18774

1

T3

20

T4

14

T5

2

auto[1]

3845

1

T13

2

T14

1

T18

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	288	1			T20	10		T185	10		T286	1
values[0]	22	1			T156	5		T191	17		-	-
values[1]	462	1			T135	20		T161	5		T32	1
values[2]	636	1			T137	1		T50	3		T159	24
values[3]	731	1			T135	7		T68	13		T141	10
values[4]	668	1			T14	5		T17	12		T19	13
values[5]	663	1			T41	15		T136	27		T139	12
values[6]	800	1			T12	5		T138	9		T69	39
values[7]	701	1			T55	20		T150	10		T68	6
values[8]	564	1			T5	1		T219	1		T199	9
values[9]	3265	1			T13	6		T15	4		T16	1
minimum	13819	1			T3	20		T4	14		T5	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	565	1			T135	20		T50	3		T159	24
values[1]	642	1			T137	1		T51	4		T151	31
values[2]	689	1			T17	12		T21	8		T135	7
values[3]	634	1			T14	5		T19	13		T41	29
values[4]	702	1			T136	27		T139	12		T151	10
values[5]	785	1			T12	5		T138	9		T79	11
values[6]	2913	1			T16	1		T18	19		T55	20
values[7]	613	1			T5	1		T148	11		T199	9
values[8]	994	1			T15	4		T31	1		T20	10
values[9]	141	1			T13	6		T185	10		T262	9
minimum	13941	1			T3	20		T4	14		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

4101

1

T12

1

T13

2

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T161	3		T34	2		T230	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T135	11		T50	3		T159	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T154	15		T225	1		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T137	1		T51	3		T151	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T21	8		T135	1		T68	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T17	12		T141	10		T221	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	4		T41	15		T55	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T19	13		T41	14		T68	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T136	15		T152	14		T180	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T139	1		T151	10		T152	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T12	5		T138	9		T69	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T79	1		T160	4		T33	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1611	1			T16	1		T18	2		T55	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T150	1		T68	6		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T148	1		T153	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	1		T199	1		T255	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T15	4		T31	1		T54	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T20	1		T137	1		T219	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T185	1		T301	11		T342	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T13	4		T262	1		T271	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13774	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T231	1		T156	1		T292	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T161	2		T34	1		T230	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T135	9		T159	10		T153	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T154	14		T225	7		T168	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T51	1		T151	12		T221	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T135	6		T68	8		T52	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T221	14		T143	9		T189	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	1		T55	11		T160	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T68	2		T225	7		T189	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T136	12		T180	17		T225	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T139	11		T326	11		T294	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T69	21		T240	13		T245	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T79	10		T160	2		T33	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1019	1			T18	17		T55	8		T229	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T150	9		T37	1		T220	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T148	10		T153	1		T186	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T199	8		T236	1		T289	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T54	3		T49	1		T151	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T20	9		T144	1		T154	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T185	9		T175	11		T335	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T13	2		T262	8		T271	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T78	1		T79	1		T217	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T231	1		T156	4		T292	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T185	1		T286	1		T322	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T20	1		T39	5		T300	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T191	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T156	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T161	3		T32	1		T34	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T135	11		T181	2		T162	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T154	15		T225	1		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T137	1		T50	3		T159	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T135	1		T68	5		T52	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T141	10		T221	14		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	4		T21	8		T55	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T17	12		T19	13		T41	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T41	15		T136	15		T160	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T139	1		T151	10		T152	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T12	5		T138	9		T69	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T160	4		T33	7		T162	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T55	12		T224	1		T234	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T150	1		T68	6		T79	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T219	1		T153	1		T144	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T5	1		T199	1		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1695	1			T15	4		T16	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T13	4		T137	1		T219	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13719	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T185	9		T322	2		T296	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T20	9		T39	3		T300	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T191	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T156	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T161	2		T34	1		T230	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T135	9		T181	1		T162	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T154	14		T225	7		T168	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T159	10		T51	1		T151	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T135	6		T68	8		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T221	14		T154	1		T145	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T14	1		T55	11		T153	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T68	2		T143	9		T225	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T136	12		T160	8		T225	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T139	11		T189	13		T327	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T69	21		T180	17		T245	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T160	2		T33	3		T162	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T55	8		T240	13		T223	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T150	9		T79	10		T220	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T153	1		T144	14		T172	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T199	8		T37	1		T289	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T18	17		T54	3		T49	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	2		T144	1		T154	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T161	3		T34	2		T230	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T135	10		T50	2		T159	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T154	15		T225	8		T168	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T137	1		T51	3		T151	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T21	1		T135	7		T68	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T17	1		T141	1		T221	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	4		T41	1		T55	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T19	1		T41	1		T68	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T136	13		T152	1		T180	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T139	12		T151	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	4		T138	1		T69	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T79	11		T160	3		T33	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T16	1		T18	19		T55	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T150	10		T68	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T148	11		T153	2		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	1		T199	9		T255	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T15	4		T31	1		T54	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T20	10		T137	1		T219	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T185	10		T301	1		T342	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T13	4		T262	9		T271	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13848	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T231	2		T156	5		T292	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T161	2		T34	1		T230	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T135	10		T50	1		T159	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T154	14		T237	10		T191	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T51	1		T151	18		T221	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T21	7		T68	4		T52	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T17	11		T141	9		T221	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	1		T41	14		T55	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T19	12		T41	13		T68	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T136	14		T152	13		T180	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T151	9		T152	16		T257	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	1		T138	8		T69	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T160	3		T33	3		T162	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T55	11		T88	20		T254	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T68	5		T37	2		T220	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T267	13		T172	9		T259	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T236	1		T163	14		T289	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T54	3		T49	1		T141	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T163	13		T39	1		T266	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T301	10		T175	11		T270	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T13	2		T271	7		T337	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T171	13		T249	13		T191	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T292	2		T237	5		T343	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T185	10		T286	1		T322	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T20	10		T39	7		T300	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T191	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T156	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T161	3		T32	1		T34	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T135	10		T181	3		T162	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T154	15		T225	8		T168	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T137	1		T50	2		T159	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T135	7		T68	9		T52	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T141	1		T221	15		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	4		T21	1		T55	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T17	1		T19	1		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T41	1		T136	13		T160	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T139	12		T151	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	4		T138	1		T69	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T160	3		T33	7		T162	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T55	9		T224	1		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T150	10		T68	1		T79	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T219	1		T153	2		T144	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	1		T199	9		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T15	4		T16	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T13	4		T137	1		T219	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13819	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T322	8		T296	10		T301	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T39	1		T273	11		T344	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T191	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T161	2		T34	1		T171	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T135	10		T162	13		T292	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T154	14		T237	10		T246	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T50	1		T159	13		T51	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T68	4		T52	1		T40	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T141	9		T221	13		T245	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	1		T21	7		T55	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T17	11		T19	12		T41	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T41	14		T136	14		T160	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T151	9		T152	16		T257	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	1		T138	8		T69	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T160	3		T33	3		T162	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T55	11		T234	9		T240	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T68	5		T238	8		T293	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T144	10		T172	9		T320	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T37	2		T289	1		T301	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T54	3		T88	20		T49	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	2		T236	1		T163	27

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

auto[0]

4101

1

T12

1

T13

2

T14

1