Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22619

1

T3

20

T4

14

T5

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19518

1

T3

20

T4

14

T5

1

auto[ADC_CTRL_FILTER_COND_OUT]

3101

1

T5

1

T31

1

T19

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16919

1

T3

20

T4

14

T5

2

auto[1]

5700

1

T13

6

T16

1

T18

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18774

1

T3

20

T4

14

T5

2

auto[1]

3845

1

T13

2

T14

1

T18

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	205	1			T31	1		T219	1		T69	3
values[0]	47	1			T298	1		T299	21		T302	25
values[1]	629	1			T224	1		T141	9		T151	31
values[2]	546	1			T20	10		T55	20		T135	27
values[3]	764	1			T13	6		T41	15		T150	10
values[4]	637	1			T138	9		T153	19		T144	25
values[5]	2950	1			T16	1		T18	19		T54	7
values[6]	597	1			T5	1		T17	12		T19	13
values[7]	739	1			T12	5		T55	26		T68	13
values[8]	899	1			T15	4		T21	8		T148	11
values[9]	787	1			T14	5		T137	2		T49	4
minimum	13819	1			T3	20		T4	14		T5	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	574	1			T141	9		T151	31		T184	1
values[1]	700	1			T13	6		T20	10		T55	20
values[2]	692	1			T41	15		T138	9		T150	10
values[3]	2894	1			T16	1		T18	19		T88	22
values[4]	754	1			T5	1		T41	14		T54	7
values[5]	560	1			T12	5		T17	12		T19	13
values[6]	839	1			T55	26		T68	13		T141	10
values[7]	742	1			T15	4		T21	8		T148	11
values[8]	753	1			T14	5		T31	1		T137	2
values[9]	118	1			T69	3		T186	14		T156	12
minimum	13993	1			T3	20		T4	14		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

4101

1

T12

1

T13

2

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T151	19		T255	1		T238	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T141	9		T184	1		T171	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T13	4		T135	1		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T20	1		T55	12		T135	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T51	3		T219	1		T144	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T41	15		T138	9		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T16	1		T18	2		T88	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T194	13		T170	1		T249	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T41	14		T68	6		T240	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	1		T54	4		T221	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T12	5		T17	12		T68	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T19	13		T236	3		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T69	16		T153	1		T144	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T55	15		T68	5		T141	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T15	4		T52	2		T152	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T21	8		T148	1		T159	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T14	4		T137	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T31	1		T137	1		T49	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T69	2		T186	1		T190	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T156	1		T164	1		T196	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13754	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T224	1		T230	10		T227	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T151	12		T220	9		T322	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T227	12		T300	1		T271	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T13	2		T135	6		T172	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T20	9		T55	8		T135	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T51	1		T144	15		T154	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T150	9		T185	9		T162	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T18	17		T229	14		T200	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T194	14		T195	20		T292	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T240	13		T227	9		T252	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T54	3		T221	7		T143	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T68	2		T79	10		T136	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T236	2		T271	14		T256	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T69	20		T153	1		T144	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T55	11		T68	8		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T52	1		T178	6		T245	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T148	10		T159	10		T151	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	1		T160	8		T153	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T49	1		T139	11		T199	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T69	1		T186	13		T190	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T156	11		T301	1		T345	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T78	1		T79	1		T160	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T230	7		T227	9		T299	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T219	1		T69	2		T186	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T31	1		T199	1		T61	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T298	1		T302	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T299	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T151	19		T160	4		T255	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T224	1		T141	9		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T135	1		T163	15		T40	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T20	1		T55	12		T135	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T13	4		T51	3		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T41	15		T150	1		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T153	9		T144	11		T181	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T138	9		T251	10		T194	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T16	1		T18	2		T88	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T54	4		T221	2		T143	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T17	12		T41	14		T68	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T5	1		T19	13		T225	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	5		T69	16		T221	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T55	15		T68	5		T141	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T15	4		T152	14		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T21	8		T148	1		T159	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T14	4		T137	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T137	1		T49	3		T50	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13719	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T69	1		T186	13		T300	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T199	8		T301	1		T95	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T302	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T299	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T151	12		T160	2		T220	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T230	7		T227	21		T271	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T135	6		T261	7		T237	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T20	9		T55	8		T135	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	2		T51	1		T144	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T150	9		T185	9		T154	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T153	10		T144	14		T181	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T194	14		T241	11		T195	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T18	17		T229	14		T200	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T54	3		T221	7		T143	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T68	2		T79	10		T136	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T225	9		T242	17		T236	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T69	20		T221	14		T178	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T55	11		T68	8		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T153	1		T144	7		T245	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T148	10		T159	10		T225	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	1		T160	8		T52	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T49	1		T139	11		T151	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T151	13		T255	1		T238	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T141	1		T184	1		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	4		T135	7		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T20	10		T55	9		T135	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T51	3		T219	1		T144	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T41	1		T138	1		T150	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T16	1		T18	19		T88	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T194	15		T170	1		T249	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T41	1		T68	1		T240	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	1		T54	4		T221	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	4		T17	1		T68	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T19	1		T236	4		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T69	21		T153	2		T144	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T55	12		T68	9		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T15	4		T52	2		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T21	1		T148	11		T159	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T14	4		T137	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T31	1		T137	1		T49	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T69	2		T186	14		T190	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T156	12		T164	1		T196	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13855	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T224	1		T230	8		T227	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T151	18		T238	13		T220	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T141	8		T171	6		T305	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	2		T163	14		T40	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T55	11		T135	10		T33	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T51	1		T144	10		T154	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T41	14		T138	8		T251	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T88	20		T254	14		T197	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T194	12		T249	5		T292	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T41	13		T68	5		T240	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T54	3		T221	1		T143	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	1		T17	11		T68	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T19	12		T236	1		T166	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T69	15		T144	10		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T55	14		T68	4		T141	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T52	1		T152	13		T178	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T21	7		T159	13		T151	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	1		T160	9		T172	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T49	1		T50	1		T151	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T69	1		T346	15		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T307	13		T308	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T160	3		T171	9		T290	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T230	9		T299	11		T347	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T219	1		T69	2		T186	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T31	1		T199	9		T61	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T298	1		T302	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T299	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T151	13		T160	3		T255	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T224	1		T141	1		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T135	7		T163	1		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T20	10		T55	9		T135	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T13	4		T51	3		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T41	1		T150	10		T185	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T153	11		T144	15		T181	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T138	1		T251	1		T194	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T16	1		T18	19		T88	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T54	4		T221	8		T143	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T17	1		T41	1		T68	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	1		T19	1		T225	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T12	4		T69	21		T221	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T55	12		T68	9		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T15	4		T152	1		T153	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T21	1		T148	11		T159	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T14	4		T137	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T137	1		T49	3		T50	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13819	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T69	1		T300	16		T274	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T307	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T302	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T299	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T151	18		T160	3		T238	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T141	8		T230	9		T271	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T163	14		T40	14		T261	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T55	11		T135	10		T33	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	2		T51	1		T180	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T41	14		T251	11		T162	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T153	8		T144	10		T187	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T138	8		T251	9		T194	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T88	20		T68	5		T254	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T54	3		T221	1		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T17	11		T41	13		T68	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T19	12		T242	3		T236	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	1		T69	15		T221	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T55	14		T68	4		T141	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T152	13		T144	10		T245	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T21	7		T159	13		T194	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	1		T160	9		T52	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T49	1		T50	1		T151	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

auto[0]

4101

1

T12

1

T13

2

T14

1