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Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 1 1 T95 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 16 1 T255 1 T40 1 T192 13
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 5 1 T256 1 T264 4 - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 91 1 T51 3 T154 1 T170 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 199 1 T199 1 T151 3 T240 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 170 1 T12 5 T41 14 T224 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 167 1 T184 1 T145 1 T33 7
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 210 1 T69 16 T142 1 T152 14
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 174 1 T41 15 T52 2 T251 12
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 182 1 T68 7 T219 1 T152 17
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 187 1 T54 4 T135 11 T141 10
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 118 1 T137 1 T50 3 T194 13
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 220 1 T17 12 T55 12 T151 19
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 183 1 T13 4 T138 9 T68 5
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 216 1 T15 4 T160 10 T221 14
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 250 1 T5 1 T14 4 T31 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 143 1 T69 2 T143 13 T181 2
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 1611 1 T16 1 T18 2 T88 22
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 256 1 T150 1 T79 1 T219 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 241 1 T20 1 T21 8 T55 15
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 415 1 T19 13 T148 1 T140 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 13719 1 T3 20 T4 14 T5 1
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 6 1 T95 6 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 19 1 T192 15 T265 4 - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 10 1 T256 9 T264 1 - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 135 1 T51 1 T154 1 T227 12
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 146 1 T199 8 T151 9 T240 1
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 135 1 T139 11 T172 23 T228 4
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 141 1 T145 16 T33 3 T186 13
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 142 1 T69 20 T242 17 T236 1
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 124 1 T52 1 T186 2 T168 15
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 148 1 T68 2 T153 1 T266 2
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T54 3 T135 9 T187 17
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 120 1 T194 14 T189 4 T230 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 102 1 T55 8 T151 12 T180 17
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 176 1 T13 2 T68 8 T159 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 186 1 T160 8 T221 14 T153 10
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 207 1 T14 1 T136 12 T225 9
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 124 1 T69 1 T143 9 T181 1
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 985 1 T18 17 T229 14 T200 15
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 140 1 T150 9 T79 10 T161 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 159 1 T20 9 T55 11 T135 6
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 395 1 T148 10 T144 15 T225 7
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 100 1 T78 1 T79 1 T217 4



Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 7 41 85.42 7


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [maximum] * -- -- 2
[auto[1]] [maximum] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 201 1 T12 4 T51 3 T154 2
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 227 1 T199 9 T151 10 T145 17
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 174 1 T41 1 T224 1 T139 12
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 188 1 T184 1 T33 7 T251 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 189 1 T68 3 T69 21 T142 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 175 1 T41 1 T54 4 T135 10
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 178 1 T50 2 T219 1 T152 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 118 1 T245 16 T257 1 T171 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 144 1 T137 1 T221 8 T189 5
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 141 1 T17 1 T55 9 T151 13
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T31 1 T138 1 T68 9
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 223 1 T15 4 T69 2 T221 15
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 1416 1 T5 1 T13 4 T14 4
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 215 1 T79 11 T219 1 T143 10
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 162 1 T32 1 T184 1 T185 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 183 1 T150 10 T151 1 T161 3
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 183 1 T20 10 T21 1 T55 12
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 288 1 T19 1 T148 11 T144 17
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 30 1 T160 3 T231 2 T258 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 72 1 T140 1 T225 8 T168 9
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 13819 1 T3 20 T4 14 T5 1
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 132 1 T12 1 T51 1 T249 8
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 193 1 T151 2 T223 15 T171 9
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T41 13 T152 13 T267 13
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 168 1 T33 3 T251 9 T238 13
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 124 1 T68 6 T69 15 T242 3
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 176 1 T41 14 T54 3 T135 10
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 144 1 T50 1 T152 16 T194 12
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 94 1 T245 11 T257 10 T171 13
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 121 1 T221 1 T259 7 T268 8
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 191 1 T17 11 T55 11 T151 18
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 84 1 T138 8 T68 4 T162 8
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 186 1 T69 1 T221 13 T234 9
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 1364 1 T13 2 T14 1 T88 20
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 146 1 T143 12 T144 10 T178 10
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 125 1 T236 1 T263 11 T269 11
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 219 1 T151 9 T161 2 T194 15
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 156 1 T21 7 T55 14 T49 1
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 252 1 T19 12 T144 10 T34 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 18 1 T160 3 T258 4 T270 7
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 40 1 T245 10 T271 9 T272 6



Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [maximum] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [maximum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 7 1 T95 7 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 23 1 T255 1 T40 1 T192 16
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 13 1 T256 10 T264 3 - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 157 1 T51 3 T154 2 T170 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 175 1 T199 9 T151 10 T240 2
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 162 1 T12 4 T41 1 T224 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 176 1 T184 1 T145 17 T33 7
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 184 1 T69 21 T142 1 T152 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 153 1 T41 1 T52 2 T251 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 181 1 T68 3 T219 1 T152 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 175 1 T54 4 T135 10 T141 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 150 1 T137 1 T50 2 T194 15
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 128 1 T17 1 T55 9 T151 13
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 213 1 T13 4 T138 1 T68 9
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 225 1 T15 4 T160 9 T221 15
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 253 1 T5 1 T14 4 T31 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 151 1 T69 2 T143 10 T181 3
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 1325 1 T16 1 T18 19 T88 2
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 181 1 T150 10 T79 11 T219 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 214 1 T20 10 T21 1 T55 12
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 453 1 T19 1 T148 11 T140 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 13819 1 T3 20 T4 14 T5 1
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 12 1 T192 12 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 2 1 T264 2 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 69 1 T51 1 T172 3 T273 6
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 170 1 T151 2 T223 15 T171 9
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 143 1 T12 1 T41 13 T267 13
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 132 1 T33 3 T251 9 T40 14
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T69 15 T152 13 T242 3
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T41 14 T52 1 T251 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 149 1 T68 6 T152 16 T266 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 157 1 T54 3 T135 10 T141 9
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 88 1 T50 1 T194 12 T230 9
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 194 1 T17 11 T55 11 T151 18
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 146 1 T13 2 T138 8 T68 4
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T160 9 T221 13 T234 9
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 204 1 T14 1 T136 14 T240 12
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 116 1 T69 1 T143 12 T274 8
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 1271 1 T88 20 T254 14 T141 8
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 215 1 T151 9 T161 2 T144 10
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 186 1 T21 7 T55 14 T49 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 357 1 T19 12 T144 10 T34 1



Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cpclk_gate_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 18518 1 T3 20 T4 14 T5 2
auto[1] auto[0] 4101 1 T12 1 T13 2 T14 1

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