Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22619

1

T3

20

T4

14

T5

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19411

1

T3

20

T4

14

T5

2

auto[ADC_CTRL_FILTER_COND_OUT]

3208

1

T12

5

T13

6

T14

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16971

1

T3

20

T4

14

T5

2

auto[1]

5648

1

T13

6

T16

1

T18

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18774

1

T3

20

T4

14

T5

2

auto[1]

3845

1

T13

2

T14

1

T18

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	236	1			T41	15		T224	1		T160	6
values[1]	611	1			T17	12		T21	8		T138	9
values[2]	805	1			T14	5		T15	4		T159	24
values[3]	549	1			T68	9		T141	10		T234	10
values[4]	2869	1			T16	1		T18	19		T41	14
values[5]	719	1			T54	7		T79	11		T199	9
values[6]	703	1			T5	1		T31	1		T148	11
values[7]	623	1			T13	6		T135	7		T136	27
values[8]	759	1			T12	5		T20	10		T151	10
values[9]	926	1			T19	13		T55	20		T137	1
minimum	13819	1			T3	20		T4	14		T5	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	555	1			T138	9		T51	4		T141	9
values[1]	807	1			T14	5		T15	4		T17	12
values[2]	550	1			T41	14		T68	22		T141	10
values[3]	2963	1			T16	1		T18	19		T55	26
values[4]	772	1			T5	1		T31	1		T54	7
values[5]	490	1			T13	6		T148	11		T150	10
values[6]	809	1			T135	7		T136	27		T140	1
values[7]	708	1			T12	5		T20	10		T50	3
values[8]	875	1			T19	13		T41	15		T55	20
values[9]	115	1			T170	1		T227	13		T172	7
minimum	13975	1			T3	20		T4	14		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

4101

1

T12

1

T13

2

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T138	9		T51	3		T141	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T32	1		T251	10		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T159	14		T151	19		T242	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	4		T15	4		T17	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T41	14		T234	10		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T68	12		T141	10		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1582	1			T16	1		T18	2		T88	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T55	15		T135	11		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	1		T31	1		T54	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T79	1		T160	10		T152	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T153	9		T144	11		T255	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T13	4		T148	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T135	1		T136	15		T178	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T140	1		T222	1		T240	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T152	17		T223	2		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	5		T20	1		T50	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T19	13		T137	1		T68	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T41	15		T55	12		T224	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T227	1		T256	1		T275	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T170	1		T172	4		T276	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13734	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T21	8		T186	1		T245	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T51	1		T221	14		T181	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T231	1		T241	12		T190	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T159	10		T151	12		T242	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	1		T225	7		T227	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T153	1		T167	3		T235	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T68	10		T154	1		T225	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	914	1			T18	17		T229	14		T200	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T55	11		T135	9		T49	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T54	3		T69	20		T199	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T79	10		T160	8		T144	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T153	10		T144	7		T240	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T13	2		T148	10		T150	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T135	6		T136	12		T178	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T240	13		T194	14		T168	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T223	2		T189	4		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T20	9		T162	13		T277	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T160	2		T52	1		T178	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T55	8		T69	1		T151	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T227	12		T256	9		T278	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T172	3		T276	11		T279	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T78	1		T79	1		T217	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T186	13		T245	8		T276	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T160	4		T178	5		T222	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T41	15		T224	1		T280	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T138	9		T51	3		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T17	12		T21	8		T186	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T159	14		T151	19		T221	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	4		T15	4		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T234	10		T153	1		T163	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T68	7		T141	10		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1562	1			T16	1		T18	2		T41	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T55	15		T135	11		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T54	4		T199	1		T161	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T79	1		T160	10		T152	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T5	1		T31	1		T69	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T148	1		T150	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T135	1		T136	15		T153	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	4		T140	1		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T223	2		T220	11		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	5		T20	1		T151	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T19	13		T137	1		T68	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T55	12		T50	3		T69	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13719	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T160	2		T178	6		T227	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T281	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T51	1		T181	1		T230	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T186	13		T245	8		T231	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T159	10		T151	12		T221	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	1		T225	7		T227	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T153	1		T282	5		T172	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T68	2		T154	1		T225	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	868	1			T18	17		T229	14		T200	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T55	11		T135	9		T49	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T54	3		T199	8		T161	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T79	10		T160	8		T144	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T69	20		T144	7		T240	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T148	10		T150	9		T144	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T135	6		T136	12		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	2		T153	1		T240	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T223	2		T220	9		T156	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T20	9		T162	13		T236	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T52	1		T180	17		T162	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T55	8		T69	1		T151	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T138	1		T51	3		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T32	1		T251	1		T231	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T159	11		T151	13		T242	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	4		T15	4		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T41	1		T234	1		T153	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T68	12		T141	1		T154	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T16	1		T18	19		T88	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T55	12		T135	10		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	1		T31	1		T54	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T79	11		T160	9		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T153	11		T144	8		T255	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T13	4		T148	11		T150	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T135	7		T136	13		T178	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T140	1		T222	1		T240	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T152	1		T223	3		T189	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	4		T20	10		T50	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T19	1		T137	1		T68	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T41	1		T55	9		T224	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T227	13		T256	10		T275	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T170	1		T172	4		T276	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13833	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T21	1		T186	14		T245	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T138	8		T51	1		T141	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T251	9		T238	8		T163	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T159	13		T151	18		T242	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T14	1		T17	11		T257	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T41	13		T234	9		T235	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T68	10		T141	9		T33	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T88	20		T254	14		T197	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T55	14		T135	10		T49	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T54	3		T69	15		T221	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T160	9		T152	13		T144	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T153	8		T144	10		T194	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T13	2		T279	3		T175	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T136	14		T178	6		T187	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T240	12		T194	12		T236	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T152	16		T223	1		T37	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	1		T50	1		T151	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T19	12		T68	5		T160	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T41	14		T55	11		T69	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T278	6		T283	5		T284	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T172	3		T279	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T99	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T21	7		T245	10		T191	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T160	3		T178	7		T222	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T41	1		T224	1		T280	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T138	1		T51	3		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T17	1		T21	1		T186	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T159	11		T151	13		T221	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	4		T15	4		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T234	1		T153	2		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T68	3		T141	1		T154	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T16	1		T18	19		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T55	12		T135	10		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T54	4		T199	9		T161	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T79	11		T160	9		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	1		T31	1		T69	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T148	11		T150	10		T144	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T135	7		T136	13		T153	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	4		T140	1		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T223	3		T220	10		T156	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	4		T20	10		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T19	1		T137	1		T68	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T55	9		T50	2		T69	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13819	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T160	3		T178	4		T285	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T41	14		T281	12		T110	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T138	8		T51	1		T141	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T17	11		T21	7		T245	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T159	13		T151	18		T221	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T14	1		T251	9		T257	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T234	9		T163	14		T282	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T68	6		T141	9		T245	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T41	13		T88	20		T254	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T55	14		T135	10		T49	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T54	3		T161	2		T221	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T160	9		T152	13		T144	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T69	15		T144	10		T194	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T223	12		T241	14		T273	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T136	14		T153	8		T178	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T13	2		T240	12		T194	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T223	1		T220	10		T268	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	1		T151	9		T162	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T19	12		T68	5		T52	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T55	11		T50	1		T69	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

auto[0]

4101

1

T12

1

T13

2

T14

1