Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22619

1

T3

20

T4

14

T5

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19212

1

T3

20

T4

14

T5

2

auto[ADC_CTRL_FILTER_COND_OUT]

3407

1

T13

6

T17

12

T19

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16883

1

T3

20

T4

14

T5

1

auto[1]

5736

1

T5

1

T15

4

T16

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18774

1

T3

20

T4

14

T5

2

auto[1]

3845

1

T13

2

T14

1

T18

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	290	1			T199	9		T234	10		T152	17
values[1]	768	1			T19	13		T41	15		T55	20
values[2]	2947	1			T14	5		T16	1		T18	19
values[3]	715	1			T12	5		T20	10		T137	1
values[4]	595	1			T17	12		T68	9		T161	5
values[5]	637	1			T13	6		T54	7		T55	26
values[6]	475	1			T5	1		T68	6		T143	22
values[7]	676	1			T135	7		T50	3		T68	13
values[8]	759	1			T21	8		T41	14		T135	20
values[9]	938	1			T15	4		T31	1		T159	24
minimum	13819	1			T3	20		T4	14		T5	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	692	1			T41	15		T55	20		T137	1
values[1]	3068	1			T12	5		T14	5		T16	1
values[2]	625	1			T137	1		T138	9		T150	10
values[3]	613	1			T17	12		T68	9		T161	5
values[4]	573	1			T13	6		T54	7		T55	26
values[5]	558	1			T5	1		T135	7		T50	3
values[6]	676	1			T21	8		T135	20		T68	13
values[7]	804	1			T41	14		T159	24		T219	1
values[8]	898	1			T15	4		T31	1		T199	9
values[9]	123	1			T234	10		T178	11		T236	4
minimum	13989	1			T3	20		T4	14		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

4101

1

T12

1

T13

2

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T55	12		T49	3		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T41	15		T137	1		T52	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1627	1			T12	5		T14	4		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T140	1		T141	9		T69	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T137	1		T138	9		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T136	15		T180	17		T286	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T68	7		T142	1		T181	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T17	12		T161	3		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T54	4		T55	15		T221	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	4		T153	1		T168	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	1		T50	3		T68	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T135	1		T144	1		T187	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T21	8		T151	19		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T135	11		T68	5		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T41	14		T141	10		T151	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T159	14		T219	1		T154	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T15	4		T31	1		T221	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T199	1		T152	17		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T234	10		T178	5		T163	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T236	3		T261	3		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13755	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T19	13		T35	2		T287	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T55	8		T49	1		T148	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T52	1		T144	7		T186	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T14	1		T18	17		T20	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T69	20		T189	13		T220	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T150	9		T51	1		T288	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T136	12		T180	17		T263	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T68	2		T181	1		T154	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T161	2		T185	9		T225	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T54	3		T55	11		T221	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	2		T153	1		T168	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T151	9		T143	9		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T135	6		T144	1		T187	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T151	12		T240	1		T189	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T135	9		T68	8		T153	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T160	10		T144	14		T145	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T159	10		T154	14		T230	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T221	14		T154	1		T223	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T199	8		T225	16		T189	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T178	6		T289	1		T167	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T236	1		T261	7		T256	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T78	1		T79	1		T217	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T290	3		T273	9		T291	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T234	10		T223	2		T40	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T199	1		T152	17		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T55	12		T49	3		T178	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T19	13		T41	15		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1621	1			T14	4		T16	1		T18	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T140	1		T141	9		T69	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	5		T20	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T136	15		T180	17		T255	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T68	7		T142	1		T181	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T17	12		T161	3		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T54	4		T55	15		T151	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	4		T153	1		T185	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	1		T68	6		T143	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T144	1		T251	12		T162	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T50	3		T224	1		T151	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T135	1		T68	5		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T21	8		T41	14		T160	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T135	11		T219	1		T154	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T15	4		T31	1		T141	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T159	14		T184	1		T225	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13719	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T223	2		T172	9		T289	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T199	8		T261	7		T237	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T55	8		T49	1		T178	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T144	7		T186	13		T194	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T14	1		T18	17		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T69	20		T52	1		T189	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T20	9		T150	9		T51	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T136	12		T180	17		T220	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T68	2		T181	1		T154	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T161	2		T241	12		T292	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T54	3		T55	11		T151	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	2		T153	1		T185	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T143	9		T168	15		T223	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T144	1		T162	13		T232	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T151	12		T240	1		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T135	6		T68	8		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T160	8		T144	14		T145	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T135	9		T154	14		T223	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T160	2		T221	14		T178	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T159	10		T225	16		T189	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T55	9		T49	3		T148	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T41	1		T137	1		T52	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T12	4		T14	4		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T140	1		T141	1		T69	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T137	1		T138	1		T150	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T136	13		T180	18		T286	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T68	3		T142	1		T181	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T17	1		T161	3		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T54	4		T55	12		T221	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	4		T153	2		T168	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	1		T50	2		T68	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T135	7		T144	2		T187	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T21	1		T151	13		T240	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T135	10		T68	9		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T41	1		T141	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T159	11		T219	1		T154	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T15	4		T31	1		T221	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T199	9		T152	1		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T234	1		T178	7		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T236	3		T261	8		T256	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13877	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T19	1		T35	2		T287	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T55	11		T49	1		T69	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T41	14		T52	1		T144	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T12	1		T14	1		T88	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T141	8		T69	15		T163	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T138	8		T51	1		T169	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T136	14		T180	16		T238	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T68	6		T162	8		T236	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T17	11		T161	2		T241	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T54	3		T55	14		T221	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T13	2		T245	21		T237	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T50	1		T68	5		T151	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T187	16		T251	11		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T21	7		T151	18		T171	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T135	10		T68	4		T153	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T41	13		T141	9		T151	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T159	13		T154	14		T293	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T221	13		T223	1		T172	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T152	16		T230	9		T267	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T234	9		T178	4		T163	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T236	1		T261	2		T272	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T239	8		T294	7		T295	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T19	12		T290	2		T273	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T234	1		T223	3		T40	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T199	9		T152	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T55	9		T49	3		T178	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T19	1		T41	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T14	4		T16	1		T18	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T140	1		T141	1		T69	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	4		T20	10		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T136	13		T180	18		T255	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T68	3		T142	1		T181	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T17	1		T161	3		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T54	4		T55	12		T151	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	4		T153	2		T185	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	1		T68	1		T143	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T144	2		T251	1		T162	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T50	2		T224	1		T151	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T135	7		T68	9		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T21	1		T41	1		T160	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T135	10		T219	1		T154	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T15	4		T31	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T159	11		T184	1		T225	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13819	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T234	9		T223	1		T172	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T152	16		T261	2		T237	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T55	11		T49	1		T178	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T19	12		T41	14		T144	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T14	1		T88	20		T254	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T141	8		T69	15		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	1		T138	8		T51	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T136	14		T180	16		T220	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T68	6		T162	8		T236	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T17	11		T161	2		T238	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T54	3		T55	14		T151	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	2		T245	21		T296	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T68	5		T143	12		T152	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T251	11		T162	13		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T50	1		T151	18		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T68	4		T153	8		T187	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T21	7		T41	13		T160	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T135	10		T154	14		T223	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T141	9		T151	9		T160	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T159	13		T293	11		T236	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

auto[0]

4101

1

T12

1

T13

2

T14

1