Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22619

1

T3

20

T4

14

T5

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19526

1

T3

20

T4

14

T5

1

auto[ADC_CTRL_FILTER_COND_OUT]

3093

1

T5

1

T31

1

T19

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16921

1

T3

20

T4

14

T5

2

auto[1]

5698

1

T13

6

T16

1

T18

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18774

1

T3

20

T4

14

T5

2

auto[1]

3845

1

T13

2

T14

1

T18

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T222	1		T297	1		-	-
values[0]	70	1			T227	13		T298	1		T299	21
values[1]	585	1			T224	1		T141	9		T151	31
values[2]	581	1			T55	20		T135	27		T154	4
values[3]	737	1			T13	6		T20	10		T150	10
values[4]	632	1			T41	15		T138	9		T153	19
values[5]	2942	1			T16	1		T18	19		T54	7
values[6]	611	1			T5	1		T19	13		T41	14
values[7]	731	1			T12	5		T15	4		T17	12
values[8]	850	1			T21	8		T148	11		T159	24
values[9]	1059	1			T14	5		T31	1		T137	2
minimum	13819	1			T3	20		T4	14		T5	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	769	1			T224	1		T141	9		T151	31
values[1]	712	1			T13	6		T20	10		T55	20
values[2]	631	1			T41	15		T138	9		T150	10
values[3]	2976	1			T16	1		T18	19		T88	22
values[4]	680	1			T5	1		T41	14		T54	7
values[5]	571	1			T12	5		T17	12		T19	13
values[6]	775	1			T15	4		T55	26		T68	13
values[7]	827	1			T21	8		T148	11		T159	24
values[8]	690	1			T14	5		T31	1		T137	2
values[9]	169	1			T69	3		T142	1		T186	14
minimum	13819	1			T3	20		T4	14		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

4101

1

T12

1

T13

2

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T151	19		T160	4		T255	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T224	1		T141	9		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	4		T135	1		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T20	1		T55	12		T135	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T51	3		T219	1		T144	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T41	15		T138	9		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1623	1			T16	1		T18	2		T88	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T162	9		T223	13		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T41	14		T68	6		T153	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	1		T54	4		T221	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T12	5		T17	12		T68	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T19	13		T225	1		T236	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T15	4		T69	16		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T55	15		T68	5		T141	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T52	2		T152	14		T178	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T21	8		T148	1		T159	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T14	4		T137	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T31	1		T137	1		T49	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T69	2		T186	1		T190	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T142	1		T61	1		T156	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13719	1			T3	20		T4	14		T5	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T151	12		T160	2		T230	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T227	21		T300	1		T271	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	2		T135	6		T172	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T20	9		T55	8		T135	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T51	1		T144	15		T154	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T150	9		T185	9		T194	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T18	17		T229	14		T200	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T162	9		T223	12		T195	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T153	10		T240	13		T231	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T54	3		T221	7		T143	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T68	2		T79	10		T136	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T225	9		T236	2		T271	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T69	20		T153	1		T144	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T55	11		T68	8		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T52	1		T178	6		T168	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T148	10		T159	10		T151	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	1		T160	8		T153	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T49	1		T139	11		T199	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T69	1		T186	13		T190	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T156	11		T301	1		T95	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T297	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T222	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T298	1		T302	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T227	1		T299	12		T303	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T151	19		T160	4		T255	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T224	1		T141	9		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T135	1		T163	15		T40	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T55	12		T135	11		T154	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T13	4		T51	3		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T20	1		T150	1		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T153	9		T144	11		T181	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T41	15		T138	9		T251	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1619	1			T16	1		T18	2		T88	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T54	4		T221	2		T162	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T41	14		T68	13		T79	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	1		T19	13		T143	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	5		T15	4		T17	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T55	15		T68	5		T257	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T69	16		T152	14		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T21	8		T148	1		T159	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T14	4		T137	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T31	1		T137	1		T49	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13719	1			T3	20		T4	14		T5	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T302	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T227	12		T299	9		T303	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T151	12		T160	2		T230	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T227	9		T300	1		T304	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T135	6		T261	7		T237	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T55	8		T135	9		T154	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	2		T51	1		T144	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T20	9		T150	9		T185	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T153	10		T144	14		T181	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T194	14		T241	11		T195	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	957	1			T18	17		T229	14		T200	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T54	3		T221	7		T162	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T68	2		T79	10		T231	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T143	9		T225	9		T242	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T136	12		T221	14		T178	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T55	11		T68	8		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T69	20		T153	1		T144	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T148	10		T159	10		T225	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T14	1		T69	1		T160	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T49	1		T139	11		T199	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T151	13		T160	3		T255	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T224	1		T141	1		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	4		T135	7		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T20	10		T55	9		T135	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T51	3		T219	1		T144	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T41	1		T138	1		T150	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T16	1		T18	19		T88	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T162	10		T223	13		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T41	1		T68	1		T153	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	1		T54	4		T221	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	4		T17	1		T68	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T19	1		T225	10		T236	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	4		T69	21		T153	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T55	12		T68	9		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T52	2		T152	1		T178	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T21	1		T148	11		T159	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	4		T137	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T31	1		T137	1		T49	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T69	2		T186	14		T190	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T142	1		T61	1		T156	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13819	1			T3	20		T4	14		T5	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T151	18		T160	3		T238	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T141	8		T171	6		T305	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	2		T163	14		T40	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T55	11		T135	10		T33	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T51	1		T144	10		T154	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T41	14		T138	8		T251	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T88	20		T254	14		T197	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T162	8		T223	12		T249	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T41	13		T68	5		T153	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T54	3		T221	1		T143	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	1		T17	11		T68	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T19	12		T236	1		T166	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T69	15		T144	10		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T55	14		T68	4		T141	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T52	1		T152	13		T178	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T21	7		T159	13		T151	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	1		T160	9		T172	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T49	1		T50	1		T151	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T69	1		T306	7		T175	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T307	13		T308	6		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T297	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T222	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T298	1		T302	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T227	13		T299	10		T303	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T151	13		T160	3		T255	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T224	1		T141	1		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T135	7		T163	1		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T55	9		T135	10		T154	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T13	4		T51	3		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T20	10		T150	10		T185	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T153	11		T144	15		T181	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T41	1		T138	1		T251	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T16	1		T18	19		T88	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T54	4		T221	8		T162	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T41	1		T68	4		T79	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	1		T19	1		T143	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T12	4		T15	4		T17	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T55	12		T68	9		T257	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T69	21		T152	1		T153	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T21	1		T148	11		T159	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T14	4		T137	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T31	1		T137	1		T49	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13819	1			T3	20		T4	14		T5	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T302	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T299	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T151	18		T160	3		T238	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T141	8		T304	8		T239	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T163	14		T40	14		T261	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T55	11		T135	10		T33	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	2		T51	1		T180	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T251	11		T162	13		T188	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T153	8		T144	10		T187	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T41	14		T138	8		T251	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T88	20		T254	14		T197	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T54	3		T221	1		T162	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T41	13		T68	11		T152	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T19	12		T143	12		T242	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	1		T17	11		T136	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T55	14		T68	4		T257	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T69	15		T152	13		T144	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T21	7		T159	13		T141	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T14	1		T69	1		T160	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T49	1		T50	1		T151	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

auto[0]

4101

1

T12

1

T13

2

T14

1