Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22619

1

T3

20

T4

14

T5

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19466

1

T3

20

T4

14

T5

1

auto[ADC_CTRL_FILTER_COND_OUT]

3153

1

T5

1

T12

5

T13

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16548

1

T3

20

T4

14

T5

1

auto[1]

6071

1

T5

1

T12

5

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18774

1

T3

20

T4

14

T5

2

auto[1]

3845

1

T13

2

T14

1

T18

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	586	1			T13	1		T14	3		T57	1
values[0]	20	1			T20	10		T37	6		T94	4
values[1]	559	1			T15	4		T54	7		T219	1
values[2]	2934	1			T16	1		T18	19		T21	8
values[3]	545	1			T55	26		T141	9		T161	5
values[4]	898	1			T55	20		T224	1		T69	36
values[5]	650	1			T5	1		T12	5		T137	1
values[6]	699	1			T135	20		T138	9		T150	10
values[7]	644	1			T19	13		T68	6		T159	24
values[8]	773	1			T14	5		T17	12		T49	4
values[9]	852	1			T13	6		T31	1		T41	15
minimum	13459	1			T3	20		T4	14		T5	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	535	1			T20	10		T21	8		T41	14
values[1]	2968	1			T16	1		T18	19		T88	22
values[2]	605	1			T55	26		T224	1		T141	9
values[3]	733	1			T12	5		T137	1		T69	36
values[4]	744	1			T5	1		T55	20		T135	20
values[5]	716	1			T19	13		T138	9		T150	10
values[6]	627	1			T14	5		T68	6		T151	41
values[7]	775	1			T17	12		T49	4		T148	11
values[8]	810	1			T13	6		T31	1		T41	15
values[9]	92	1			T241	26		T166	13		T312	5
minimum	14014	1			T3	20		T4	14		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

4101

1

T12

1

T13

2

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T20	1		T21	8		T41	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T219	2		T236	3		T163	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1651	1			T16	1		T18	2		T88	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T137	1		T79	1		T141	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T141	9		T32	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T55	15		T224	1		T234	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T160	10		T52	2		T154	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T12	5		T137	1		T69	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T55	12		T135	11		T221	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	1		T185	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T19	13		T222	1		T240	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T138	9		T150	1		T159	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T151	29		T178	5		T171	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	4		T68	6		T160	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T17	12		T180	17		T225	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T49	3		T148	1		T50	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T31	1		T139	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T13	4		T41	15		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T241	15		T166	13		T312	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13758	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T245	11		T313	1		T310	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T20	9		T151	9		T33	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T236	2		T156	11		T285	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T18	17		T229	14		T136	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T79	10		T153	10		T194	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T153	1		T189	8		T195	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T55	11		T186	13		T39	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T160	8		T52	1		T154	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T69	20		T154	1		T240	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T55	8		T135	9		T221	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T195	7		T172	9		T266	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T240	1		T194	14		T300	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T150	9		T159	10		T51	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T151	12		T178	6		T282	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	1		T160	2		T144	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T180	17		T225	7		T242	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	1		T148	10		T241	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T139	11		T69	1		T199	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T13	2		T135	6		T68	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T241	11		T311	9		T314	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T54	3		T78	1		T79	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T245	8		T315	14		T316	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	426	1			T13	1		T14	3		T57	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T143	13		T245	12		T317	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T20	1		T37	5		T94	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	4		T54	4		T181	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T219	1		T245	11		T163	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1644	1			T16	1		T18	2		T21	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T137	1		T79	1		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T141	9		T161	3		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T55	15		T234	10		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T55	12		T160	10		T52	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T224	1		T69	16		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T152	14		T186	1		T223	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	1		T12	5		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T135	11		T221	14		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T138	9		T150	1		T51	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T19	13		T151	10		T178	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T68	6		T159	14		T160	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T17	12		T151	19		T225	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	4		T49	3		T50	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T31	1		T139	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T13	4		T41	15		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13359	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T199	8		T225	9		T241	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T143	9		T245	15		T317	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T20	9		T37	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T54	3		T181	1		T189	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T245	8		T285	9		T315	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T18	17		T229	14		T136	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T79	10		T153	10		T194	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T161	2		T153	1		T189	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T55	11		T39	3		T318	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T55	8		T160	8		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T69	20		T154	1		T186	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T186	2		T223	12		T261	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T250	11		T195	7		T172	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T135	9		T221	14		T145	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T150	9		T51	1		T185	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T178	6		T282	5		T260	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T159	10		T160	2		T144	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T151	12		T225	7		T223	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	1		T49	1		T241	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T139	11		T69	1		T221	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	2		T135	6		T148	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T20	10		T21	1		T41	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T219	2		T236	4		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T16	1		T18	19		T88	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T137	1		T79	11		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T141	1		T32	1		T153	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T55	12		T224	1		T234	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T160	9		T52	2		T154	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	4		T137	1		T69	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T55	9		T135	10		T221	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	1		T185	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T19	1		T222	1		T240	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T138	1		T150	10		T159	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T151	14		T178	7		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	4		T68	1		T160	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T17	1		T180	18		T225	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T49	3		T148	11		T50	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T31	1		T139	12		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T13	4		T41	1		T135	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T241	12		T166	1		T312	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13885	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T245	9		T313	1		T310	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T21	7		T41	13		T151	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T236	1		T163	13		T285	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T88	20		T136	14		T254	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T141	9		T152	16		T153	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T141	8		T249	8		T172	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T55	14		T234	9		T188	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T160	9		T52	1		T154	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	1		T69	15		T240	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T55	11		T135	10		T221	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T171	6		T172	9		T274	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T19	12		T194	12		T267	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T138	8		T159	13		T51	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T151	27		T178	4		T171	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	1		T68	5		T160	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T17	11		T180	16		T242	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T49	1		T50	1		T188	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T69	1		T221	1		T178	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T13	2		T41	14		T68	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T241	14		T166	12		T312	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T54	3		T107	7		T319	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T245	10		T315	12		T244	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	411	1			T13	1		T14	3		T57	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T143	10		T245	16		T317	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T20	10		T37	4		T94	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	4		T54	4		T181	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T219	1		T245	9		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T16	1		T18	19		T21	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T137	1		T79	11		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T141	1		T161	3		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T55	12		T234	1		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T55	9		T160	9		T52	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T224	1		T69	21		T154	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T152	1		T186	3		T223	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	1		T12	4		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T135	10		T221	15		T145	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T138	1		T150	10		T51	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T19	1		T151	1		T178	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T68	1		T159	11		T160	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T17	1		T151	13		T225	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	4		T49	3		T50	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T31	1		T139	12		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T13	4		T41	1		T135	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13459	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T241	14		T166	11		T312	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T143	12		T245	11		T233	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T37	2		T94	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T54	3		T274	8		T289	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T245	10		T163	13		T285	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T21	7		T41	13		T88	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T141	9		T152	16		T153	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T141	8		T161	2		T172	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T55	14		T234	9		T188	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T55	11		T160	9		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T69	15		T240	12		T162	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T152	13		T223	12		T40	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T171	6		T163	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T135	10		T221	13		T194	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T138	8		T51	1		T187	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T19	12		T151	9		T178	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T68	5		T159	13		T160	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T17	11		T151	18		T223	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	1		T49	1		T50	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T69	1		T221	1		T178	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	2		T41	14		T68	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

auto[0]

4101

1

T12

1

T13

2

T14

1