Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22619

1

T3

20

T4

14

T5

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19762

1

T3

20

T4

14

T5

2

auto[ADC_CTRL_FILTER_COND_OUT]

2857

1

T12

5

T14

5

T31

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16574

1

T3

20

T4

14

T5

1

auto[1]

6045

1

T5

1

T12

5

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18774

1

T3

20

T4

14

T5

2

auto[1]

3845

1

T13

2

T14

1

T18

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	391	1			T13	1		T14	3		T57	1
values[0]	21	1			T20	10		T37	6		T192	1
values[1]	508	1			T15	4		T54	7		T219	1
values[2]	2956	1			T16	1		T18	19		T21	8
values[3]	580	1			T55	26		T136	27		T141	9
values[4]	835	1			T55	20		T224	1		T69	36
values[5]	763	1			T5	1		T12	5		T137	1
values[6]	723	1			T135	20		T138	9		T150	10
values[7]	540	1			T19	13		T68	6		T160	6
values[8]	791	1			T14	5		T17	12		T49	4
values[9]	1052	1			T13	6		T31	1		T41	15
minimum	13459	1			T3	20		T4	14		T5	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	673	1			T15	4		T20	10		T21	8
values[1]	2998	1			T16	1		T18	19		T88	22
values[2]	644	1			T55	26		T224	1		T141	9
values[3]	694	1			T137	1		T69	36		T52	3
values[4]	756	1			T5	1		T12	5		T55	20
values[5]	738	1			T19	13		T138	9		T150	10
values[6]	599	1			T14	5		T68	6		T51	4
values[7]	771	1			T17	12		T49	4		T148	11
values[8]	694	1			T13	6		T31	1		T41	15
values[9]	217	1			T135	7		T139	12		T230	17
minimum	13835	1			T3	20		T4	14		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

4101

1

T12

1

T13

2

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T15	4		T20	1		T21	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T181	2		T286	1		T245	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1654	1			T16	1		T18	2		T88	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T137	1		T79	1		T141	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T55	15		T160	10		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T224	1		T141	9		T234	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T69	16		T52	2		T154	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T137	1		T186	1		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T5	1		T55	12		T135	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	5		T185	1		T187	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T19	13		T151	10		T221	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T138	9		T150	1		T159	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T68	6		T151	19		T178	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	4		T51	3		T160	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T180	17		T225	1		T222	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T17	12		T49	3		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	4		T41	15		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T31	1		T68	12		T221	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T135	1		T139	1		T166	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T230	10		T241	15		T220	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13721	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T192	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T20	9		T54	3		T151	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T181	1		T245	8		T236	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T18	17		T229	14		T136	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T79	10		T153	11		T194	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T55	11		T160	8		T153	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T154	1		T271	14		T304	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T69	20		T52	1		T154	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T186	2		T168	8		T231	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T55	8		T135	9		T145	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T187	17		T195	7		T285	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T221	14		T194	14		T228	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T150	9		T159	10		T185	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T151	12		T178	6		T232	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T14	1		T51	1		T160	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T180	17		T225	7		T162	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T49	1		T148	10		T242	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T13	2		T69	1		T199	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T68	10		T221	7		T143	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T135	6		T139	11		T311	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T230	7		T241	11		T220	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T78	1		T79	1		T217	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T13	1		T14	3		T57	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T230	10		T213	1		T308	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T20	1		T37	5		T94	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T192	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	4		T54	4		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T181	2		T286	1		T245	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1637	1			T16	1		T18	2		T21	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T137	1		T79	1		T141	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T55	15		T136	15		T161	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T141	9		T234	10		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T55	12		T69	16		T160	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T224	1		T154	1		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T5	1		T152	14		T154	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	5		T137	1		T185	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T135	11		T151	10		T221	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T138	9		T150	1		T159	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T19	13		T68	6		T178	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T160	4		T144	22		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T151	19		T225	1		T222	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T14	4		T17	12		T49	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T13	4		T41	15		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T31	1		T148	1		T68	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13359	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T230	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T20	9		T37	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T54	3		T189	13		T237	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T181	1		T245	8		T277	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T18	17		T229	14		T200	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T79	10		T153	11		T194	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T55	11		T136	12		T161	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T168	8		T39	3		T296	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T55	8		T69	20		T160	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T154	1		T231	1		T195	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T154	14		T145	16		T223	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T187	17		T186	2		T250	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T135	9		T221	14		T194	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T150	9		T159	10		T51	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T178	6		T232	10		T190	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T160	2		T144	21		T154	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T151	12		T225	7		T282	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	1		T49	1		T223	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	2		T135	6		T139	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T148	10		T68	10		T221	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T15	4		T20	10		T21	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T181	3		T286	1		T245	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T16	1		T18	19		T88	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T137	1		T79	11		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T55	12		T160	9		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T224	1		T141	1		T234	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T69	21		T52	2		T154	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T137	1		T186	3		T168	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T5	1		T55	9		T135	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T12	4		T185	1		T187	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T19	1		T151	1		T221	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T138	1		T150	10		T159	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T68	1		T151	13		T178	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T14	4		T51	3		T160	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T180	18		T225	8		T222	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T17	1		T49	3		T148	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	4		T41	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T31	1		T68	12		T221	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T135	7		T139	12		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T230	8		T241	12		T220	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13834	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T192	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T21	7		T41	13		T54	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T245	10		T236	1		T289	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T88	20		T136	14		T254	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T141	9		T152	16		T153	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T55	14		T160	9		T188	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T141	8		T234	9		T320	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T69	15		T52	1		T154	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T238	13		T293	11		T250	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T55	11		T135	10		T152	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T12	1		T187	16		T171	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T19	12		T151	9		T221	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T138	8		T159	13		T238	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T68	5		T151	18		T178	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	1		T51	1		T160	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T180	16		T162	8		T246	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T17	11		T49	1		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	2		T41	14		T69	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T68	10		T221	1		T143	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T166	12		T244	19		T321	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T230	9		T241	14		T220	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T13	1		T14	3		T57	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T230	8		T213	1		T308	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T20	10		T37	4		T94	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T192	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T15	4		T54	4		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T181	3		T286	1		T245	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T16	1		T18	19		T21	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T137	1		T79	11		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T55	12		T136	13		T161	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T141	1		T234	1		T168	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T55	9		T69	21		T160	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T224	1		T154	2		T231	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T5	1		T152	1		T154	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	4		T137	1		T185	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T135	10		T151	1		T221	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T138	1		T150	10		T159	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T19	1		T68	1		T178	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T160	3		T144	23		T154	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T151	13		T225	8		T222	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T14	4		T17	1		T49	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T13	4		T41	1		T135	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T31	1		T148	11		T68	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13459	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T230	9		T308	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T37	2		T94	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T54	3		T274	8		T258	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T245	10		T163	13		T289	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T21	7		T41	13		T88	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T141	9		T152	16		T153	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T55	14		T136	14		T161	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T141	8		T234	9		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T55	11		T69	15		T160	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T238	13		T293	11		T237	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T152	13		T154	14		T223	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	1		T187	16		T171	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T135	10		T151	9		T221	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T138	8		T159	13		T51	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T19	12		T68	5		T178	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T160	3		T144	20		T251	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T151	18		T171	9		T282	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	1		T17	11		T49	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T13	2		T41	14		T69	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T68	10		T221	1		T143	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

auto[0]

4101

1

T12

1

T13

2

T14

1