Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22619

1

T3

20

T4

14

T5

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19195

1

T3

20

T4

14

T5

2

auto[ADC_CTRL_FILTER_COND_OUT]

3424

1

T14

5

T15

4

T17

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16928

1

T3

20

T4

14

T5

1

auto[1]

5691

1

T5

1

T16

1

T17

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18774

1

T3

20

T4

14

T5

2

auto[1]

3845

1

T13

2

T14

1

T18

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T153	2		-	-		-	-
values[0]	38	1			T15	4		T267	14		T263	9
values[1]	590	1			T135	7		T68	22		T224	1
values[2]	574	1			T159	24		T79	11		T141	9
values[3]	603	1			T12	5		T219	1		T151	12
values[4]	545	1			T138	9		T150	10		T219	1
values[5]	2713	1			T13	6		T16	1		T18	19
values[6]	725	1			T5	1		T14	5		T31	1
values[7]	844	1			T41	14		T54	7		T55	46
values[8]	700	1			T68	6		T221	28		T222	1
values[9]	1466	1			T19	13		T20	10		T21	8
minimum	13819	1			T3	20		T4	14		T5	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	675	1			T15	4		T135	7		T68	22
values[1]	665	1			T12	5		T159	24		T79	11
values[2]	465	1			T138	9		T150	10		T219	1
values[3]	2856	1			T16	1		T18	19		T88	22
values[4]	473	1			T5	1		T13	6		T31	1
values[5]	905	1			T14	5		T54	7		T55	20
values[6]	762	1			T17	12		T41	14		T55	26
values[7]	648	1			T21	8		T68	6		T141	10
values[8]	1093	1			T19	13		T20	10		T135	20
values[9]	220	1			T51	4		T152	17		T153	2
minimum	13857	1			T3	20		T4	14		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

4101

1

T12

1

T13

2

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T135	1		T68	7		T224	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T15	4		T68	5		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	5		T79	1		T238	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T159	14		T219	1		T52	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T138	9		T150	1		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T144	1		T223	16		T171	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1643	1			T16	1		T18	2		T88	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T221	2		T153	10		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	1		T13	4		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T49	3		T50	3		T236	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T222	2		T169	5		T249	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T14	4		T54	4		T55	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T41	14		T55	15		T69	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T17	12		T148	1		T160	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T21	8		T141	10		T151	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T68	6		T221	14		T225	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T19	13		T20	1		T135	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T137	1		T199	1		T161	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T194	13		T168	2		T282	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T51	3		T152	17		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13730	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T255	1		T263	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T135	6		T68	2		T136	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T68	8		T186	13		T240	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T79	10		T322	2		T318	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T159	10		T52	1		T187	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T150	9		T69	1		T151	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T144	1		T223	13		T156	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T18	17		T229	14		T200	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T221	7		T153	11		T232	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T13	2		T154	1		T189	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T49	1		T236	2		T190	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T266	2		T290	9		T269	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T14	1		T54	3		T55	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T55	11		T69	20		T178	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T148	10		T160	8		T186	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T151	12		T144	7		T240	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T221	14		T225	9		T223	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T20	9		T135	9		T139	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T199	8		T161	2		T160	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T194	14		T168	23		T282	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T51	1		T153	1		T185	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T78	1		T79	1		T217	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T263	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T153	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T94	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T15	4		T267	14		T263	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T135	1		T68	7		T224	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T68	5		T140	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T79	1		T141	9		T69	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T159	14		T52	2		T187	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	5		T151	3		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T219	1		T32	1		T152	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T138	9		T150	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T221	2		T153	10		T185	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1620	1			T13	4		T16	1		T18	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T49	3		T50	3		T236	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	1		T31	1		T41	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	4		T17	12		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T41	14		T55	15		T234	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T54	4		T55	12		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T222	1		T240	1		T162	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T68	6		T221	14		T238	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T19	13		T20	1		T21	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T137	1		T51	3		T199	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13719	1			T3	20		T4	14		T5	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T153	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T135	6		T68	2		T136	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T68	8		T186	13		T260	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T79	10		T69	1		T178	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T159	10		T52	1		T187	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T151	9		T225	7		T318	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T144	1		T223	13		T250	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T150	9		T154	14		T189	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T221	7		T153	11		T232	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	903	1			T13	2		T18	17		T229	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T49	1		T236	2		T190	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T69	20		T266	2		T290	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	1		T245	15		T288	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T55	11		T178	6		T145	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T54	3		T55	8		T148	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T240	1		T162	9		T220	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T221	14		T236	1		T156	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T20	9		T135	9		T139	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	386	1			T51	1		T199	8		T161	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T78	1		T79	1		T217	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T135	7		T68	3		T224	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	4		T68	9		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T12	4		T79	11		T238	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T159	11		T219	1		T52	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T138	1		T150	10		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T144	2		T223	14		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T16	1		T18	19		T88	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T221	8		T153	13		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T5	1		T13	4		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T49	3		T50	2		T236	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T222	2		T169	1		T249	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T14	4		T54	4		T55	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T41	1		T55	12		T69	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T17	1		T148	11		T160	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T21	1		T141	1		T151	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T68	1		T221	15		T225	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T19	1		T20	10		T135	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T137	1		T199	9		T161	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T194	15		T168	25		T282	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T51	3		T152	1		T153	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13823	1			T3	20		T4	14		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T255	1		T263	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T68	6		T136	14		T141	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T68	4		T240	12		T267	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	1		T238	13		T322	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T159	13		T52	1		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T138	8		T69	1		T151	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T223	15		T171	9		T323	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T88	20		T254	14		T197	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T221	1		T153	8		T257	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	2		T41	14		T151	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T49	1		T50	1		T236	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T169	4		T249	8		T274	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T14	1		T54	3		T55	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T41	13		T55	14		T69	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T17	11		T160	9		T230	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T21	7		T141	9		T151	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T68	5		T221	13		T223	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T19	12		T135	10		T143	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T161	2		T160	3		T33	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T194	12		T282	5		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T51	1		T152	16		T271	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T324	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T263	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T153	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T94	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T15	4		T267	1		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T135	7		T68	3		T224	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T68	9		T140	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T79	11		T141	1		T69	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T159	11		T52	2		T187	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	4		T151	10		T225	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T219	1		T32	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T138	1		T150	10		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T221	8		T153	13		T185	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T13	4		T16	1		T18	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T49	3		T50	2		T236	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	1		T31	1		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	4		T17	1		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T41	1		T55	12		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T54	4		T55	9		T148	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T222	1		T240	2		T162	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T68	1		T221	15		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	396	1			T19	1		T20	10		T21	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	451	1			T137	1		T51	3		T199	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13819	1			T3	20		T4	14		T5	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T94	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T267	13		T263	8		T325	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T68	6		T136	14		T194	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T68	4		T172	12		T263	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T141	8		T69	1		T178	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T159	13		T52	1		T187	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T12	1		T151	2		T296	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T152	13		T223	15		T171	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T138	8		T154	14		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T221	1		T153	8		T257	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T13	2		T88	20		T254	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T49	1		T50	1		T236	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T41	14		T69	15		T169	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	1		T17	11		T245	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T41	13		T55	14		T234	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T54	3		T55	11		T160	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T162	8		T293	11		T220	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T68	5		T221	13		T238	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T19	12		T21	7		T135	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T51	1		T161	2		T160	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18518

1

T3

20

T4

14

T5

2

auto[1]

auto[0]

4101

1

T12

1

T13

2

T14

1