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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.56 99.07 96.67 100.00 100.00 98.83 98.33 90.04


Total test records in report: 920
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T795 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup_fixed.4040598668 Aug 21 06:12:06 AM UTC 24 Aug 21 06:30:39 AM UTC 24 381333663910 ps
T796 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.2008996461 Aug 21 06:15:06 AM UTC 24 Aug 21 06:31:01 AM UTC 24 358499914447 ps
T797 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all.2592677063 Aug 21 06:03:03 AM UTC 24 Aug 21 06:31:34 AM UTC 24 481761103017 ps
T798 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.3767262282 Aug 21 06:14:39 AM UTC 24 Aug 21 06:36:13 AM UTC 24 531495438578 ps
T799 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.2559139247 Aug 21 06:12:15 AM UTC 24 Aug 21 06:37:47 AM UTC 24 489265242823 ps
T800 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.1987950061 Aug 21 05:02:27 AM UTC 24 Aug 21 05:02:29 AM UTC 24 381735208 ps
T74 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4147035580 Aug 21 05:02:25 AM UTC 24 Aug 21 05:02:30 AM UTC 24 568388977 ps
T115 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3542479896 Aug 21 05:02:27 AM UTC 24 Aug 21 05:02:30 AM UTC 24 366858501 ps
T132 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2961146295 Aug 21 05:02:27 AM UTC 24 Aug 21 05:02:32 AM UTC 24 678544820 ps
T801 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.3153778022 Aug 21 05:02:31 AM UTC 24 Aug 21 05:02:33 AM UTC 24 385299198 ps
T75 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2624752095 Aug 21 05:02:31 AM UTC 24 Aug 21 05:02:33 AM UTC 24 370058208 ps
T80 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1530409100 Aug 21 05:02:31 AM UTC 24 Aug 21 05:02:35 AM UTC 24 523719759 ps
T116 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3631656959 Aug 21 05:02:31 AM UTC 24 Aug 21 05:02:36 AM UTC 24 1373019814 ps
T117 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2268383143 Aug 21 05:02:32 AM UTC 24 Aug 21 05:02:36 AM UTC 24 438127082 ps
T133 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3436029575 Aug 21 05:02:33 AM UTC 24 Aug 21 05:02:37 AM UTC 24 802709944 ps
T84 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.770284878 Aug 21 05:02:35 AM UTC 24 Aug 21 05:02:38 AM UTC 24 401787489 ps
T70 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1136657315 Aug 21 05:02:31 AM UTC 24 Aug 21 05:02:38 AM UTC 24 3965235328 ps
T64 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.630777993 Aug 21 05:02:30 AM UTC 24 Aug 21 05:02:38 AM UTC 24 5409264001 ps
T134 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3393332071 Aug 21 05:02:30 AM UTC 24 Aug 21 05:02:40 AM UTC 24 1209221987 ps
T81 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3751341927 Aug 21 05:02:35 AM UTC 24 Aug 21 05:02:40 AM UTC 24 422514518 ps
T802 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.680112988 Aug 21 05:02:36 AM UTC 24 Aug 21 05:02:40 AM UTC 24 527953471 ps
T118 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1048508261 Aug 21 05:02:36 AM UTC 24 Aug 21 05:02:41 AM UTC 24 1265533859 ps
T119 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.838247650 Aug 21 05:02:37 AM UTC 24 Aug 21 05:02:41 AM UTC 24 359478472 ps
T82 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1100847344 Aug 21 05:02:39 AM UTC 24 Aug 21 05:02:42 AM UTC 24 481065137 ps
T71 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1912568298 Aug 21 05:02:36 AM UTC 24 Aug 21 05:02:42 AM UTC 24 4719111130 ps
T803 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.3683147032 Aug 21 05:02:41 AM UTC 24 Aug 21 05:02:43 AM UTC 24 634390356 ps
T104 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2435309241 Aug 21 05:02:39 AM UTC 24 Aug 21 05:02:44 AM UTC 24 535109800 ps
T120 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1366069001 Aug 21 05:02:39 AM UTC 24 Aug 21 05:02:44 AM UTC 24 1475655642 ps
T65 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.548284835 Aug 21 05:02:39 AM UTC 24 Aug 21 05:02:44 AM UTC 24 2197029612 ps
T128 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.636540088 Aug 21 05:02:41 AM UTC 24 Aug 21 05:02:45 AM UTC 24 435924047 ps
T105 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.824618384 Aug 21 05:02:43 AM UTC 24 Aug 21 05:02:46 AM UTC 24 578608759 ps
T83 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2920639454 Aug 21 05:02:43 AM UTC 24 Aug 21 05:02:46 AM UTC 24 624768698 ps
T804 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1324367705 Aug 21 05:02:41 AM UTC 24 Aug 21 05:02:47 AM UTC 24 778769038 ps
T121 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1869451216 Aug 21 05:02:43 AM UTC 24 Aug 21 05:02:47 AM UTC 24 1735160017 ps
T805 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.2973605827 Aug 21 05:02:46 AM UTC 24 Aug 21 05:02:48 AM UTC 24 394924834 ps
T122 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3677928168 Aug 21 05:02:46 AM UTC 24 Aug 21 05:02:48 AM UTC 24 493351098 ps
T806 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.996983964 Aug 21 05:02:46 AM UTC 24 Aug 21 05:02:49 AM UTC 24 872582235 ps
T72 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4220787820 Aug 21 05:02:41 AM UTC 24 Aug 21 05:02:49 AM UTC 24 8218527886 ps
T85 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.948853471 Aug 21 05:02:46 AM UTC 24 Aug 21 05:02:49 AM UTC 24 551279766 ps
T807 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.2695954709 Aug 21 05:02:48 AM UTC 24 Aug 21 05:02:50 AM UTC 24 507071413 ps
T129 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.286912411 Aug 21 05:02:48 AM UTC 24 Aug 21 05:02:50 AM UTC 24 325171910 ps
T66 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.437039647 Aug 21 05:02:46 AM UTC 24 Aug 21 05:02:51 AM UTC 24 1544735911 ps
T808 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1217801108 Aug 21 05:02:48 AM UTC 24 Aug 21 05:02:51 AM UTC 24 583835605 ps
T809 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3795303321 Aug 21 05:02:48 AM UTC 24 Aug 21 05:02:51 AM UTC 24 592815665 ps
T67 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1334608809 Aug 21 05:02:35 AM UTC 24 Aug 21 05:02:51 AM UTC 24 5241998361 ps
T810 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.4185526379 Aug 21 05:02:49 AM UTC 24 Aug 21 05:02:51 AM UTC 24 303309256 ps
T811 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2631498878 Aug 21 05:02:46 AM UTC 24 Aug 21 05:02:52 AM UTC 24 412561551 ps
T812 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1695499797 Aug 21 05:02:49 AM UTC 24 Aug 21 05:02:53 AM UTC 24 570777646 ps
T130 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.662662543 Aug 21 05:02:48 AM UTC 24 Aug 21 05:02:53 AM UTC 24 2348334331 ps
T813 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.250385932 Aug 21 05:02:51 AM UTC 24 Aug 21 05:02:53 AM UTC 24 481311865 ps
T123 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.845246695 Aug 21 05:02:30 AM UTC 24 Aug 21 05:02:53 AM UTC 24 28475133474 ps
T814 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3581116488 Aug 21 05:02:52 AM UTC 24 Aug 21 05:02:55 AM UTC 24 539098992 ps
T76 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3772494147 Aug 21 05:02:49 AM UTC 24 Aug 21 05:02:55 AM UTC 24 4531363237 ps
T815 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2760694932 Aug 21 05:02:51 AM UTC 24 Aug 21 05:02:55 AM UTC 24 402414748 ps
T816 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1259044305 Aug 21 05:02:51 AM UTC 24 Aug 21 05:02:55 AM UTC 24 355693658 ps
T817 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.2182959842 Aug 21 05:02:53 AM UTC 24 Aug 21 05:02:55 AM UTC 24 408449096 ps
T818 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.305701811 Aug 21 05:02:52 AM UTC 24 Aug 21 05:02:55 AM UTC 24 429937155 ps
T124 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.459585932 Aug 21 05:02:53 AM UTC 24 Aug 21 05:02:55 AM UTC 24 366253407 ps
T131 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3963889255 Aug 21 05:02:49 AM UTC 24 Aug 21 05:02:56 AM UTC 24 4316524037 ps
T819 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1732187693 Aug 21 05:02:54 AM UTC 24 Aug 21 05:02:56 AM UTC 24 572327864 ps
T820 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2130619716 Aug 21 05:02:52 AM UTC 24 Aug 21 05:02:56 AM UTC 24 442696793 ps
T821 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.768008878 Aug 21 05:02:54 AM UTC 24 Aug 21 05:02:57 AM UTC 24 2515756188 ps
T77 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.210629285 Aug 21 05:02:48 AM UTC 24 Aug 21 05:02:57 AM UTC 24 8778008556 ps
T822 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.59475260 Aug 21 05:02:54 AM UTC 24 Aug 21 05:02:58 AM UTC 24 749392034 ps
T823 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.2660533198 Aug 21 05:02:56 AM UTC 24 Aug 21 05:02:58 AM UTC 24 329515066 ps
T824 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3175573499 Aug 21 05:02:56 AM UTC 24 Aug 21 05:02:58 AM UTC 24 437303115 ps
T825 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3368219499 Aug 21 05:02:52 AM UTC 24 Aug 21 05:02:58 AM UTC 24 2168386912 ps
T826 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.457054917 Aug 21 05:02:56 AM UTC 24 Aug 21 05:02:59 AM UTC 24 348568689 ps
T827 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.598720061 Aug 21 05:02:56 AM UTC 24 Aug 21 05:02:59 AM UTC 24 426140413 ps
T828 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1093641688 Aug 21 05:02:46 AM UTC 24 Aug 21 05:02:59 AM UTC 24 2387873263 ps
T829 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3715944938 Aug 21 05:02:57 AM UTC 24 Aug 21 05:03:00 AM UTC 24 582391436 ps
T830 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.4278933021 Aug 21 05:02:56 AM UTC 24 Aug 21 05:03:00 AM UTC 24 510957472 ps
T831 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2936545950 Aug 21 05:02:57 AM UTC 24 Aug 21 05:03:00 AM UTC 24 528755115 ps
T832 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1844531717 Aug 21 05:02:39 AM UTC 24 Aug 21 05:03:01 AM UTC 24 25862943718 ps
T833 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.945396201 Aug 21 05:02:59 AM UTC 24 Aug 21 05:03:01 AM UTC 24 413698731 ps
T125 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3669951820 Aug 21 05:02:59 AM UTC 24 Aug 21 05:03:02 AM UTC 24 351919616 ps
T834 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3141585511 Aug 21 05:02:57 AM UTC 24 Aug 21 05:03:02 AM UTC 24 1082787323 ps
T835 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2405203995 Aug 21 05:02:57 AM UTC 24 Aug 21 05:03:02 AM UTC 24 4038407581 ps
T836 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3689194997 Aug 21 05:02:43 AM UTC 24 Aug 21 05:03:02 AM UTC 24 4940044432 ps
T837 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.2872565845 Aug 21 05:03:01 AM UTC 24 Aug 21 05:03:03 AM UTC 24 388888235 ps
T838 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.182865455 Aug 21 05:03:01 AM UTC 24 Aug 21 05:03:03 AM UTC 24 880008793 ps
T839 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2841661812 Aug 21 05:03:01 AM UTC 24 Aug 21 05:03:03 AM UTC 24 457411695 ps
T127 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2294513075 Aug 21 05:03:01 AM UTC 24 Aug 21 05:03:03 AM UTC 24 528565187 ps
T840 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2755170623 Aug 21 05:03:01 AM UTC 24 Aug 21 05:03:04 AM UTC 24 827221896 ps
T841 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3784648501 Aug 21 05:02:56 AM UTC 24 Aug 21 05:03:04 AM UTC 24 4699925626 ps
T350 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.4209118131 Aug 21 05:02:27 AM UTC 24 Aug 21 05:03:04 AM UTC 24 8312692354 ps
T842 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2644241441 Aug 21 05:02:51 AM UTC 24 Aug 21 05:03:05 AM UTC 24 4657237182 ps
T843 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2896989183 Aug 21 05:03:02 AM UTC 24 Aug 21 05:03:05 AM UTC 24 559944551 ps
T844 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1582272668 Aug 21 05:03:01 AM UTC 24 Aug 21 05:03:05 AM UTC 24 543846442 ps
T845 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4134471579 Aug 21 05:03:01 AM UTC 24 Aug 21 05:03:05 AM UTC 24 2059110592 ps
T126 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3261113913 Aug 21 05:03:03 AM UTC 24 Aug 21 05:03:05 AM UTC 24 503197923 ps
T846 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3169542415 Aug 21 05:03:03 AM UTC 24 Aug 21 05:03:06 AM UTC 24 527020279 ps
T847 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2763420459 Aug 21 05:03:03 AM UTC 24 Aug 21 05:03:06 AM UTC 24 458056111 ps
T848 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4188175191 Aug 21 05:03:03 AM UTC 24 Aug 21 05:03:06 AM UTC 24 420468472 ps
T849 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.355711304 Aug 21 05:03:01 AM UTC 24 Aug 21 05:03:06 AM UTC 24 9131161048 ps
T850 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2617475170 Aug 21 05:03:03 AM UTC 24 Aug 21 05:03:07 AM UTC 24 737895877 ps
T851 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.574762324 Aug 21 05:03:04 AM UTC 24 Aug 21 05:03:07 AM UTC 24 667547479 ps
T852 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.2498933373 Aug 21 05:03:04 AM UTC 24 Aug 21 05:03:08 AM UTC 24 355394122 ps
T853 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3000203457 Aug 21 05:03:04 AM UTC 24 Aug 21 05:03:08 AM UTC 24 330632048 ps
T854 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3268723518 Aug 21 05:03:05 AM UTC 24 Aug 21 05:03:08 AM UTC 24 638357887 ps
T348 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1833495592 Aug 21 05:03:03 AM UTC 24 Aug 21 05:03:08 AM UTC 24 4387056740 ps
T855 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.875103218 Aug 21 05:03:04 AM UTC 24 Aug 21 05:03:08 AM UTC 24 729160792 ps
T856 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3741679959 Aug 21 05:03:03 AM UTC 24 Aug 21 05:03:08 AM UTC 24 3625411584 ps
T857 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.1207722412 Aug 21 05:03:06 AM UTC 24 Aug 21 05:03:08 AM UTC 24 384731853 ps
T858 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.916258105 Aug 21 05:03:06 AM UTC 24 Aug 21 05:03:08 AM UTC 24 426812735 ps
T859 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2787146583 Aug 21 05:03:06 AM UTC 24 Aug 21 05:03:09 AM UTC 24 465758019 ps
T860 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.255713003 Aug 21 05:03:06 AM UTC 24 Aug 21 05:03:09 AM UTC 24 522308440 ps
T861 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.273981790 Aug 21 05:03:07 AM UTC 24 Aug 21 05:03:10 AM UTC 24 500841156 ps
T862 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.134066095 Aug 21 05:03:08 AM UTC 24 Aug 21 05:03:10 AM UTC 24 363319084 ps
T863 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.3580303640 Aug 21 05:03:07 AM UTC 24 Aug 21 05:03:10 AM UTC 24 392877603 ps
T864 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.846912473 Aug 21 05:03:03 AM UTC 24 Aug 21 05:03:10 AM UTC 24 4849517390 ps
T865 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.123612706 Aug 21 05:03:08 AM UTC 24 Aug 21 05:03:10 AM UTC 24 747428973 ps
T866 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2530224867 Aug 21 05:03:05 AM UTC 24 Aug 21 05:03:11 AM UTC 24 4432605844 ps
T867 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.2638154556 Aug 21 05:03:09 AM UTC 24 Aug 21 05:03:11 AM UTC 24 354617711 ps
T868 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3540010950 Aug 21 05:03:09 AM UTC 24 Aug 21 05:03:11 AM UTC 24 489700343 ps
T86 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2246936723 Aug 21 05:02:43 AM UTC 24 Aug 21 05:03:11 AM UTC 24 8688175444 ps
T869 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2245930599 Aug 21 05:03:07 AM UTC 24 Aug 21 05:03:11 AM UTC 24 833254108 ps
T870 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1596005652 Aug 21 05:03:09 AM UTC 24 Aug 21 05:03:12 AM UTC 24 559309131 ps
T871 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2114848489 Aug 21 05:03:09 AM UTC 24 Aug 21 05:03:12 AM UTC 24 381369301 ps
T872 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1186528903 Aug 21 05:03:09 AM UTC 24 Aug 21 05:03:12 AM UTC 24 519251158 ps
T873 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2077574424 Aug 21 05:03:01 AM UTC 24 Aug 21 05:03:13 AM UTC 24 2729761032 ps
T874 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.509459273 Aug 21 05:03:10 AM UTC 24 Aug 21 05:03:13 AM UTC 24 491089208 ps
T87 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2375000160 Aug 21 05:02:58 AM UTC 24 Aug 21 05:03:13 AM UTC 24 8375552821 ps
T875 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2348516390 Aug 21 05:03:10 AM UTC 24 Aug 21 05:03:13 AM UTC 24 555204552 ps
T876 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.103074019 Aug 21 05:03:09 AM UTC 24 Aug 21 05:03:13 AM UTC 24 453516349 ps
T877 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.789382306 Aug 21 05:03:10 AM UTC 24 Aug 21 05:03:13 AM UTC 24 400817682 ps
T878 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.2103386342 Aug 21 05:03:12 AM UTC 24 Aug 21 05:03:14 AM UTC 24 346735216 ps
T879 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.3976582680 Aug 21 05:03:12 AM UTC 24 Aug 21 05:03:14 AM UTC 24 444752636 ps
T880 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.2401347409 Aug 21 05:03:12 AM UTC 24 Aug 21 05:03:14 AM UTC 24 416091310 ps
T881 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.2974929027 Aug 21 05:03:10 AM UTC 24 Aug 21 05:03:14 AM UTC 24 375196116 ps
T882 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.845086636 Aug 21 05:03:12 AM UTC 24 Aug 21 05:03:14 AM UTC 24 441724367 ps
T883 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.1791404778 Aug 21 05:03:10 AM UTC 24 Aug 21 05:03:14 AM UTC 24 464379884 ps
T884 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.1727870493 Aug 21 05:03:12 AM UTC 24 Aug 21 05:03:14 AM UTC 24 556536452 ps
T885 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.1345630792 Aug 21 05:03:12 AM UTC 24 Aug 21 05:03:14 AM UTC 24 282989146 ps
T886 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.2014159289 Aug 21 05:03:12 AM UTC 24 Aug 21 05:03:14 AM UTC 24 425607509 ps
T887 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1260866283 Aug 21 05:03:09 AM UTC 24 Aug 21 05:03:14 AM UTC 24 4545913162 ps
T888 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3973094742 Aug 21 05:03:08 AM UTC 24 Aug 21 05:03:15 AM UTC 24 4303807681 ps
T889 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.808668467 Aug 21 05:03:06 AM UTC 24 Aug 21 05:03:15 AM UTC 24 2321280618 ps
T890 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.222058513 Aug 21 05:03:13 AM UTC 24 Aug 21 05:03:15 AM UTC 24 427751108 ps
T349 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1952973889 Aug 21 05:03:07 AM UTC 24 Aug 21 05:03:15 AM UTC 24 4269201081 ps
T891 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.3261637159 Aug 21 05:03:13 AM UTC 24 Aug 21 05:03:16 AM UTC 24 397635868 ps
T892 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.3341432770 Aug 21 05:03:13 AM UTC 24 Aug 21 05:03:16 AM UTC 24 460648338 ps
T893 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.604532690 Aug 21 05:03:14 AM UTC 24 Aug 21 05:03:16 AM UTC 24 317922427 ps
T894 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.2169056274 Aug 21 05:03:14 AM UTC 24 Aug 21 05:03:16 AM UTC 24 512427343 ps
T895 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.370407005 Aug 21 05:03:14 AM UTC 24 Aug 21 05:03:17 AM UTC 24 473005487 ps
T896 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.3189962861 Aug 21 05:03:15 AM UTC 24 Aug 21 05:03:17 AM UTC 24 390057773 ps
T897 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.2681601306 Aug 21 05:03:15 AM UTC 24 Aug 21 05:03:17 AM UTC 24 387548736 ps
T898 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2054984191 Aug 21 05:03:06 AM UTC 24 Aug 21 05:03:17 AM UTC 24 3964932640 ps
T899 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.90174789 Aug 21 05:03:15 AM UTC 24 Aug 21 05:03:17 AM UTC 24 374197227 ps
T900 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.900813199 Aug 21 05:03:15 AM UTC 24 Aug 21 05:03:17 AM UTC 24 535929302 ps
T901 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.124179900 Aug 21 05:03:14 AM UTC 24 Aug 21 05:03:17 AM UTC 24 350027453 ps
T902 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.1348357890 Aug 21 05:03:14 AM UTC 24 Aug 21 05:03:17 AM UTC 24 447879542 ps
T903 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.3940940310 Aug 21 05:03:15 AM UTC 24 Aug 21 05:03:17 AM UTC 24 440565549 ps
T904 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.3258945768 Aug 21 05:03:15 AM UTC 24 Aug 21 05:03:17 AM UTC 24 298196047 ps
T905 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.3088903132 Aug 21 05:03:15 AM UTC 24 Aug 21 05:03:17 AM UTC 24 360469337 ps
T906 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2391989483 Aug 21 05:03:02 AM UTC 24 Aug 21 05:03:17 AM UTC 24 4805107048 ps
T907 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1733379712 Aug 21 05:02:55 AM UTC 24 Aug 21 05:03:17 AM UTC 24 7925676274 ps
T908 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1500985235 Aug 21 05:03:08 AM UTC 24 Aug 21 05:03:18 AM UTC 24 8668679732 ps
T909 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.430023506 Aug 21 05:03:10 AM UTC 24 Aug 21 05:03:18 AM UTC 24 2676601533 ps
T910 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3992408176 Aug 21 05:02:56 AM UTC 24 Aug 21 05:03:18 AM UTC 24 8015228646 ps
T911 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.225881539 Aug 21 05:03:16 AM UTC 24 Aug 21 05:03:19 AM UTC 24 360518180 ps
T912 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.840156632 Aug 21 05:03:16 AM UTC 24 Aug 21 05:03:19 AM UTC 24 339726933 ps
T913 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.2745311571 Aug 21 05:03:16 AM UTC 24 Aug 21 05:03:19 AM UTC 24 279265690 ps
T914 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.428719648 Aug 21 05:03:16 AM UTC 24 Aug 21 05:03:19 AM UTC 24 323179729 ps
T915 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1682678414 Aug 21 05:03:09 AM UTC 24 Aug 21 05:03:19 AM UTC 24 4534798466 ps
T916 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.188489967 Aug 21 05:02:46 AM UTC 24 Aug 21 05:03:19 AM UTC 24 26945131067 ps
T917 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2091763063 Aug 21 05:02:53 AM UTC 24 Aug 21 05:03:20 AM UTC 24 8606905969 ps
T918 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1978972927 Aug 21 05:03:04 AM UTC 24 Aug 21 05:03:24 AM UTC 24 8615106440 ps
T919 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1388681323 Aug 21 05:02:41 AM UTC 24 Aug 21 05:03:39 AM UTC 24 25886176599 ps
T920 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4224285384 Aug 21 05:02:32 AM UTC 24 Aug 21 05:04:25 AM UTC 24 26159959592 ps

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2021186427
Short name T5
Test name
Test status
Simulation time 2558834356 ps
CPU time 5.91 seconds
Started Aug 21 05:07:15 AM UTC 24
Finished Aug 21 05:07:25 AM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2021186427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2021186427
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2284385940
Short name T12
Test name
Test status
Simulation time 30314783149 ps
CPU time 18.2 seconds
Started Aug 21 05:07:11 AM UTC 24
Finished Aug 21 05:07:37 AM UTC 24
Peak memory 222012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2284385940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2284385940
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.34510256
Short name T41
Test name
Test status
Simulation time 353947662555 ps
CPU time 132.66 seconds
Started Aug 21 05:07:13 AM UTC 24
Finished Aug 21 05:09:29 AM UTC 24
Peak memory 211436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34510256 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fi
lters_wakeup.34510256
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.886379540
Short name T58
Test name
Test status
Simulation time 97212299960 ps
CPU time 397.95 seconds
Started Aug 21 05:07:11 AM UTC 24
Finished Aug 21 05:14:00 AM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=886379540 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.886379540
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.3519863670
Short name T151
Test name
Test status
Simulation time 521307750877 ps
CPU time 408.44 seconds
Started Aug 21 05:08:18 AM UTC 24
Finished Aug 21 05:15:11 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3519863670 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_cl
ock_gating.3519863670
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.2934115021
Short name T68
Test name
Test status
Simulation time 543228441279 ps
CPU time 129.93 seconds
Started Aug 21 05:09:27 AM UTC 24
Finished Aug 21 05:11:39 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2934115021 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_cl
ock_gating.2934115021
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.4220306195
Short name T144
Test name
Test status
Simulation time 523163591676 ps
CPU time 132.56 seconds
Started Aug 21 05:14:16 AM UTC 24
Finished Aug 21 05:16:31 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4220306195 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_cl
ock_gating.4220306195
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1366234579
Short name T13
Test name
Test status
Simulation time 25943973928 ps
CPU time 16.96 seconds
Started Aug 21 05:07:21 AM UTC 24
Finished Aug 21 05:07:43 AM UTC 24
Peak memory 221956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1366234579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1366234579
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.1021841594
Short name T154
Test name
Test status
Simulation time 518578386707 ps
CPU time 558.88 seconds
Started Aug 21 05:07:38 AM UTC 24
Finished Aug 21 05:17:03 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1021841594 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_cl
ock_gating.1021841594
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2961243772
Short name T236
Test name
Test status
Simulation time 231389407356 ps
CPU time 35.84 seconds
Started Aug 21 05:23:44 AM UTC 24
Finished Aug 21 05:24:21 AM UTC 24
Peak memory 221836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2961243772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2961243772
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.4291854998
Short name T2
Test name
Test status
Simulation time 3854230346 ps
CPU time 2.74 seconds
Started Aug 21 05:07:13 AM UTC 24
Finished Aug 21 05:07:16 AM UTC 24
Peak memory 243384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4291854998 -ass
ert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.4291854998
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4147035580
Short name T74
Test name
Test status
Simulation time 568388977 ps
CPU time 4.05 seconds
Started Aug 21 05:02:25 AM UTC 24
Finished Aug 21 05:02:30 AM UTC 24
Peak memory 211380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4147035580 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.4147035580
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.2240994184
Short name T162
Test name
Test status
Simulation time 346572016581 ps
CPU time 185.76 seconds
Started Aug 21 05:17:10 AM UTC 24
Finished Aug 21 05:20:19 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2240994184 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_c
lock_gating.2240994184
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.4114004737
Short name T245
Test name
Test status
Simulation time 326596976089 ps
CPU time 782.21 seconds
Started Aug 21 05:07:28 AM UTC 24
Finished Aug 21 05:20:39 AM UTC 24
Peak memory 212760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4114004737 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_cl
ock_gating.4114004737
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.336478376
Short name T189
Test name
Test status
Simulation time 493841971101 ps
CPU time 384.92 seconds
Started Aug 21 05:16:55 AM UTC 24
Finished Aug 21 05:23:25 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=336478376 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.336478376
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.1883587351
Short name T225
Test name
Test status
Simulation time 493512513187 ps
CPU time 619.01 seconds
Started Aug 21 05:07:11 AM UTC 24
Finished Aug 21 05:17:40 AM UTC 24
Peak memory 212756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1883587351 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1883587351
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1277414335
Short name T18
Test name
Test status
Simulation time 327485368851 ps
CPU time 93.21 seconds
Started Aug 21 05:07:37 AM UTC 24
Finished Aug 21 05:09:12 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1277414335 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
interrupt_fixed.1277414335
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.1988523533
Short name T230
Test name
Test status
Simulation time 379009009457 ps
CPU time 1030.18 seconds
Started Aug 21 05:07:11 AM UTC 24
Finished Aug 21 05:24:38 AM UTC 24
Peak memory 212736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1988523533
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_str
ess_all.1988523533
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.3833128448
Short name T238
Test name
Test status
Simulation time 345479124482 ps
CPU time 348.8 seconds
Started Aug 21 05:17:04 AM UTC 24
Finished Aug 21 05:22:57 AM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3833128448 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl
_filters_wakeup.3833128448
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.2358351773
Short name T172
Test name
Test status
Simulation time 598281216525 ps
CPU time 487.23 seconds
Started Aug 21 05:22:18 AM UTC 24
Finished Aug 21 05:30:31 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2358351773 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2358351773
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.845246695
Short name T123
Test name
Test status
Simulation time 28475133474 ps
CPU time 21.88 seconds
Started Aug 21 05:02:30 AM UTC 24
Finished Aug 21 05:02:53 AM UTC 24
Peak memory 211516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=845246695
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_c
sr_bit_bash.845246695
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.1854833188
Short name T156
Test name
Test status
Simulation time 494471335130 ps
CPU time 798.45 seconds
Started Aug 21 05:15:52 AM UTC 24
Finished Aug 21 05:29:19 AM UTC 24
Peak memory 211516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1854833188 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1854833188
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.2295758846
Short name T221
Test name
Test status
Simulation time 363419953376 ps
CPU time 487.76 seconds
Started Aug 21 05:07:13 AM UTC 24
Finished Aug 21 05:15:27 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2295758846 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_cl
ock_gating.2295758846
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.2892570319
Short name T69
Test name
Test status
Simulation time 355766663906 ps
CPU time 170.2 seconds
Started Aug 21 05:12:04 AM UTC 24
Finished Aug 21 05:14:57 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2892570319 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_cl
ock_gating.2892570319
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.3378993297
Short name T194
Test name
Test status
Simulation time 435127900865 ps
CPU time 179.26 seconds
Started Aug 21 05:16:41 AM UTC 24
Finished Aug 21 05:19:43 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3378993297
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_st
ress_all.3378993297
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.3757141732
Short name T235
Test name
Test status
Simulation time 490464118113 ps
CPU time 1509.07 seconds
Started Aug 21 05:20:22 AM UTC 24
Finished Aug 21 05:45:46 AM UTC 24
Peak memory 212768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3757141732 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3757141732
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.2152066965
Short name T271
Test name
Test status
Simulation time 659478856959 ps
CPU time 1611.5 seconds
Started Aug 21 05:15:40 AM UTC 24
Finished Aug 21 05:42:48 AM UTC 24
Peak memory 212628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2152066965
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_st
ress_all.2152066965
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.1650693948
Short name T263
Test name
Test status
Simulation time 528751658687 ps
CPU time 1494.19 seconds
Started Aug 21 05:07:11 AM UTC 24
Finished Aug 21 05:32:21 AM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1650693948 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_cl
ock_gating.1650693948
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1074642038
Short name T49
Test name
Test status
Simulation time 3960881399 ps
CPU time 11.09 seconds
Started Aug 21 05:10:04 AM UTC 24
Finished Aug 21 05:10:16 AM UTC 24
Peak memory 211352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1074642038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1074642038
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.517227351
Short name T160
Test name
Test status
Simulation time 329830669214 ps
CPU time 192.52 seconds
Started Aug 21 05:12:08 AM UTC 24
Finished Aug 21 05:15:24 AM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=517227351 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.517227351
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.2354332272
Short name T234
Test name
Test status
Simulation time 192209215746 ps
CPU time 481.2 seconds
Started Aug 21 05:07:38 AM UTC 24
Finished Aug 21 05:15:45 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2354332272 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_
filters_wakeup.2354332272
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.1564941510
Short name T239
Test name
Test status
Simulation time 487449408032 ps
CPU time 1011.72 seconds
Started Aug 21 05:31:29 AM UTC 24
Finished Aug 21 05:48:31 AM UTC 24
Peak memory 212612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1564941510 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_c
lock_gating.1564941510
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/22.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_both.2922293905
Short name T175
Test name
Test status
Simulation time 503875425740 ps
CPU time 391.9 seconds
Started Aug 21 06:01:31 AM UTC 24
Finished Aug 21 06:08:08 AM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2922293905 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2922293905
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/41.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.263085988
Short name T1
Test name
Test status
Simulation time 415806005 ps
CPU time 1.44 seconds
Started Aug 21 05:07:13 AM UTC 24
Finished Aug 21 05:07:16 AM UTC 24
Peak memory 210700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=263085988 -ass
ert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.263085988
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2246936723
Short name T86
Test name
Test status
Simulation time 8688175444 ps
CPU time 26.63 seconds
Started Aug 21 05:02:43 AM UTC 24
Finished Aug 21 05:03:11 AM UTC 24
Peak memory 211448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2246936
723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_tl_intg_err.2246936723
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.3526311823
Short name T227
Test name
Test status
Simulation time 496067184259 ps
CPU time 647.1 seconds
Started Aug 21 05:18:06 AM UTC 24
Finished Aug 21 05:29:00 AM UTC 24
Peak memory 211440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3526311823 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3526311823
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.3345247016
Short name T192
Test name
Test status
Simulation time 321953968817 ps
CPU time 724.72 seconds
Started Aug 21 05:48:19 AM UTC 24
Finished Aug 21 06:00:32 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3345247016
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_st
ress_all.3345247016
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.630777993
Short name T64
Test name
Test status
Simulation time 5409264001 ps
CPU time 6.05 seconds
Started Aug 21 05:02:30 AM UTC 24
Finished Aug 21 05:02:38 AM UTC 24
Peak memory 211516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=630777993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.adc_ctrl_same_csr_outstanding.630777993
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.443015244
Short name T166
Test name
Test status
Simulation time 696515786159 ps
CPU time 137.66 seconds
Started Aug 21 05:35:53 AM UTC 24
Finished Aug 21 05:38:13 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=443015244 -a
ssert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_
filters_wakeup.443015244
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.826685391
Short name T212
Test name
Test status
Simulation time 131285699064 ps
CPU time 631.61 seconds
Started Aug 21 05:07:15 AM UTC 24
Finished Aug 21 05:17:57 AM UTC 24
Peak memory 211572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=826685391 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.826685391
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.3578959775
Short name T296
Test name
Test status
Simulation time 381072329857 ps
CPU time 903.53 seconds
Started Aug 21 05:23:26 AM UTC 24
Finished Aug 21 05:38:39 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3578959775 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_c
lock_gating.3578959775
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_both.1782528558
Short name T302
Test name
Test status
Simulation time 575032379920 ps
CPU time 615.66 seconds
Started Aug 21 06:04:47 AM UTC 24
Finished Aug 21 06:15:10 AM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1782528558 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1782528558
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/44.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all.2041193445
Short name T326
Test name
Test status
Simulation time 341325302349 ps
CPU time 400.74 seconds
Started Aug 21 05:39:34 AM UTC 24
Finished Aug 21 05:46:19 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2041193445
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_st
ress_all.2041193445
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.600952550
Short name T94
Test name
Test status
Simulation time 14808965736 ps
CPU time 19.8 seconds
Started Aug 21 06:01:40 AM UTC 24
Finished Aug 21 06:02:01 AM UTC 24
Peak memory 221736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=600952550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.600952550
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.768048687
Short name T379
Test name
Test status
Simulation time 201340370821 ps
CPU time 584.47 seconds
Started Aug 21 05:07:11 AM UTC 24
Finished Aug 21 05:17:10 AM UTC 24
Peak memory 212732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=768048687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 0.adc_ctrl_filters_wakeup_fixed.768048687
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.4284618293
Short name T299
Test name
Test status
Simulation time 355414415012 ps
CPU time 940.15 seconds
Started Aug 21 05:32:17 AM UTC 24
Finished Aug 21 05:48:07 AM UTC 24
Peak memory 212628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4284618293
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_st
ress_all.4284618293
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt.1511909291
Short name T95
Test name
Test status
Simulation time 323980996992 ps
CPU time 829.33 seconds
Started Aug 21 05:37:39 AM UTC 24
Finished Aug 21 05:51:37 AM UTC 24
Peak memory 212584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1511909291 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1511909291
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all.689071314
Short name T98
Test name
Test status
Simulation time 628437362675 ps
CPU time 783.37 seconds
Started Aug 21 05:38:38 AM UTC 24
Finished Aug 21 05:51:50 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=689071314 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_str
ess_all.689071314
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_both.872714743
Short name T273
Test name
Test status
Simulation time 508139889012 ps
CPU time 301.66 seconds
Started Aug 21 05:40:33 AM UTC 24
Finished Aug 21 05:45:38 AM UTC 24
Peak memory 211824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=872714743 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.872714743
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/28.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.4219881646
Short name T206
Test name
Test status
Simulation time 132534660383 ps
CPU time 700.09 seconds
Started Aug 21 05:18:44 AM UTC 24
Finished Aug 21 05:30:32 AM UTC 24
Peak memory 211712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4219881646 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.4219881646
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.2016563856
Short name T196
Test name
Test status
Simulation time 328838567560 ps
CPU time 483.78 seconds
Started Aug 21 05:24:02 AM UTC 24
Finished Aug 21 05:32:12 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2016563856 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2016563856
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.2815635376
Short name T222
Test name
Test status
Simulation time 493338221656 ps
CPU time 295.64 seconds
Started Aug 21 05:13:09 AM UTC 24
Finished Aug 21 05:18:08 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2815635376 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2815635376
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.3085160695
Short name T153
Test name
Test status
Simulation time 531533263901 ps
CPU time 61.53 seconds
Started Aug 21 05:15:21 AM UTC 24
Finished Aug 21 05:16:24 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3085160695 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_c
lock_gating.3085160695
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.1015977333
Short name T330
Test name
Test status
Simulation time 366957399825 ps
CPU time 536.92 seconds
Started Aug 21 05:30:05 AM UTC 24
Finished Aug 21 05:39:08 AM UTC 24
Peak memory 211696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1015977333
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_st
ress_all.1015977333
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.2684374690
Short name T191
Test name
Test status
Simulation time 516280584525 ps
CPU time 206.08 seconds
Started Aug 21 05:42:47 AM UTC 24
Finished Aug 21 05:46:16 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2684374690 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2684374690
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/29.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_both.2135082399
Short name T335
Test name
Test status
Simulation time 489636381993 ps
CPU time 1419.27 seconds
Started Aug 21 06:00:40 AM UTC 24
Finished Aug 21 06:24:35 AM UTC 24
Peak memory 212884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2135082399 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2135082399
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/40.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2642139274
Short name T264
Test name
Test status
Simulation time 13668748982 ps
CPU time 13.87 seconds
Started Aug 21 06:05:34 AM UTC 24
Finished Aug 21 06:05:49 AM UTC 24
Peak memory 221688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2642139274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2642139274
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.2255941603
Short name T282
Test name
Test status
Simulation time 276803665586 ps
CPU time 731.92 seconds
Started Aug 21 05:15:24 AM UTC 24
Finished Aug 21 05:27:44 AM UTC 24
Peak memory 211696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2255941603 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2255941603
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.1955450420
Short name T267
Test name
Test status
Simulation time 211674408275 ps
CPU time 556.41 seconds
Started Aug 21 05:16:05 AM UTC 24
Finished Aug 21 05:25:28 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1955450420 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl
_filters_wakeup.1955450420
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.1121240631
Short name T278
Test name
Test status
Simulation time 562439968265 ps
CPU time 1677.68 seconds
Started Aug 21 05:26:06 AM UTC 24
Finished Aug 21 05:54:21 AM UTC 24
Peak memory 212440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1121240631 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_c
lock_gating.1121240631
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt.1817191576
Short name T311
Test name
Test status
Simulation time 327453077113 ps
CPU time 985.69 seconds
Started Aug 21 05:43:45 AM UTC 24
Finished Aug 21 06:00:21 AM UTC 24
Peak memory 212840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1817191576 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1817191576
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.2024356711
Short name T246
Test name
Test status
Simulation time 514521794040 ps
CPU time 1028.67 seconds
Started Aug 21 05:24:22 AM UTC 24
Finished Aug 21 05:41:41 AM UTC 24
Peak memory 212564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2024356711 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl
_filters_wakeup.2024356711
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup.3696451968
Short name T307
Test name
Test status
Simulation time 364687697798 ps
CPU time 51.9 seconds
Started Aug 21 05:37:43 AM UTC 24
Finished Aug 21 05:38:37 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3696451968 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl
_filters_wakeup.3696451968
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.3760813478
Short name T138
Test name
Test status
Simulation time 219176441734 ps
CPU time 133.74 seconds
Started Aug 21 05:08:10 AM UTC 24
Finished Aug 21 05:10:26 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3760813478 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_
filters_wakeup.3760813478
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.3027699769
Short name T251
Test name
Test status
Simulation time 331647389419 ps
CPU time 269.38 seconds
Started Aug 21 05:13:59 AM UTC 24
Finished Aug 21 05:18:32 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3027699769 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_
filters_wakeup.3027699769
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.3473419518
Short name T54
Test name
Test status
Simulation time 163995851034 ps
CPU time 144.57 seconds
Started Aug 21 05:07:13 AM UTC 24
Finished Aug 21 05:09:41 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3473419518 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3473419518
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.2969627532
Short name T20
Test name
Test status
Simulation time 167078503658 ps
CPU time 123.95 seconds
Started Aug 21 05:07:13 AM UTC 24
Finished Aug 21 05:09:20 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2969627532 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2969627532
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.110456215
Short name T322
Test name
Test status
Simulation time 181143839462 ps
CPU time 611.23 seconds
Started Aug 21 05:16:25 AM UTC 24
Finished Aug 21 05:26:44 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=110456215 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.110456215
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.3963307671
Short name T280
Test name
Test status
Simulation time 330826253874 ps
CPU time 792.79 seconds
Started Aug 21 05:15:46 AM UTC 24
Finished Aug 21 05:29:07 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3963307671 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3963307671
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.211913659
Short name T250
Test name
Test status
Simulation time 157491246404 ps
CPU time 396.32 seconds
Started Aug 21 05:22:00 AM UTC 24
Finished Aug 21 05:28:41 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=211913659 -a
ssert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_cl
ock_gating.211913659
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled.2126669935
Short name T165
Test name
Test status
Simulation time 493524915165 ps
CPU time 177.3 seconds
Started Aug 21 05:33:38 AM UTC 24
Finished Aug 21 05:36:38 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2126669935 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2126669935
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.3683037603
Short name T99
Test name
Test status
Simulation time 343856351783 ps
CPU time 266 seconds
Started Aug 21 05:47:25 AM UTC 24
Finished Aug 21 05:51:55 AM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3683037603 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_c
lock_gating.3683037603
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/32.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_fsm_reset.1262026020
Short name T356
Test name
Test status
Simulation time 126221052250 ps
CPU time 779.81 seconds
Started Aug 21 05:56:17 AM UTC 24
Finished Aug 21 06:09:25 AM UTC 24
Peak memory 212152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1262026020 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1262026020
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/38.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.4207422804
Short name T208
Test name
Test status
Simulation time 143495545695 ps
CPU time 941.33 seconds
Started Aug 21 05:07:44 AM UTC 24
Finished Aug 21 05:23:35 AM UTC 24
Peak memory 212776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4207422804 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.4207422804
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled.4162659000
Short name T297
Test name
Test status
Simulation time 504249671806 ps
CPU time 402.38 seconds
Started Aug 21 06:11:29 AM UTC 24
Finished Aug 21 06:18:16 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4162659000 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.4162659000
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1530409100
Short name T80
Test name
Test status
Simulation time 523719759 ps
CPU time 3.48 seconds
Started Aug 21 05:02:31 AM UTC 24
Finished Aug 21 05:02:35 AM UTC 24
Peak memory 211352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1530409100 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1530409100
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1833495592
Short name T348
Test name
Test status
Simulation time 4387056740 ps
CPU time 4.28 seconds
Started Aug 21 05:03:03 AM UTC 24
Finished Aug 21 05:03:08 AM UTC 24
Peak memory 211364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1833495
592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_tl_intg_err.1833495592
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.3822364811
Short name T203
Test name
Test status
Simulation time 70903368968 ps
CPU time 319.4 seconds
Started Aug 21 05:17:24 AM UTC 24
Finished Aug 21 05:22:47 AM UTC 24
Peak memory 211972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3822364811 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3822364811
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.977445417
Short name T210
Test name
Test status
Simulation time 137299772650 ps
CPU time 564.49 seconds
Started Aug 21 05:20:35 AM UTC 24
Finished Aug 21 05:30:05 AM UTC 24
Peak memory 211900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=977445417 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.977445417
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.1512797349
Short name T259
Test name
Test status
Simulation time 417603947011 ps
CPU time 640.39 seconds
Started Aug 21 05:20:41 AM UTC 24
Finished Aug 21 05:31:28 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1512797349
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_st
ress_all.1512797349
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.1015984910
Short name T213
Test name
Test status
Simulation time 486729029153 ps
CPU time 745.18 seconds
Started Aug 21 05:25:18 AM UTC 24
Finished Aug 21 05:37:51 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1015984910
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_st
ress_all.1015984910
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.2861470093
Short name T292
Test name
Test status
Simulation time 162095383114 ps
CPU time 310.66 seconds
Started Aug 21 05:26:30 AM UTC 24
Finished Aug 21 05:31:44 AM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2861470093 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2861470093
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.2375066592
Short name T281
Test name
Test status
Simulation time 539994027172 ps
CPU time 1509.95 seconds
Started Aug 21 05:29:35 AM UTC 24
Finished Aug 21 05:55:00 AM UTC 24
Peak memory 212624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2375066592 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2375066592
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_fsm_reset.2955392422
Short name T352
Test name
Test status
Simulation time 93589598395 ps
CPU time 391.37 seconds
Started Aug 21 05:30:36 AM UTC 24
Finished Aug 21 05:37:12 AM UTC 24
Peak memory 212036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2955392422 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2955392422
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/21.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.3276584707
Short name T324
Test name
Test status
Simulation time 355930934629 ps
CPU time 921.02 seconds
Started Aug 21 05:37:51 AM UTC 24
Finished Aug 21 05:53:22 AM UTC 24
Peak memory 212760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3276584707 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_c
lock_gating.3276584707
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/26.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_clock_gating.1784834264
Short name T248
Test name
Test status
Simulation time 374953158933 ps
CPU time 1082.79 seconds
Started Aug 21 06:02:26 AM UTC 24
Finished Aug 21 06:20:41 AM UTC 24
Peak memory 212644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1784834264 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_c
lock_gating.1784834264
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/42.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup.2367057999
Short name T338
Test name
Test status
Simulation time 369825129970 ps
CPU time 397.04 seconds
Started Aug 21 06:10:39 AM UTC 24
Finished Aug 21 06:17:21 AM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2367057999 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl
_filters_wakeup.2367057999
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3393332071
Short name T134
Test name
Test status
Simulation time 1209221987 ps
CPU time 8.34 seconds
Started Aug 21 05:02:30 AM UTC 24
Finished Aug 21 05:02:40 AM UTC 24
Peak memory 211352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3393332071
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_
csr_aliasing.3393332071
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2961146295
Short name T132
Test name
Test status
Simulation time 678544820 ps
CPU time 4.17 seconds
Started Aug 21 05:02:27 AM UTC 24
Finished Aug 21 05:02:32 AM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2961146295
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_
csr_hw_reset.2961146295
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2624752095
Short name T75
Test name
Test status
Simulation time 370058208 ps
CPU time 1.5 seconds
Started Aug 21 05:02:31 AM UTC 24
Finished Aug 21 05:02:33 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2624752095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2624752095
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3542479896
Short name T115
Test name
Test status
Simulation time 366858501 ps
CPU time 1.95 seconds
Started Aug 21 05:02:27 AM UTC 24
Finished Aug 21 05:02:30 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3542479896 -asse
rt nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3542479896
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.1987950061
Short name T800
Test name
Test status
Simulation time 381735208 ps
CPU time 1.34 seconds
Started Aug 21 05:02:27 AM UTC 24
Finished Aug 21 05:02:29 AM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1987950061 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1987950061
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.4209118131
Short name T350
Test name
Test status
Simulation time 8312692354 ps
CPU time 35.93 seconds
Started Aug 21 05:02:27 AM UTC 24
Finished Aug 21 05:03:04 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4209118
131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_tl_intg_err.4209118131
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3436029575
Short name T133
Test name
Test status
Simulation time 802709944 ps
CPU time 2.78 seconds
Started Aug 21 05:02:33 AM UTC 24
Finished Aug 21 05:02:37 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3436029575
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_
csr_aliasing.3436029575
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4224285384
Short name T920
Test name
Test status
Simulation time 26159959592 ps
CPU time 110.8 seconds
Started Aug 21 05:02:32 AM UTC 24
Finished Aug 21 05:04:25 AM UTC 24
Peak memory 211448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4224285384
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_
csr_bit_bash.4224285384
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3631656959
Short name T116
Test name
Test status
Simulation time 1373019814 ps
CPU time 3.92 seconds
Started Aug 21 05:02:31 AM UTC 24
Finished Aug 21 05:02:36 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3631656959
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_
csr_hw_reset.3631656959
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.770284878
Short name T84
Test name
Test status
Simulation time 401787489 ps
CPU time 1.59 seconds
Started Aug 21 05:02:35 AM UTC 24
Finished Aug 21 05:02:38 AM UTC 24
Peak memory 209856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=770284878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.770284878
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2268383143
Short name T117
Test name
Test status
Simulation time 438127082 ps
CPU time 2.95 seconds
Started Aug 21 05:02:32 AM UTC 24
Finished Aug 21 05:02:36 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2268383143 -asse
rt nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2268383143
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.3153778022
Short name T801
Test name
Test status
Simulation time 385299198 ps
CPU time 1.31 seconds
Started Aug 21 05:02:31 AM UTC 24
Finished Aug 21 05:02:33 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3153778022 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3153778022
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1334608809
Short name T67
Test name
Test status
Simulation time 5241998361 ps
CPU time 15.28 seconds
Started Aug 21 05:02:35 AM UTC 24
Finished Aug 21 05:02:51 AM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=1334608809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.adc_ctrl_same_csr_outstanding.1334608809
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1136657315
Short name T70
Test name
Test status
Simulation time 3965235328 ps
CPU time 5.86 seconds
Started Aug 21 05:02:31 AM UTC 24
Finished Aug 21 05:02:38 AM UTC 24
Peak memory 211452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1136657
315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_tl_intg_err.1136657315
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3715944938
Short name T829
Test name
Test status
Simulation time 582391436 ps
CPU time 1.32 seconds
Started Aug 21 05:02:57 AM UTC 24
Finished Aug 21 05:03:00 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3715944938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3715944938
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2936545950
Short name T831
Test name
Test status
Simulation time 528755115 ps
CPU time 2.19 seconds
Started Aug 21 05:02:57 AM UTC 24
Finished Aug 21 05:03:00 AM UTC 24
Peak memory 211224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2936545950 -asse
rt nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2936545950
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.4278933021
Short name T830
Test name
Test status
Simulation time 510957472 ps
CPU time 3.03 seconds
Started Aug 21 05:02:56 AM UTC 24
Finished Aug 21 05:03:00 AM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4278933021 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.4278933021
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2405203995
Short name T835
Test name
Test status
Simulation time 4038407581 ps
CPU time 3.48 seconds
Started Aug 21 05:02:57 AM UTC 24
Finished Aug 21 05:03:02 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=2405203995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.adc_ctrl_same_csr_outstanding.2405203995
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.457054917
Short name T826
Test name
Test status
Simulation time 348568689 ps
CPU time 1.68 seconds
Started Aug 21 05:02:56 AM UTC 24
Finished Aug 21 05:02:59 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=457054917 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.457054917
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3992408176
Short name T910
Test name
Test status
Simulation time 8015228646 ps
CPU time 20.83 seconds
Started Aug 21 05:02:56 AM UTC 24
Finished Aug 21 05:03:18 AM UTC 24
Peak memory 211624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3992408
176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_tl_intg_err.3992408176
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.182865455
Short name T838
Test name
Test status
Simulation time 880008793 ps
CPU time 1.53 seconds
Started Aug 21 05:03:01 AM UTC 24
Finished Aug 21 05:03:03 AM UTC 24
Peak memory 220420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=182865455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.182865455
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3669951820
Short name T125
Test name
Test status
Simulation time 351919616 ps
CPU time 2.2 seconds
Started Aug 21 05:02:59 AM UTC 24
Finished Aug 21 05:03:02 AM UTC 24
Peak memory 211224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3669951820 -asse
rt nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3669951820
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.945396201
Short name T833
Test name
Test status
Simulation time 413698731 ps
CPU time 1.77 seconds
Started Aug 21 05:02:59 AM UTC 24
Finished Aug 21 05:03:01 AM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=945396201 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.945396201
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2077574424
Short name T873
Test name
Test status
Simulation time 2729761032 ps
CPU time 11.01 seconds
Started Aug 21 05:03:01 AM UTC 24
Finished Aug 21 05:03:13 AM UTC 24
Peak memory 211268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=2077574424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.adc_ctrl_same_csr_outstanding.2077574424
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3141585511
Short name T834
Test name
Test status
Simulation time 1082787323 ps
CPU time 3.35 seconds
Started Aug 21 05:02:57 AM UTC 24
Finished Aug 21 05:03:02 AM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3141585511 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3141585511
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2375000160
Short name T87
Test name
Test status
Simulation time 8375552821 ps
CPU time 13.15 seconds
Started Aug 21 05:02:58 AM UTC 24
Finished Aug 21 05:03:13 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2375000
160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_tl_intg_err.2375000160
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2841661812
Short name T839
Test name
Test status
Simulation time 457411695 ps
CPU time 1.37 seconds
Started Aug 21 05:03:01 AM UTC 24
Finished Aug 21 05:03:03 AM UTC 24
Peak memory 209920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2841661812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2841661812
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2294513075
Short name T127
Test name
Test status
Simulation time 528565187 ps
CPU time 1.58 seconds
Started Aug 21 05:03:01 AM UTC 24
Finished Aug 21 05:03:03 AM UTC 24
Peak memory 209920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2294513075 -asse
rt nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2294513075
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.2872565845
Short name T837
Test name
Test status
Simulation time 388888235 ps
CPU time 1.17 seconds
Started Aug 21 05:03:01 AM UTC 24
Finished Aug 21 05:03:03 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2872565845 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2872565845
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4134471579
Short name T845
Test name
Test status
Simulation time 2059110592 ps
CPU time 3.2 seconds
Started Aug 21 05:03:01 AM UTC 24
Finished Aug 21 05:03:05 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=4134471579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
12.adc_ctrl_same_csr_outstanding.4134471579
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2755170623
Short name T840
Test name
Test status
Simulation time 827221896 ps
CPU time 2.49 seconds
Started Aug 21 05:03:01 AM UTC 24
Finished Aug 21 05:03:04 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2755170623 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2755170623
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.355711304
Short name T849
Test name
Test status
Simulation time 9131161048 ps
CPU time 4.7 seconds
Started Aug 21 05:03:01 AM UTC 24
Finished Aug 21 05:03:06 AM UTC 24
Peak memory 211624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3557113
04 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ct
rl_tl_intg_err.355711304
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4188175191
Short name T848
Test name
Test status
Simulation time 420468472 ps
CPU time 2.67 seconds
Started Aug 21 05:03:03 AM UTC 24
Finished Aug 21 05:03:06 AM UTC 24
Peak memory 211312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=4188175191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.4188175191
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3261113913
Short name T126
Test name
Test status
Simulation time 503197923 ps
CPU time 1.49 seconds
Started Aug 21 05:03:03 AM UTC 24
Finished Aug 21 05:03:05 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3261113913 -asse
rt nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3261113913
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2896989183
Short name T843
Test name
Test status
Simulation time 559944551 ps
CPU time 1.53 seconds
Started Aug 21 05:03:02 AM UTC 24
Finished Aug 21 05:03:05 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2896989183 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2896989183
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.846912473
Short name T864
Test name
Test status
Simulation time 4849517390 ps
CPU time 6.49 seconds
Started Aug 21 05:03:03 AM UTC 24
Finished Aug 21 05:03:10 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=846912473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
13.adc_ctrl_same_csr_outstanding.846912473
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1582272668
Short name T844
Test name
Test status
Simulation time 543846442 ps
CPU time 3.03 seconds
Started Aug 21 05:03:01 AM UTC 24
Finished Aug 21 05:03:05 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1582272668 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1582272668
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2391989483
Short name T906
Test name
Test status
Simulation time 4805107048 ps
CPU time 13.82 seconds
Started Aug 21 05:03:02 AM UTC 24
Finished Aug 21 05:03:17 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2391989
483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_tl_intg_err.2391989483
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.574762324
Short name T851
Test name
Test status
Simulation time 667547479 ps
CPU time 1.65 seconds
Started Aug 21 05:03:04 AM UTC 24
Finished Aug 21 05:03:07 AM UTC 24
Peak memory 210044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=574762324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.574762324
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3169542415
Short name T846
Test name
Test status
Simulation time 527020279 ps
CPU time 2.12 seconds
Started Aug 21 05:03:03 AM UTC 24
Finished Aug 21 05:03:06 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3169542415 -asse
rt nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3169542415
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2763420459
Short name T847
Test name
Test status
Simulation time 458056111 ps
CPU time 2.11 seconds
Started Aug 21 05:03:03 AM UTC 24
Finished Aug 21 05:03:06 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2763420459 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2763420459
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3741679959
Short name T856
Test name
Test status
Simulation time 3625411584 ps
CPU time 4.26 seconds
Started Aug 21 05:03:03 AM UTC 24
Finished Aug 21 05:03:08 AM UTC 24
Peak memory 211588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=3741679959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
14.adc_ctrl_same_csr_outstanding.3741679959
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2617475170
Short name T850
Test name
Test status
Simulation time 737895877 ps
CPU time 2.99 seconds
Started Aug 21 05:03:03 AM UTC 24
Finished Aug 21 05:03:07 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2617475170 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2617475170
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3268723518
Short name T854
Test name
Test status
Simulation time 638357887 ps
CPU time 1.26 seconds
Started Aug 21 05:03:05 AM UTC 24
Finished Aug 21 05:03:08 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3268723518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3268723518
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3000203457
Short name T853
Test name
Test status
Simulation time 330632048 ps
CPU time 2.12 seconds
Started Aug 21 05:03:04 AM UTC 24
Finished Aug 21 05:03:08 AM UTC 24
Peak memory 211224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3000203457 -asse
rt nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3000203457
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.2498933373
Short name T852
Test name
Test status
Simulation time 355394122 ps
CPU time 2.2 seconds
Started Aug 21 05:03:04 AM UTC 24
Finished Aug 21 05:03:08 AM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2498933373 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2498933373
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2530224867
Short name T866
Test name
Test status
Simulation time 4432605844 ps
CPU time 4.12 seconds
Started Aug 21 05:03:05 AM UTC 24
Finished Aug 21 05:03:11 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=2530224867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
15.adc_ctrl_same_csr_outstanding.2530224867
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.875103218
Short name T855
Test name
Test status
Simulation time 729160792 ps
CPU time 2.73 seconds
Started Aug 21 05:03:04 AM UTC 24
Finished Aug 21 05:03:08 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=875103218 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.875103218
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1978972927
Short name T918
Test name
Test status
Simulation time 8615106440 ps
CPU time 18.98 seconds
Started Aug 21 05:03:04 AM UTC 24
Finished Aug 21 05:03:24 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1978972
927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_tl_intg_err.1978972927
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.255713003
Short name T860
Test name
Test status
Simulation time 522308440 ps
CPU time 2.38 seconds
Started Aug 21 05:03:06 AM UTC 24
Finished Aug 21 05:03:09 AM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=255713003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.255713003
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2787146583
Short name T859
Test name
Test status
Simulation time 465758019 ps
CPU time 1.96 seconds
Started Aug 21 05:03:06 AM UTC 24
Finished Aug 21 05:03:09 AM UTC 24
Peak memory 210044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2787146583 -asse
rt nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2787146583
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.1207722412
Short name T857
Test name
Test status
Simulation time 384731853 ps
CPU time 1.61 seconds
Started Aug 21 05:03:06 AM UTC 24
Finished Aug 21 05:03:08 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1207722412 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1207722412
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.808668467
Short name T889
Test name
Test status
Simulation time 2321280618 ps
CPU time 8.01 seconds
Started Aug 21 05:03:06 AM UTC 24
Finished Aug 21 05:03:15 AM UTC 24
Peak memory 211384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=808668467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.adc_ctrl_same_csr_outstanding.808668467
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.916258105
Short name T858
Test name
Test status
Simulation time 426812735 ps
CPU time 1.74 seconds
Started Aug 21 05:03:06 AM UTC 24
Finished Aug 21 05:03:08 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=916258105 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.916258105
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2054984191
Short name T898
Test name
Test status
Simulation time 3964932640 ps
CPU time 10.27 seconds
Started Aug 21 05:03:06 AM UTC 24
Finished Aug 21 05:03:17 AM UTC 24
Peak memory 211448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2054984
191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_tl_intg_err.2054984191
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.134066095
Short name T862
Test name
Test status
Simulation time 363319084 ps
CPU time 1.35 seconds
Started Aug 21 05:03:08 AM UTC 24
Finished Aug 21 05:03:10 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=134066095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.134066095
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.273981790
Short name T861
Test name
Test status
Simulation time 500841156 ps
CPU time 1.37 seconds
Started Aug 21 05:03:07 AM UTC 24
Finished Aug 21 05:03:10 AM UTC 24
Peak memory 209924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=273981790 -asser
t nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.273981790
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.3580303640
Short name T863
Test name
Test status
Simulation time 392877603 ps
CPU time 1.57 seconds
Started Aug 21 05:03:07 AM UTC 24
Finished Aug 21 05:03:10 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3580303640 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3580303640
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3973094742
Short name T888
Test name
Test status
Simulation time 4303807681 ps
CPU time 5.87 seconds
Started Aug 21 05:03:08 AM UTC 24
Finished Aug 21 05:03:15 AM UTC 24
Peak memory 211628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=3973094742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
17.adc_ctrl_same_csr_outstanding.3973094742
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2245930599
Short name T869
Test name
Test status
Simulation time 833254108 ps
CPU time 2.75 seconds
Started Aug 21 05:03:07 AM UTC 24
Finished Aug 21 05:03:11 AM UTC 24
Peak memory 221512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2245930599 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2245930599
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1952973889
Short name T349
Test name
Test status
Simulation time 4269201081 ps
CPU time 6.98 seconds
Started Aug 21 05:03:07 AM UTC 24
Finished Aug 21 05:03:15 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1952973
889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_tl_intg_err.1952973889
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.103074019
Short name T876
Test name
Test status
Simulation time 453516349 ps
CPU time 3.13 seconds
Started Aug 21 05:03:09 AM UTC 24
Finished Aug 21 05:03:13 AM UTC 24
Peak memory 211268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=103074019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.103074019
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3540010950
Short name T868
Test name
Test status
Simulation time 489700343 ps
CPU time 1.1 seconds
Started Aug 21 05:03:09 AM UTC 24
Finished Aug 21 05:03:11 AM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3540010950 -asse
rt nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3540010950
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.2638154556
Short name T867
Test name
Test status
Simulation time 354617711 ps
CPU time 1.12 seconds
Started Aug 21 05:03:09 AM UTC 24
Finished Aug 21 05:03:11 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2638154556 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2638154556
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1682678414
Short name T915
Test name
Test status
Simulation time 4534798466 ps
CPU time 9.11 seconds
Started Aug 21 05:03:09 AM UTC 24
Finished Aug 21 05:03:19 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=1682678414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.adc_ctrl_same_csr_outstanding.1682678414
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.123612706
Short name T865
Test name
Test status
Simulation time 747428973 ps
CPU time 1.76 seconds
Started Aug 21 05:03:08 AM UTC 24
Finished Aug 21 05:03:10 AM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=123612706 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.123612706
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1500985235
Short name T908
Test name
Test status
Simulation time 8668679732 ps
CPU time 8.89 seconds
Started Aug 21 05:03:08 AM UTC 24
Finished Aug 21 05:03:18 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1500985
235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_tl_intg_err.1500985235
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2348516390
Short name T875
Test name
Test status
Simulation time 555204552 ps
CPU time 1.6 seconds
Started Aug 21 05:03:10 AM UTC 24
Finished Aug 21 05:03:13 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2348516390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2348516390
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1186528903
Short name T872
Test name
Test status
Simulation time 519251158 ps
CPU time 1.88 seconds
Started Aug 21 05:03:09 AM UTC 24
Finished Aug 21 05:03:12 AM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1186528903 -asse
rt nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1186528903
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2114848489
Short name T871
Test name
Test status
Simulation time 381369301 ps
CPU time 1.78 seconds
Started Aug 21 05:03:09 AM UTC 24
Finished Aug 21 05:03:12 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2114848489 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2114848489
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.430023506
Short name T909
Test name
Test status
Simulation time 2676601533 ps
CPU time 6.7 seconds
Started Aug 21 05:03:10 AM UTC 24
Finished Aug 21 05:03:18 AM UTC 24
Peak memory 211268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=430023506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
19.adc_ctrl_same_csr_outstanding.430023506
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1596005652
Short name T870
Test name
Test status
Simulation time 559309131 ps
CPU time 1.81 seconds
Started Aug 21 05:03:09 AM UTC 24
Finished Aug 21 05:03:12 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1596005652 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1596005652
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1260866283
Short name T887
Test name
Test status
Simulation time 4545913162 ps
CPU time 4.41 seconds
Started Aug 21 05:03:09 AM UTC 24
Finished Aug 21 05:03:14 AM UTC 24
Peak memory 211464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1260866
283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_tl_intg_err.1260866283
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1366069001
Short name T120
Test name
Test status
Simulation time 1475655642 ps
CPU time 3.68 seconds
Started Aug 21 05:02:39 AM UTC 24
Finished Aug 21 05:02:44 AM UTC 24
Peak memory 211436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1366069001
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_
csr_aliasing.1366069001
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1844531717
Short name T832
Test name
Test status
Simulation time 25862943718 ps
CPU time 20.46 seconds
Started Aug 21 05:02:39 AM UTC 24
Finished Aug 21 05:03:01 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1844531717
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_
csr_bit_bash.1844531717
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1048508261
Short name T118
Test name
Test status
Simulation time 1265533859 ps
CPU time 3.44 seconds
Started Aug 21 05:02:36 AM UTC 24
Finished Aug 21 05:02:41 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1048508261
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_
csr_hw_reset.1048508261
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2435309241
Short name T104
Test name
Test status
Simulation time 535109800 ps
CPU time 3.65 seconds
Started Aug 21 05:02:39 AM UTC 24
Finished Aug 21 05:02:44 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2435309241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2435309241
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.838247650
Short name T119
Test name
Test status
Simulation time 359478472 ps
CPU time 2.55 seconds
Started Aug 21 05:02:37 AM UTC 24
Finished Aug 21 05:02:41 AM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=838247650 -asser
t nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.838247650
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.680112988
Short name T802
Test name
Test status
Simulation time 527953471 ps
CPU time 2.62 seconds
Started Aug 21 05:02:36 AM UTC 24
Finished Aug 21 05:02:40 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=680112988 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.680112988
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.548284835
Short name T65
Test name
Test status
Simulation time 2197029612 ps
CPU time 4.23 seconds
Started Aug 21 05:02:39 AM UTC 24
Finished Aug 21 05:02:44 AM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=548284835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.adc_ctrl_same_csr_outstanding.548284835
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3751341927
Short name T81
Test name
Test status
Simulation time 422514518 ps
CPU time 3.92 seconds
Started Aug 21 05:02:35 AM UTC 24
Finished Aug 21 05:02:40 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3751341927 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3751341927
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1912568298
Short name T71
Test name
Test status
Simulation time 4719111130 ps
CPU time 4.83 seconds
Started Aug 21 05:02:36 AM UTC 24
Finished Aug 21 05:02:42 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1912568
298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_tl_intg_err.1912568298
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.1791404778
Short name T883
Test name
Test status
Simulation time 464379884 ps
CPU time 2.69 seconds
Started Aug 21 05:03:10 AM UTC 24
Finished Aug 21 05:03:14 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1791404778 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1791404778
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/20.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.2974929027
Short name T881
Test name
Test status
Simulation time 375196116 ps
CPU time 2.34 seconds
Started Aug 21 05:03:10 AM UTC 24
Finished Aug 21 05:03:14 AM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2974929027 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2974929027
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/21.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.509459273
Short name T874
Test name
Test status
Simulation time 491089208 ps
CPU time 1.34 seconds
Started Aug 21 05:03:10 AM UTC 24
Finished Aug 21 05:03:13 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=509459273 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.509459273
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/22.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.789382306
Short name T877
Test name
Test status
Simulation time 400817682 ps
CPU time 1.87 seconds
Started Aug 21 05:03:10 AM UTC 24
Finished Aug 21 05:03:13 AM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=789382306 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.789382306
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/23.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.1727870493
Short name T884
Test name
Test status
Simulation time 556536452 ps
CPU time 1.52 seconds
Started Aug 21 05:03:12 AM UTC 24
Finished Aug 21 05:03:14 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1727870493 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1727870493
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/24.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.1345630792
Short name T885
Test name
Test status
Simulation time 282989146 ps
CPU time 1.77 seconds
Started Aug 21 05:03:12 AM UTC 24
Finished Aug 21 05:03:14 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1345630792 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1345630792
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/25.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.2103386342
Short name T878
Test name
Test status
Simulation time 346735216 ps
CPU time 0.9 seconds
Started Aug 21 05:03:12 AM UTC 24
Finished Aug 21 05:03:14 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2103386342 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2103386342
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/26.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.3976582680
Short name T879
Test name
Test status
Simulation time 444752636 ps
CPU time 0.99 seconds
Started Aug 21 05:03:12 AM UTC 24
Finished Aug 21 05:03:14 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3976582680 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3976582680
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/27.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.2401347409
Short name T880
Test name
Test status
Simulation time 416091310 ps
CPU time 0.96 seconds
Started Aug 21 05:03:12 AM UTC 24
Finished Aug 21 05:03:14 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2401347409 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2401347409
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/28.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.2014159289
Short name T886
Test name
Test status
Simulation time 425607509 ps
CPU time 1.62 seconds
Started Aug 21 05:03:12 AM UTC 24
Finished Aug 21 05:03:14 AM UTC 24
Peak memory 209920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2014159289 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2014159289
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/29.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1869451216
Short name T121
Test name
Test status
Simulation time 1735160017 ps
CPU time 3.31 seconds
Started Aug 21 05:02:43 AM UTC 24
Finished Aug 21 05:02:47 AM UTC 24
Peak memory 211436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1869451216
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_
csr_aliasing.1869451216
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1388681323
Short name T919
Test name
Test status
Simulation time 25886176599 ps
CPU time 55.99 seconds
Started Aug 21 05:02:41 AM UTC 24
Finished Aug 21 05:03:39 AM UTC 24
Peak memory 211716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1388681323
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_
csr_bit_bash.1388681323
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1324367705
Short name T804
Test name
Test status
Simulation time 778769038 ps
CPU time 4.3 seconds
Started Aug 21 05:02:41 AM UTC 24
Finished Aug 21 05:02:47 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1324367705
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_
csr_hw_reset.1324367705
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.824618384
Short name T105
Test name
Test status
Simulation time 578608759 ps
CPU time 1.94 seconds
Started Aug 21 05:02:43 AM UTC 24
Finished Aug 21 05:02:46 AM UTC 24
Peak memory 220572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=824618384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.824618384
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.636540088
Short name T128
Test name
Test status
Simulation time 435924047 ps
CPU time 2.71 seconds
Started Aug 21 05:02:41 AM UTC 24
Finished Aug 21 05:02:45 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=636540088 -asser
t nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.636540088
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.3683147032
Short name T803
Test name
Test status
Simulation time 634390356 ps
CPU time 1.05 seconds
Started Aug 21 05:02:41 AM UTC 24
Finished Aug 21 05:02:43 AM UTC 24
Peak memory 209440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3683147032 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3683147032
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3689194997
Short name T836
Test name
Test status
Simulation time 4940044432 ps
CPU time 17.84 seconds
Started Aug 21 05:02:43 AM UTC 24
Finished Aug 21 05:03:02 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=3689194997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.adc_ctrl_same_csr_outstanding.3689194997
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1100847344
Short name T82
Test name
Test status
Simulation time 481065137 ps
CPU time 1.73 seconds
Started Aug 21 05:02:39 AM UTC 24
Finished Aug 21 05:02:42 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1100847344 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1100847344
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4220787820
Short name T72
Test name
Test status
Simulation time 8218527886 ps
CPU time 6.51 seconds
Started Aug 21 05:02:41 AM UTC 24
Finished Aug 21 05:02:49 AM UTC 24
Peak memory 211508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4220787
820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_tl_intg_err.4220787820
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.845086636
Short name T882
Test name
Test status
Simulation time 441724367 ps
CPU time 0.98 seconds
Started Aug 21 05:03:12 AM UTC 24
Finished Aug 21 05:03:14 AM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=845086636 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.845086636
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/30.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.222058513
Short name T890
Test name
Test status
Simulation time 427751108 ps
CPU time 1.31 seconds
Started Aug 21 05:03:13 AM UTC 24
Finished Aug 21 05:03:15 AM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=222058513 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.222058513
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/31.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.3261637159
Short name T891
Test name
Test status
Simulation time 397635868 ps
CPU time 1.59 seconds
Started Aug 21 05:03:13 AM UTC 24
Finished Aug 21 05:03:16 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3261637159 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3261637159
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/32.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.3341432770
Short name T892
Test name
Test status
Simulation time 460648338 ps
CPU time 1.97 seconds
Started Aug 21 05:03:13 AM UTC 24
Finished Aug 21 05:03:16 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3341432770 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3341432770
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/33.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.604532690
Short name T893
Test name
Test status
Simulation time 317922427 ps
CPU time 0.96 seconds
Started Aug 21 05:03:14 AM UTC 24
Finished Aug 21 05:03:16 AM UTC 24
Peak memory 210240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=604532690 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.604532690
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/34.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.370407005
Short name T895
Test name
Test status
Simulation time 473005487 ps
CPU time 1.27 seconds
Started Aug 21 05:03:14 AM UTC 24
Finished Aug 21 05:03:17 AM UTC 24
Peak memory 210128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=370407005 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.370407005
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/35.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.2169056274
Short name T894
Test name
Test status
Simulation time 512427343 ps
CPU time 1.01 seconds
Started Aug 21 05:03:14 AM UTC 24
Finished Aug 21 05:03:16 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2169056274 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2169056274
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/36.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.124179900
Short name T901
Test name
Test status
Simulation time 350027453 ps
CPU time 1.67 seconds
Started Aug 21 05:03:14 AM UTC 24
Finished Aug 21 05:03:17 AM UTC 24
Peak memory 209856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=124179900 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.124179900
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/37.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.1348357890
Short name T902
Test name
Test status
Simulation time 447879542 ps
CPU time 1.8 seconds
Started Aug 21 05:03:14 AM UTC 24
Finished Aug 21 05:03:17 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1348357890 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1348357890
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/38.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.2681601306
Short name T897
Test name
Test status
Simulation time 387548736 ps
CPU time 1.42 seconds
Started Aug 21 05:03:15 AM UTC 24
Finished Aug 21 05:03:17 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2681601306 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2681601306
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/39.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.437039647
Short name T66
Test name
Test status
Simulation time 1544735911 ps
CPU time 3.8 seconds
Started Aug 21 05:02:46 AM UTC 24
Finished Aug 21 05:02:51 AM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=437039647
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_c
sr_aliasing.437039647
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.188489967
Short name T916
Test name
Test status
Simulation time 26945131067 ps
CPU time 32.01 seconds
Started Aug 21 05:02:46 AM UTC 24
Finished Aug 21 05:03:19 AM UTC 24
Peak memory 211568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=188489967
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_c
sr_bit_bash.188489967
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.996983964
Short name T806
Test name
Test status
Simulation time 872582235 ps
CPU time 1.81 seconds
Started Aug 21 05:02:46 AM UTC 24
Finished Aug 21 05:02:49 AM UTC 24
Peak memory 209668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=996983964
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_c
sr_hw_reset.996983964
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.948853471
Short name T85
Test name
Test status
Simulation time 551279766 ps
CPU time 2.32 seconds
Started Aug 21 05:02:46 AM UTC 24
Finished Aug 21 05:02:49 AM UTC 24
Peak memory 223520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=948853471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.948853471
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3677928168
Short name T122
Test name
Test status
Simulation time 493351098 ps
CPU time 1.3 seconds
Started Aug 21 05:02:46 AM UTC 24
Finished Aug 21 05:02:48 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3677928168 -asse
rt nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3677928168
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.2973605827
Short name T805
Test name
Test status
Simulation time 394924834 ps
CPU time 1.31 seconds
Started Aug 21 05:02:46 AM UTC 24
Finished Aug 21 05:02:48 AM UTC 24
Peak memory 209792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2973605827 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2973605827
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1093641688
Short name T828
Test name
Test status
Simulation time 2387873263 ps
CPU time 12.19 seconds
Started Aug 21 05:02:46 AM UTC 24
Finished Aug 21 05:02:59 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=1093641688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.adc_ctrl_same_csr_outstanding.1093641688
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2920639454
Short name T83
Test name
Test status
Simulation time 624768698 ps
CPU time 2.39 seconds
Started Aug 21 05:02:43 AM UTC 24
Finished Aug 21 05:02:46 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2920639454 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2920639454
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.3189962861
Short name T896
Test name
Test status
Simulation time 390057773 ps
CPU time 1.27 seconds
Started Aug 21 05:03:15 AM UTC 24
Finished Aug 21 05:03:17 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3189962861 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3189962861
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/40.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.90174789
Short name T899
Test name
Test status
Simulation time 374197227 ps
CPU time 1.42 seconds
Started Aug 21 05:03:15 AM UTC 24
Finished Aug 21 05:03:17 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=90174789 -assert no
postproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.90174789
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/41.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.3940940310
Short name T903
Test name
Test status
Simulation time 440565549 ps
CPU time 1.66 seconds
Started Aug 21 05:03:15 AM UTC 24
Finished Aug 21 05:03:17 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3940940310 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3940940310
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/42.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.3258945768
Short name T904
Test name
Test status
Simulation time 298196047 ps
CPU time 1.58 seconds
Started Aug 21 05:03:15 AM UTC 24
Finished Aug 21 05:03:17 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3258945768 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3258945768
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/43.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.900813199
Short name T900
Test name
Test status
Simulation time 535929302 ps
CPU time 1.29 seconds
Started Aug 21 05:03:15 AM UTC 24
Finished Aug 21 05:03:17 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=900813199 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.900813199
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/44.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.3088903132
Short name T905
Test name
Test status
Simulation time 360469337 ps
CPU time 1.51 seconds
Started Aug 21 05:03:15 AM UTC 24
Finished Aug 21 05:03:17 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3088903132 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3088903132
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/45.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.225881539
Short name T911
Test name
Test status
Simulation time 360518180 ps
CPU time 1.39 seconds
Started Aug 21 05:03:16 AM UTC 24
Finished Aug 21 05:03:19 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=225881539 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.225881539
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/46.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.428719648
Short name T914
Test name
Test status
Simulation time 323179729 ps
CPU time 1.58 seconds
Started Aug 21 05:03:16 AM UTC 24
Finished Aug 21 05:03:19 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=428719648 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.428719648
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/47.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.840156632
Short name T912
Test name
Test status
Simulation time 339726933 ps
CPU time 1.38 seconds
Started Aug 21 05:03:16 AM UTC 24
Finished Aug 21 05:03:19 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=840156632 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.840156632
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/48.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.2745311571
Short name T913
Test name
Test status
Simulation time 279265690 ps
CPU time 1.35 seconds
Started Aug 21 05:03:16 AM UTC 24
Finished Aug 21 05:03:19 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2745311571 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2745311571
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/49.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1217801108
Short name T808
Test name
Test status
Simulation time 583835605 ps
CPU time 2 seconds
Started Aug 21 05:02:48 AM UTC 24
Finished Aug 21 05:02:51 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1217801108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1217801108
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.286912411
Short name T129
Test name
Test status
Simulation time 325171910 ps
CPU time 1.43 seconds
Started Aug 21 05:02:48 AM UTC 24
Finished Aug 21 05:02:50 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=286912411 -asser
t nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.286912411
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.2695954709
Short name T807
Test name
Test status
Simulation time 507071413 ps
CPU time 0.96 seconds
Started Aug 21 05:02:48 AM UTC 24
Finished Aug 21 05:02:50 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2695954709 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2695954709
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.662662543
Short name T130
Test name
Test status
Simulation time 2348334331 ps
CPU time 3.93 seconds
Started Aug 21 05:02:48 AM UTC 24
Finished Aug 21 05:02:53 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=662662543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
5.adc_ctrl_same_csr_outstanding.662662543
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2631498878
Short name T811
Test name
Test status
Simulation time 412561551 ps
CPU time 4.8 seconds
Started Aug 21 05:02:46 AM UTC 24
Finished Aug 21 05:02:52 AM UTC 24
Peak memory 227488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2631498878 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2631498878
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.210629285
Short name T77
Test name
Test status
Simulation time 8778008556 ps
CPU time 8.6 seconds
Started Aug 21 05:02:48 AM UTC 24
Finished Aug 21 05:02:57 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2106292
85 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctr
l_tl_intg_err.210629285
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2760694932
Short name T815
Test name
Test status
Simulation time 402414748 ps
CPU time 3.19 seconds
Started Aug 21 05:02:51 AM UTC 24
Finished Aug 21 05:02:55 AM UTC 24
Peak memory 211268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2760694932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2760694932
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1695499797
Short name T812
Test name
Test status
Simulation time 570777646 ps
CPU time 2.51 seconds
Started Aug 21 05:02:49 AM UTC 24
Finished Aug 21 05:02:53 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1695499797 -asse
rt nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1695499797
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.4185526379
Short name T810
Test name
Test status
Simulation time 303309256 ps
CPU time 1.28 seconds
Started Aug 21 05:02:49 AM UTC 24
Finished Aug 21 05:02:51 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4185526379 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.4185526379
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3963889255
Short name T131
Test name
Test status
Simulation time 4316524037 ps
CPU time 5.46 seconds
Started Aug 21 05:02:49 AM UTC 24
Finished Aug 21 05:02:56 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=3963889255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.adc_ctrl_same_csr_outstanding.3963889255
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3795303321
Short name T809
Test name
Test status
Simulation time 592815665 ps
CPU time 2.32 seconds
Started Aug 21 05:02:48 AM UTC 24
Finished Aug 21 05:02:51 AM UTC 24
Peak memory 211452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3795303321 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3795303321
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3772494147
Short name T76
Test name
Test status
Simulation time 4531363237 ps
CPU time 4.59 seconds
Started Aug 21 05:02:49 AM UTC 24
Finished Aug 21 05:02:55 AM UTC 24
Peak memory 211644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3772494
147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_tl_intg_err.3772494147
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3581116488
Short name T814
Test name
Test status
Simulation time 539098992 ps
CPU time 1.2 seconds
Started Aug 21 05:02:52 AM UTC 24
Finished Aug 21 05:02:55 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3581116488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3581116488
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.305701811
Short name T818
Test name
Test status
Simulation time 429937155 ps
CPU time 1.93 seconds
Started Aug 21 05:02:52 AM UTC 24
Finished Aug 21 05:02:55 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=305701811 -asser
t nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.305701811
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.250385932
Short name T813
Test name
Test status
Simulation time 481311865 ps
CPU time 1.29 seconds
Started Aug 21 05:02:51 AM UTC 24
Finished Aug 21 05:02:53 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=250385932 -assert n
opostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.250385932
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3368219499
Short name T825
Test name
Test status
Simulation time 2168386912 ps
CPU time 5.08 seconds
Started Aug 21 05:02:52 AM UTC 24
Finished Aug 21 05:02:58 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=3368219499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
7.adc_ctrl_same_csr_outstanding.3368219499
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1259044305
Short name T816
Test name
Test status
Simulation time 355693658 ps
CPU time 3.22 seconds
Started Aug 21 05:02:51 AM UTC 24
Finished Aug 21 05:02:55 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1259044305 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1259044305
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2644241441
Short name T842
Test name
Test status
Simulation time 4657237182 ps
CPU time 12.93 seconds
Started Aug 21 05:02:51 AM UTC 24
Finished Aug 21 05:03:05 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2644241
441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_tl_intg_err.2644241441
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1732187693
Short name T819
Test name
Test status
Simulation time 572327864 ps
CPU time 1.55 seconds
Started Aug 21 05:02:54 AM UTC 24
Finished Aug 21 05:02:56 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1732187693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1732187693
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.459585932
Short name T124
Test name
Test status
Simulation time 366253407 ps
CPU time 1.8 seconds
Started Aug 21 05:02:53 AM UTC 24
Finished Aug 21 05:02:55 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=459585932 -asser
t nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.459585932
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.2182959842
Short name T817
Test name
Test status
Simulation time 408449096 ps
CPU time 1.56 seconds
Started Aug 21 05:02:53 AM UTC 24
Finished Aug 21 05:02:55 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2182959842 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2182959842
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.768008878
Short name T821
Test name
Test status
Simulation time 2515756188 ps
CPU time 2.14 seconds
Started Aug 21 05:02:54 AM UTC 24
Finished Aug 21 05:02:57 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=768008878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
8.adc_ctrl_same_csr_outstanding.768008878
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2130619716
Short name T820
Test name
Test status
Simulation time 442696793 ps
CPU time 2.85 seconds
Started Aug 21 05:02:52 AM UTC 24
Finished Aug 21 05:02:56 AM UTC 24
Peak memory 211580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2130619716 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2130619716
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2091763063
Short name T917
Test name
Test status
Simulation time 8606905969 ps
CPU time 26.02 seconds
Started Aug 21 05:02:53 AM UTC 24
Finished Aug 21 05:03:20 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2091763
063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_tl_intg_err.2091763063
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.598720061
Short name T827
Test name
Test status
Simulation time 426140413 ps
CPU time 1.78 seconds
Started Aug 21 05:02:56 AM UTC 24
Finished Aug 21 05:02:59 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=598720061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.598720061
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3175573499
Short name T824
Test name
Test status
Simulation time 437303115 ps
CPU time 1.29 seconds
Started Aug 21 05:02:56 AM UTC 24
Finished Aug 21 05:02:58 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3175573499 -asse
rt nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3175573499
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.2660533198
Short name T823
Test name
Test status
Simulation time 329515066 ps
CPU time 0.94 seconds
Started Aug 21 05:02:56 AM UTC 24
Finished Aug 21 05:02:58 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2660533198 -assert
nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2660533198
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3784648501
Short name T841
Test name
Test status
Simulation time 4699925626 ps
CPU time 7.18 seconds
Started Aug 21 05:02:56 AM UTC 24
Finished Aug 21 05:03:04 AM UTC 24
Peak memory 211628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=3784648501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
9.adc_ctrl_same_csr_outstanding.3784648501
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.59475260
Short name T822
Test name
Test status
Simulation time 749392034 ps
CPU time 3.04 seconds
Started Aug 21 05:02:54 AM UTC 24
Finished Aug 21 05:02:58 AM UTC 24
Peak memory 211384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=59475260 -assert no
postproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.59475260
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1733379712
Short name T907
Test name
Test status
Simulation time 7925676274 ps
CPU time 20.39 seconds
Started Aug 21 05:02:55 AM UTC 24
Finished Aug 21 05:03:17 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1733379
712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_tl_intg_err.1733379712
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.2782229994
Short name T135
Test name
Test status
Simulation time 411228915523 ps
CPU time 170.54 seconds
Started Aug 21 05:07:11 AM UTC 24
Finished Aug 21 05:10:05 AM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2782229994 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2782229994
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2026459662
Short name T395
Test name
Test status
Simulation time 329481755572 ps
CPU time 785.69 seconds
Started Aug 21 05:07:11 AM UTC 24
Finished Aug 21 05:20:28 AM UTC 24
Peak memory 212504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2026459662 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
interrupt_fixed.2026459662
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.1524830844
Short name T137
Test name
Test status
Simulation time 335195457184 ps
CPU time 175.89 seconds
Started Aug 21 05:07:11 AM UTC 24
Finished Aug 21 05:10:13 AM UTC 24
Peak memory 212576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1524830844 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1524830844
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.1191390992
Short name T368
Test name
Test status
Simulation time 331416823701 ps
CPU time 370.57 seconds
Started Aug 21 05:07:11 AM UTC 24
Finished Aug 21 05:13:29 AM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1191390992 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_pol
led_fixed.1191390992
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.3138132177
Short name T249
Test name
Test status
Simulation time 575838501023 ps
CPU time 1295.97 seconds
Started Aug 21 05:07:11 AM UTC 24
Finished Aug 21 05:29:00 AM UTC 24
Peak memory 212500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3138132177 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_
filters_wakeup.3138132177
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.918753838
Short name T11
Test name
Test status
Simulation time 36843831185 ps
CPU time 16.98 seconds
Started Aug 21 05:07:11 AM UTC 24
Finished Aug 21 05:07:37 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=918753838 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.918753838
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.1599722565
Short name T6
Test name
Test status
Simulation time 5286357208 ps
CPU time 6.52 seconds
Started Aug 21 05:07:11 AM UTC 24
Finished Aug 21 05:07:26 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1599722565 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1599722565
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.2905268275
Short name T8
Test name
Test status
Simulation time 5536012343 ps
CPU time 12.42 seconds
Started Aug 21 05:07:11 AM UTC 24
Finished Aug 21 05:07:28 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2905268275 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2905268275
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/0.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.4070031773
Short name T22
Test name
Test status
Simulation time 535521658 ps
CPU time 0.59 seconds
Started Aug 21 05:07:16 AM UTC 24
Finished Aug 21 05:07:25 AM UTC 24
Peak memory 210332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4070031773 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.4070031773
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.4079425855
Short name T179
Test name
Test status
Simulation time 161662868642 ps
CPU time 559.23 seconds
Started Aug 21 05:07:13 AM UTC 24
Finished Aug 21 05:16:40 AM UTC 24
Peak memory 212616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4079425855 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
interrupt_fixed.4079425855
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.631836866
Short name T286
Test name
Test status
Simulation time 171920239792 ps
CPU time 591.76 seconds
Started Aug 21 05:07:13 AM UTC 24
Finished Aug 21 05:17:11 AM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=631836866 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.631836866
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.536885011
Short name T365
Test name
Test status
Simulation time 163409673999 ps
CPU time 348.07 seconds
Started Aug 21 05:07:13 AM UTC 24
Finished Aug 21 05:13:06 AM UTC 24
Peak memory 211444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=536885011 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_poll
ed_fixed.536885011
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3478779752
Short name T457
Test name
Test status
Simulation time 591367392871 ps
CPU time 1456.13 seconds
Started Aug 21 05:07:13 AM UTC 24
Finished Aug 21 05:31:45 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3478779752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 1.adc_ctrl_filters_wakeup_fixed.3478779752
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.4072435667
Short name T47
Test name
Test status
Simulation time 34169006614 ps
CPU time 71 seconds
Started Aug 21 05:07:14 AM UTC 24
Finished Aug 21 05:08:27 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4072435667 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.4072435667
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.828712861
Short name T4
Test name
Test status
Simulation time 4010604538 ps
CPU time 8.8 seconds
Started Aug 21 05:07:13 AM UTC 24
Finished Aug 21 05:07:23 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=828712861 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.828712861
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.2515652373
Short name T42
Test name
Test status
Simulation time 8486609287 ps
CPU time 10.62 seconds
Started Aug 21 05:07:16 AM UTC 24
Finished Aug 21 05:07:35 AM UTC 24
Peak memory 243472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2515652373 -ass
ert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2515652373
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.4048400029
Short name T9
Test name
Test status
Simulation time 5933819843 ps
CPU time 7.5 seconds
Started Aug 21 05:07:13 AM UTC 24
Finished Aug 21 05:07:31 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4048400029 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.4048400029
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.3041478976
Short name T26
Test name
Test status
Simulation time 63189807912 ps
CPU time 23.72 seconds
Started Aug 21 05:07:15 AM UTC 24
Finished Aug 21 05:07:43 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3041478976
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_str
ess_all.3041478976
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.1758504452
Short name T374
Test name
Test status
Simulation time 375628796 ps
CPU time 2.26 seconds
Started Aug 21 05:15:41 AM UTC 24
Finished Aug 21 05:15:44 AM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1758504452 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1758504452
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.563309086
Short name T186
Test name
Test status
Simulation time 338252620378 ps
CPU time 207.73 seconds
Started Aug 21 05:15:12 AM UTC 24
Finished Aug 21 05:18:43 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=563309086 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.563309086
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2191839368
Short name T394
Test name
Test status
Simulation time 482451372797 ps
CPU time 305.49 seconds
Started Aug 21 05:15:12 AM UTC 24
Finished Aug 21 05:20:21 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2191839368 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_interrupt_fixed.2191839368
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.2966351477
Short name T255
Test name
Test status
Simulation time 332578557673 ps
CPU time 182.2 seconds
Started Aug 21 05:15:01 AM UTC 24
Finished Aug 21 05:18:06 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2966351477 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2966351477
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.2525650370
Short name T409
Test name
Test status
Simulation time 164846676486 ps
CPU time 473.06 seconds
Started Aug 21 05:15:12 AM UTC 24
Finished Aug 21 05:23:11 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2525650370 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_po
lled_fixed.2525650370
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.2376155648
Short name T188
Test name
Test status
Simulation time 455882397859 ps
CPU time 459.3 seconds
Started Aug 21 05:15:13 AM UTC 24
Finished Aug 21 05:22:58 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2376155648 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl
_filters_wakeup.2376155648
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3399469206
Short name T435
Test name
Test status
Simulation time 608469507771 ps
CPU time 777.26 seconds
Started Aug 21 05:15:15 AM UTC 24
Finished Aug 21 05:28:21 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3399469206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 10.adc_ctrl_filters_wakeup_fixed.3399469206
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.3929565746
Short name T433
Test name
Test status
Simulation time 101183450513 ps
CPU time 715.7 seconds
Started Aug 21 05:15:33 AM UTC 24
Finished Aug 21 05:27:36 AM UTC 24
Peak memory 211712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3929565746 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3929565746
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.816872834
Short name T375
Test name
Test status
Simulation time 21500969825 ps
CPU time 19.8 seconds
Started Aug 21 05:15:27 AM UTC 24
Finished Aug 21 05:15:48 AM UTC 24
Peak memory 211300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=816872834 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.816872834
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.3513321353
Short name T372
Test name
Test status
Simulation time 4783399425 ps
CPU time 5.8 seconds
Started Aug 21 05:15:25 AM UTC 24
Finished Aug 21 05:15:32 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3513321353 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3513321353
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.1959560226
Short name T202
Test name
Test status
Simulation time 5925545246 ps
CPU time 12.58 seconds
Started Aug 21 05:15:01 AM UTC 24
Finished Aug 21 05:15:15 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1959560226 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1959560226
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.4207237533
Short name T32
Test name
Test status
Simulation time 8451841840 ps
CPU time 4.68 seconds
Started Aug 21 05:15:35 AM UTC 24
Finished Aug 21 05:15:40 AM UTC 24
Peak memory 211696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4207237533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.4207237533
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.1042914791
Short name T182
Test name
Test status
Simulation time 526903413 ps
CPU time 1.92 seconds
Started Aug 21 05:16:48 AM UTC 24
Finished Aug 21 05:16:51 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1042914791 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1042914791
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1599571683
Short name T241
Test name
Test status
Simulation time 340611011619 ps
CPU time 557.05 seconds
Started Aug 21 05:16:17 AM UTC 24
Finished Aug 21 05:25:41 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1599571683 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_c
lock_gating.1599571683
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2193734606
Short name T412
Test name
Test status
Simulation time 165565004790 ps
CPU time 467.87 seconds
Started Aug 21 05:15:53 AM UTC 24
Finished Aug 21 05:23:46 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2193734606 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_interrupt_fixed.2193734606
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.1294605201
Short name T392
Test name
Test status
Simulation time 159645950071 ps
CPU time 242.55 seconds
Started Aug 21 05:15:49 AM UTC 24
Finished Aug 21 05:19:55 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1294605201 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_po
lled_fixed.1294605201
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.4133700419
Short name T512
Test name
Test status
Simulation time 610734208820 ps
CPU time 1434.46 seconds
Started Aug 21 05:16:09 AM UTC 24
Finished Aug 21 05:40:18 AM UTC 24
Peak memory 212616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4133700419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 11.adc_ctrl_filters_wakeup_fixed.4133700419
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.1766314597
Short name T204
Test name
Test status
Simulation time 121955336011 ps
CPU time 717.48 seconds
Started Aug 21 05:16:33 AM UTC 24
Finished Aug 21 05:28:37 AM UTC 24
Peak memory 211976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1766314597 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1766314597
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.1246570535
Short name T380
Test name
Test status
Simulation time 22701260206 ps
CPU time 36.98 seconds
Started Aug 21 05:16:31 AM UTC 24
Finished Aug 21 05:17:10 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1246570535 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1246570535
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.1346024290
Short name T183
Test name
Test status
Simulation time 4845837544 ps
CPU time 21.78 seconds
Started Aug 21 05:16:29 AM UTC 24
Finished Aug 21 05:16:52 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1346024290 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1346024290
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.430958714
Short name T376
Test name
Test status
Simulation time 6098144670 ps
CPU time 5.37 seconds
Started Aug 21 05:15:45 AM UTC 24
Finished Aug 21 05:15:51 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=430958714 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.430958714
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2612458963
Short name T181
Test name
Test status
Simulation time 2729835918 ps
CPU time 12.37 seconds
Started Aug 21 05:16:36 AM UTC 24
Finished Aug 21 05:16:49 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2612458963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2612458963
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.1088912024
Short name T384
Test name
Test status
Simulation time 369016627 ps
CPU time 1.06 seconds
Started Aug 21 05:17:43 AM UTC 24
Finished Aug 21 05:17:45 AM UTC 24
Peak memory 210348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1088912024 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1088912024
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.2458575125
Short name T223
Test name
Test status
Simulation time 513531374335 ps
CPU time 334.57 seconds
Started Aug 21 05:17:12 AM UTC 24
Finished Aug 21 05:22:51 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2458575125 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2458575125
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.870020411
Short name T397
Test name
Test status
Simulation time 326182948497 ps
CPU time 219.72 seconds
Started Aug 21 05:16:57 AM UTC 24
Finished Aug 21 05:20:40 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=870020411 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
interrupt_fixed.870020411
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.3075640348
Short name T518
Test name
Test status
Simulation time 497049890246 ps
CPU time 1421.97 seconds
Started Aug 21 05:16:52 AM UTC 24
Finished Aug 21 05:40:48 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3075640348 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3075640348
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.1623585228
Short name T390
Test name
Test status
Simulation time 165735172908 ps
CPU time 166.88 seconds
Started Aug 21 05:16:53 AM UTC 24
Finished Aug 21 05:19:43 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1623585228 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_po
lled_fixed.1623585228
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.589511515
Short name T415
Test name
Test status
Simulation time 189344108767 ps
CPU time 408.72 seconds
Started Aug 21 05:17:10 AM UTC 24
Finished Aug 21 05:24:04 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=589511515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 12.adc_ctrl_filters_wakeup_fixed.589511515
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.695235982
Short name T393
Test name
Test status
Simulation time 43778238978 ps
CPU time 150.87 seconds
Started Aug 21 05:17:23 AM UTC 24
Finished Aug 21 05:19:56 AM UTC 24
Peak memory 211300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=695235982 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.695235982
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.2155577789
Short name T383
Test name
Test status
Simulation time 2955171854 ps
CPU time 12.8 seconds
Started Aug 21 05:17:18 AM UTC 24
Finished Aug 21 05:17:32 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2155577789 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2155577789
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.721924101
Short name T381
Test name
Test status
Simulation time 5705578232 ps
CPU time 26.02 seconds
Started Aug 21 05:16:50 AM UTC 24
Finished Aug 21 05:17:17 AM UTC 24
Peak memory 211200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=721924101 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.721924101
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.3490250407
Short name T217
Test name
Test status
Simulation time 27161841738 ps
CPU time 49.69 seconds
Started Aug 21 05:17:41 AM UTC 24
Finished Aug 21 05:18:32 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3490250407
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_st
ress_all.3490250407
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2946958853
Short name T33
Test name
Test status
Simulation time 37482654107 ps
CPU time 17.75 seconds
Started Aug 21 05:17:33 AM UTC 24
Finished Aug 21 05:17:52 AM UTC 24
Peak memory 227904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2946958853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2946958853
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.4230355634
Short name T389
Test name
Test status
Simulation time 534124000 ps
CPU time 1.31 seconds
Started Aug 21 05:19:29 AM UTC 24
Finished Aug 21 05:19:32 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4230355634 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.4230355634
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.4258651238
Short name T240
Test name
Test status
Simulation time 343310280405 ps
CPU time 56.3 seconds
Started Aug 21 05:18:30 AM UTC 24
Finished Aug 21 05:19:28 AM UTC 24
Peak memory 211612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4258651238 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_c
lock_gating.4258651238
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.1535002546
Short name T242
Test name
Test status
Simulation time 222786909739 ps
CPU time 158.71 seconds
Started Aug 21 05:18:32 AM UTC 24
Finished Aug 21 05:21:14 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1535002546 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1535002546
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1513109729
Short name T405
Test name
Test status
Simulation time 331519689666 ps
CPU time 273.36 seconds
Started Aug 21 05:18:08 AM UTC 24
Finished Aug 21 05:22:45 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1513109729 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_interrupt_fixed.1513109729
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.2864805259
Short name T445
Test name
Test status
Simulation time 492803443136 ps
CPU time 734.63 seconds
Started Aug 21 05:17:52 AM UTC 24
Finished Aug 21 05:30:15 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2864805259 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2864805259
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.2679132619
Short name T418
Test name
Test status
Simulation time 163809032914 ps
CPU time 385.15 seconds
Started Aug 21 05:17:58 AM UTC 24
Finished Aug 21 05:24:27 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2679132619 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_po
lled_fixed.2679132619
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.1971434403
Short name T171
Test name
Test status
Simulation time 549005446687 ps
CPU time 348.14 seconds
Started Aug 21 05:18:09 AM UTC 24
Finished Aug 21 05:24:01 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1971434403 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl
_filters_wakeup.1971434403
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1577645844
Short name T442
Test name
Test status
Simulation time 196981868958 ps
CPU time 692.18 seconds
Started Aug 21 05:18:11 AM UTC 24
Finished Aug 21 05:29:51 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1577645844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 13.adc_ctrl_filters_wakeup_fixed.1577645844
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.118475343
Short name T388
Test name
Test status
Simulation time 30218551070 ps
CPU time 32.7 seconds
Started Aug 21 05:18:37 AM UTC 24
Finished Aug 21 05:19:12 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=118475343 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.118475343
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.1500098673
Short name T386
Test name
Test status
Simulation time 4420613626 ps
CPU time 2.19 seconds
Started Aug 21 05:18:33 AM UTC 24
Finished Aug 21 05:18:37 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1500098673 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1500098673
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.1118772166
Short name T385
Test name
Test status
Simulation time 5812623686 ps
CPU time 20.29 seconds
Started Aug 21 05:17:46 AM UTC 24
Finished Aug 21 05:18:07 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1118772166 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1118772166
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.2717774280
Short name T253
Test name
Test status
Simulation time 514344095569 ps
CPU time 1515.81 seconds
Started Aug 21 05:19:12 AM UTC 24
Finished Aug 21 05:44:44 AM UTC 24
Peak memory 212624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2717774280
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_st
ress_all.2717774280
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.782691527
Short name T34
Test name
Test status
Simulation time 13834065739 ps
CPU time 37.86 seconds
Started Aug 21 05:19:09 AM UTC 24
Finished Aug 21 05:19:48 AM UTC 24
Peak memory 221964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=782691527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.782691527
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.2022364029
Short name T398
Test name
Test status
Simulation time 513401119 ps
CPU time 1.88 seconds
Started Aug 21 05:20:45 AM UTC 24
Finished Aug 21 05:20:48 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2022364029 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2022364029
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.611257763
Short name T231
Test name
Test status
Simulation time 168630594086 ps
CPU time 81.07 seconds
Started Aug 21 05:20:19 AM UTC 24
Finished Aug 21 05:21:42 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=611257763 -a
ssert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_cl
ock_gating.611257763
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.1953556139
Short name T232
Test name
Test status
Simulation time 164928050564 ps
CPU time 219.15 seconds
Started Aug 21 05:19:46 AM UTC 24
Finished Aug 21 05:23:29 AM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1953556139 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1953556139
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2930673096
Short name T430
Test name
Test status
Simulation time 325927923326 ps
CPU time 441.2 seconds
Started Aug 21 05:19:49 AM UTC 24
Finished Aug 21 05:27:16 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2930673096 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_interrupt_fixed.2930673096
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.807999841
Short name T336
Test name
Test status
Simulation time 327076398313 ps
CPU time 293.45 seconds
Started Aug 21 05:19:43 AM UTC 24
Finished Aug 21 05:24:41 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=807999841 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.807999841
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.1012292624
Short name T426
Test name
Test status
Simulation time 483562956037 ps
CPU time 409.17 seconds
Started Aug 21 05:19:43 AM UTC 24
Finished Aug 21 05:26:37 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1012292624 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_po
lled_fixed.1012292624
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.2313392103
Short name T257
Test name
Test status
Simulation time 183136760600 ps
CPU time 47.64 seconds
Started Aug 21 05:19:55 AM UTC 24
Finished Aug 21 05:20:44 AM UTC 24
Peak memory 211628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2313392103 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl
_filters_wakeup.2313392103
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.4156377915
Short name T423
Test name
Test status
Simulation time 603734705266 ps
CPU time 358.05 seconds
Started Aug 21 05:19:56 AM UTC 24
Finished Aug 21 05:25:59 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4156377915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 14.adc_ctrl_filters_wakeup_fixed.4156377915
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.4217856336
Short name T400
Test name
Test status
Simulation time 36217161657 ps
CPU time 25.89 seconds
Started Aug 21 05:20:34 AM UTC 24
Finished Aug 21 05:21:01 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4217856336 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.4217856336
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.4137627282
Short name T396
Test name
Test status
Simulation time 5625919079 ps
CPU time 3.09 seconds
Started Aug 21 05:20:29 AM UTC 24
Finished Aug 21 05:20:33 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4137627282 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.4137627282
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.475174358
Short name T391
Test name
Test status
Simulation time 5621708756 ps
CPU time 11.44 seconds
Started Aug 21 05:19:33 AM UTC 24
Finished Aug 21 05:19:46 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=475174358 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.475174358
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.800406543
Short name T35
Test name
Test status
Simulation time 5042006830 ps
CPU time 30.76 seconds
Started Aug 21 05:20:40 AM UTC 24
Finished Aug 21 05:21:12 AM UTC 24
Peak memory 222272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=800406543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.800406543
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.2880266111
Short name T407
Test name
Test status
Simulation time 461980832 ps
CPU time 1.31 seconds
Started Aug 21 05:22:52 AM UTC 24
Finished Aug 21 05:22:55 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2880266111 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2880266111
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.2581430826
Short name T327
Test name
Test status
Simulation time 498827049253 ps
CPU time 1059.08 seconds
Started Aug 21 05:21:12 AM UTC 24
Finished Aug 21 05:39:03 AM UTC 24
Peak memory 212648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2581430826 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2581430826
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2290105473
Short name T439
Test name
Test status
Simulation time 318149500091 ps
CPU time 493.72 seconds
Started Aug 21 05:21:14 AM UTC 24
Finished Aug 21 05:29:34 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2290105473 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_interrupt_fixed.2290105473
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.4272038050
Short name T155
Test name
Test status
Simulation time 495996232512 ps
CPU time 111.64 seconds
Started Aug 21 05:20:58 AM UTC 24
Finished Aug 21 05:22:52 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4272038050 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.4272038050
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.1185388211
Short name T451
Test name
Test status
Simulation time 325237215919 ps
CPU time 585.65 seconds
Started Aug 21 05:21:01 AM UTC 24
Finished Aug 21 05:30:53 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1185388211 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_po
lled_fixed.1185388211
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.1846390636
Short name T293
Test name
Test status
Simulation time 181024361044 ps
CPU time 117.4 seconds
Started Aug 21 05:21:44 AM UTC 24
Finished Aug 21 05:23:43 AM UTC 24
Peak memory 211436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1846390636 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl
_filters_wakeup.1846390636
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2980096255
Short name T425
Test name
Test status
Simulation time 393068558631 ps
CPU time 269.35 seconds
Started Aug 21 05:21:56 AM UTC 24
Finished Aug 21 05:26:29 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2980096255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 15.adc_ctrl_filters_wakeup_fixed.2980096255
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.3250560692
Short name T357
Test name
Test status
Simulation time 72022853693 ps
CPU time 263.92 seconds
Started Aug 21 05:22:47 AM UTC 24
Finished Aug 21 05:27:15 AM UTC 24
Peak memory 211784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3250560692 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3250560692
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.38318732
Short name T410
Test name
Test status
Simulation time 44611514908 ps
CPU time 46.97 seconds
Started Aug 21 05:22:46 AM UTC 24
Finished Aug 21 05:23:34 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38318732 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.38318732
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.1511648791
Short name T406
Test name
Test status
Simulation time 3900346243 ps
CPU time 17.52 seconds
Started Aug 21 05:22:30 AM UTC 24
Finished Aug 21 05:22:49 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1511648791 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1511648791
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.2782228571
Short name T399
Test name
Test status
Simulation time 6041067654 ps
CPU time 7.82 seconds
Started Aug 21 05:20:49 AM UTC 24
Finished Aug 21 05:20:58 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2782228571 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2782228571
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.2580670693
Short name T228
Test name
Test status
Simulation time 169426630127 ps
CPU time 558.14 seconds
Started Aug 21 05:22:52 AM UTC 24
Finished Aug 21 05:32:17 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2580670693
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_st
ress_all.2580670693
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.51695605
Short name T36
Test name
Test status
Simulation time 2744683285 ps
CPU time 6.92 seconds
Started Aug 21 05:22:49 AM UTC 24
Finished Aug 21 05:22:57 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=51695605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.51695605
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.160024138
Short name T414
Test name
Test status
Simulation time 467834489 ps
CPU time 0.99 seconds
Started Aug 21 05:23:51 AM UTC 24
Finished Aug 21 05:23:53 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=160024138 -ass
ert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.160024138
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.2740305696
Short name T252
Test name
Test status
Simulation time 567275586490 ps
CPU time 1215.57 seconds
Started Aug 21 05:23:30 AM UTC 24
Finished Aug 21 05:43:58 AM UTC 24
Peak memory 212528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2740305696 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2740305696
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.1250288490
Short name T277
Test name
Test status
Simulation time 163689763895 ps
CPU time 184.12 seconds
Started Aug 21 05:22:58 AM UTC 24
Finished Aug 21 05:26:05 AM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1250288490 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1250288490
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2377530665
Short name T447
Test name
Test status
Simulation time 161369226861 ps
CPU time 438.17 seconds
Started Aug 21 05:23:06 AM UTC 24
Finished Aug 21 05:30:29 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2377530665 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_interrupt_fixed.2377530665
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.2012437442
Short name T164
Test name
Test status
Simulation time 163218998746 ps
CPU time 407.98 seconds
Started Aug 21 05:22:58 AM UTC 24
Finished Aug 21 05:29:51 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2012437442 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2012437442
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.1183059370
Short name T419
Test name
Test status
Simulation time 162449700867 ps
CPU time 91.25 seconds
Started Aug 21 05:22:58 AM UTC 24
Finished Aug 21 05:24:31 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1183059370 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_po
lled_fixed.1183059370
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.1207614984
Short name T169
Test name
Test status
Simulation time 295287483999 ps
CPU time 306.99 seconds
Started Aug 21 05:23:11 AM UTC 24
Finished Aug 21 05:28:21 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1207614984 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl
_filters_wakeup.1207614984
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3112685621
Short name T460
Test name
Test status
Simulation time 409435275071 ps
CPU time 542.92 seconds
Started Aug 21 05:23:12 AM UTC 24
Finished Aug 21 05:32:21 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3112685621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 16.adc_ctrl_filters_wakeup_fixed.3112685621
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_fsm_reset.2557322507
Short name T484
Test name
Test status
Simulation time 100316352920 ps
CPU time 749.48 seconds
Started Aug 21 05:23:44 AM UTC 24
Finished Aug 21 05:36:21 AM UTC 24
Peak memory 212856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2557322507 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2557322507
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.2407015341
Short name T417
Test name
Test status
Simulation time 40712023544 ps
CPU time 45.44 seconds
Started Aug 21 05:23:36 AM UTC 24
Finished Aug 21 05:24:23 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2407015341 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2407015341
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.707221348
Short name T413
Test name
Test status
Simulation time 4721240897 ps
CPU time 14.72 seconds
Started Aug 21 05:23:35 AM UTC 24
Finished Aug 21 05:23:51 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=707221348 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.707221348
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.3775211025
Short name T408
Test name
Test status
Simulation time 5916195018 ps
CPU time 7.79 seconds
Started Aug 21 05:22:55 AM UTC 24
Finished Aug 21 05:23:04 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3775211025 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3775211025
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.205547540
Short name T458
Test name
Test status
Simulation time 157247418721 ps
CPU time 480.53 seconds
Started Aug 21 05:23:47 AM UTC 24
Finished Aug 21 05:31:52 AM UTC 24
Peak memory 221856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=205547540 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_str
ess_all.205547540
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.2710014345
Short name T421
Test name
Test status
Simulation time 437371353 ps
CPU time 1.74 seconds
Started Aug 21 05:25:28 AM UTC 24
Finished Aug 21 05:25:31 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2710014345 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2710014345
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.3180937674
Short name T261
Test name
Test status
Simulation time 166016572442 ps
CPU time 402.65 seconds
Started Aug 21 05:24:28 AM UTC 24
Finished Aug 21 05:31:16 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3180937674 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_c
lock_gating.3180937674
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.1254610491
Short name T220
Test name
Test status
Simulation time 163038703921 ps
CPU time 90.16 seconds
Started Aug 21 05:24:32 AM UTC 24
Finished Aug 21 05:26:04 AM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1254610491 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1254610491
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.839450651
Short name T167
Test name
Test status
Simulation time 333121239567 ps
CPU time 1125.22 seconds
Started Aug 21 05:24:14 AM UTC 24
Finished Aug 21 05:43:10 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=839450651 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.839450651
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2398675803
Short name T566
Test name
Test status
Simulation time 490229257570 ps
CPU time 1451.19 seconds
Started Aug 21 05:24:20 AM UTC 24
Finished Aug 21 05:48:46 AM UTC 24
Peak memory 212544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2398675803 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_interrupt_fixed.2398675803
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.2416955086
Short name T491
Test name
Test status
Simulation time 333648328936 ps
CPU time 804.2 seconds
Started Aug 21 05:24:05 AM UTC 24
Finished Aug 21 05:37:38 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2416955086 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_po
lled_fixed.2416955086
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2968050977
Short name T450
Test name
Test status
Simulation time 404640274626 ps
CPU time 383.5 seconds
Started Aug 21 05:24:24 AM UTC 24
Finished Aug 21 05:30:53 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2968050977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 17.adc_ctrl_filters_wakeup_fixed.2968050977
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_fsm_reset.1007385900
Short name T215
Test name
Test status
Simulation time 64153400190 ps
CPU time 265.05 seconds
Started Aug 21 05:25:01 AM UTC 24
Finished Aug 21 05:29:29 AM UTC 24
Peak memory 211784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1007385900 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1007385900
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.3098958990
Short name T422
Test name
Test status
Simulation time 38823496977 ps
CPU time 57.97 seconds
Started Aug 21 05:24:41 AM UTC 24
Finished Aug 21 05:25:41 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3098958990 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3098958990
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.2388213653
Short name T420
Test name
Test status
Simulation time 4680449453 ps
CPU time 20.06 seconds
Started Aug 21 05:24:39 AM UTC 24
Finished Aug 21 05:25:00 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2388213653 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2388213653
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.1107576558
Short name T416
Test name
Test status
Simulation time 6089985273 ps
CPU time 23.3 seconds
Started Aug 21 05:23:54 AM UTC 24
Finished Aug 21 05:24:19 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1107576558 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1107576558
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2725222688
Short name T37
Test name
Test status
Simulation time 27755258118 ps
CPU time 27.52 seconds
Started Aug 21 05:25:16 AM UTC 24
Finished Aug 21 05:25:45 AM UTC 24
Peak memory 221876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2725222688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2725222688
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.1379310443
Short name T429
Test name
Test status
Simulation time 377255579 ps
CPU time 2.42 seconds
Started Aug 21 05:27:09 AM UTC 24
Finished Aug 21 05:27:13 AM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1379310443 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1379310443
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.2651677327
Short name T288
Test name
Test status
Simulation time 165823376812 ps
CPU time 142.35 seconds
Started Aug 21 05:25:46 AM UTC 24
Finished Aug 21 05:28:10 AM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2651677327 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2651677327
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2218312708
Short name T526
Test name
Test status
Simulation time 321914386375 ps
CPU time 995.42 seconds
Started Aug 21 05:26:00 AM UTC 24
Finished Aug 21 05:42:46 AM UTC 24
Peak memory 212624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2218312708 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_interrupt_fixed.2218312708
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.2264949231
Short name T474
Test name
Test status
Simulation time 165714701769 ps
CPU time 486.16 seconds
Started Aug 21 05:25:41 AM UTC 24
Finished Aug 21 05:33:53 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2264949231 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2264949231
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.2507894889
Short name T446
Test name
Test status
Simulation time 329342023224 ps
CPU time 279.98 seconds
Started Aug 21 05:25:41 AM UTC 24
Finished Aug 21 05:30:25 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2507894889 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_po
lled_fixed.2507894889
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.3042555488
Short name T268
Test name
Test status
Simulation time 190214694496 ps
CPU time 607.08 seconds
Started Aug 21 05:26:02 AM UTC 24
Finished Aug 21 05:36:16 AM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3042555488 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl
_filters_wakeup.3042555488
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup_fixed.58792977
Short name T434
Test name
Test status
Simulation time 403951939628 ps
CPU time 111.37 seconds
Started Aug 21 05:26:06 AM UTC 24
Finished Aug 21 05:28:00 AM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=58792977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 18.adc_ctrl_filters_wakeup_fixed.58792977
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_fsm_reset.3713334412
Short name T476
Test name
Test status
Simulation time 74449397897 ps
CPU time 421.78 seconds
Started Aug 21 05:26:50 AM UTC 24
Finished Aug 21 05:33:56 AM UTC 24
Peak memory 211704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3713334412 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3713334412
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.2181913975
Short name T428
Test name
Test status
Simulation time 26749962102 ps
CPU time 20.79 seconds
Started Aug 21 05:26:44 AM UTC 24
Finished Aug 21 05:27:06 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2181913975 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2181913975
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.1662992269
Short name T427
Test name
Test status
Simulation time 4676074641 ps
CPU time 10.73 seconds
Started Aug 21 05:26:38 AM UTC 24
Finished Aug 21 05:26:50 AM UTC 24
Peak memory 211224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1662992269 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1662992269
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.4241744617
Short name T424
Test name
Test status
Simulation time 6093260208 ps
CPU time 26.92 seconds
Started Aug 21 05:25:32 AM UTC 24
Finished Aug 21 05:26:01 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4241744617 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.4241744617
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.3185352982
Short name T490
Test name
Test status
Simulation time 413186393206 ps
CPU time 619.33 seconds
Started Aug 21 05:27:06 AM UTC 24
Finished Aug 21 05:37:32 AM UTC 24
Peak memory 211704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3185352982
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_st
ress_all.3185352982
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2745371627
Short name T38
Test name
Test status
Simulation time 3840110675 ps
CPU time 17.55 seconds
Started Aug 21 05:26:50 AM UTC 24
Finished Aug 21 05:27:09 AM UTC 24
Peak memory 221764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2745371627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2745371627
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.1042164723
Short name T437
Test name
Test status
Simulation time 338749685 ps
CPU time 1.22 seconds
Started Aug 21 05:28:42 AM UTC 24
Finished Aug 21 05:28:45 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1042164723 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1042164723
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.1082215782
Short name T300
Test name
Test status
Simulation time 355774443305 ps
CPU time 264.66 seconds
Started Aug 21 05:28:11 AM UTC 24
Finished Aug 21 05:32:39 AM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1082215782 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_c
lock_gating.1082215782
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.2435161555
Short name T318
Test name
Test status
Simulation time 181770021817 ps
CPU time 257.19 seconds
Started Aug 21 05:28:22 AM UTC 24
Finished Aug 21 05:32:43 AM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2435161555 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2435161555
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt.1360335138
Short name T190
Test name
Test status
Simulation time 320526053919 ps
CPU time 231.41 seconds
Started Aug 21 05:27:29 AM UTC 24
Finished Aug 21 05:31:24 AM UTC 24
Peak memory 211572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1360335138 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1360335138
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3637487220
Short name T478
Test name
Test status
Simulation time 491759149605 ps
CPU time 415.88 seconds
Started Aug 21 05:27:37 AM UTC 24
Finished Aug 21 05:34:38 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3637487220 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_interrupt_fixed.3637487220
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.3421932433
Short name T298
Test name
Test status
Simulation time 158365128372 ps
CPU time 365.58 seconds
Started Aug 21 05:27:15 AM UTC 24
Finished Aug 21 05:33:25 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3421932433 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3421932433
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled_fixed.526275486
Short name T572
Test name
Test status
Simulation time 496168018828 ps
CPU time 1321.26 seconds
Started Aug 21 05:27:16 AM UTC 24
Finished Aug 21 05:49:31 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=526275486 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_pol
led_fixed.526275486
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.2788937442
Short name T274
Test name
Test status
Simulation time 379228635507 ps
CPU time 370.67 seconds
Started Aug 21 05:27:45 AM UTC 24
Finished Aug 21 05:34:00 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2788937442 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl
_filters_wakeup.2788937442
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup_fixed.4148996872
Short name T455
Test name
Test status
Simulation time 406449738652 ps
CPU time 196.9 seconds
Started Aug 21 05:28:01 AM UTC 24
Finished Aug 21 05:31:21 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4148996872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 19.adc_ctrl_filters_wakeup_fixed.4148996872
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.440482076
Short name T355
Test name
Test status
Simulation time 113365317994 ps
CPU time 643.17 seconds
Started Aug 21 05:28:36 AM UTC 24
Finished Aug 21 05:39:26 AM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=440482076 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.440482076
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.267408346
Short name T440
Test name
Test status
Simulation time 35860719005 ps
CPU time 71.89 seconds
Started Aug 21 05:28:31 AM UTC 24
Finished Aug 21 05:29:45 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=267408346 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.267408346
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.1749178535
Short name T436
Test name
Test status
Simulation time 3267324970 ps
CPU time 6.94 seconds
Started Aug 21 05:28:22 AM UTC 24
Finished Aug 21 05:28:30 AM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1749178535 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1749178535
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.2606892004
Short name T431
Test name
Test status
Simulation time 5855627534 ps
CPU time 13.56 seconds
Started Aug 21 05:27:13 AM UTC 24
Finished Aug 21 05:27:28 AM UTC 24
Peak memory 211296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2606892004 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2606892004
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.2385271531
Short name T304
Test name
Test status
Simulation time 363866420945 ps
CPU time 907.4 seconds
Started Aug 21 05:28:41 AM UTC 24
Finished Aug 21 05:43:58 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2385271531
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_st
ress_all.2385271531
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2525402928
Short name T438
Test name
Test status
Simulation time 3781042893 ps
CPU time 16.92 seconds
Started Aug 21 05:28:38 AM UTC 24
Finished Aug 21 05:28:56 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2525402928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2525402928
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.2172056450
Short name T23
Test name
Test status
Simulation time 322797316 ps
CPU time 1.93 seconds
Started Aug 21 05:07:23 AM UTC 24
Finished Aug 21 05:07:27 AM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2172056450 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2172056450
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.1564020866
Short name T136
Test name
Test status
Simulation time 247186574845 ps
CPU time 319.68 seconds
Started Aug 21 05:07:20 AM UTC 24
Finished Aug 21 05:12:47 AM UTC 24
Peak memory 211056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1564020866 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_cl
ock_gating.1564020866
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.2741332092
Short name T159
Test name
Test status
Simulation time 162506802809 ps
CPU time 268.31 seconds
Started Aug 21 05:07:20 AM UTC 24
Finished Aug 21 05:11:55 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2741332092 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2741332092
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.3152626781
Short name T150
Test name
Test status
Simulation time 164602044362 ps
CPU time 229.23 seconds
Started Aug 21 05:07:18 AM UTC 24
Finished Aug 21 05:11:11 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3152626781 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3152626781
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.392887438
Short name T411
Test name
Test status
Simulation time 327489375822 ps
CPU time 967.29 seconds
Started Aug 21 05:07:18 AM UTC 24
Finished Aug 21 05:23:44 AM UTC 24
Peak memory 212612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=392887438 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_i
nterrupt_fixed.392887438
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.2372402794
Short name T224
Test name
Test status
Simulation time 163625646192 ps
CPU time 258.98 seconds
Started Aug 21 05:07:18 AM UTC 24
Finished Aug 21 05:11:49 AM UTC 24
Peak memory 211696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2372402794 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2372402794
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.4243035446
Short name T193
Test name
Test status
Simulation time 492392009677 ps
CPU time 281.12 seconds
Started Aug 21 05:07:18 AM UTC 24
Finished Aug 21 05:12:03 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4243035446 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_pol
led_fixed.4243035446
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.4274596509
Short name T17
Test name
Test status
Simulation time 178957987181 ps
CPU time 96.99 seconds
Started Aug 21 05:07:18 AM UTC 24
Finished Aug 21 05:09:05 AM UTC 24
Peak memory 211696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4274596509 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_
filters_wakeup.4274596509
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3705943988
Short name T197
Test name
Test status
Simulation time 192576135572 ps
CPU time 448.73 seconds
Started Aug 21 05:07:19 AM UTC 24
Finished Aug 21 05:15:00 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3705943988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 2.adc_ctrl_filters_wakeup_fixed.3705943988
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.3118498435
Short name T57
Test name
Test status
Simulation time 89217993000 ps
CPU time 308.83 seconds
Started Aug 21 05:07:21 AM UTC 24
Finished Aug 21 05:12:37 AM UTC 24
Peak memory 211712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3118498435 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3118498435
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.2330248769
Short name T90
Test name
Test status
Simulation time 30233692742 ps
CPU time 112.47 seconds
Started Aug 21 05:07:20 AM UTC 24
Finished Aug 21 05:09:18 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2330248769 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2330248769
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.2401105436
Short name T7
Test name
Test status
Simulation time 3384601165 ps
CPU time 2.64 seconds
Started Aug 21 05:07:20 AM UTC 24
Finished Aug 21 05:07:27 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2401105436 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2401105436
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.78743266
Short name T53
Test name
Test status
Simulation time 3959551449 ps
CPU time 12.18 seconds
Started Aug 21 05:07:22 AM UTC 24
Finished Aug 21 05:07:37 AM UTC 24
Peak memory 243560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=78743266 -asser
t nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.78743266
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.4075680222
Short name T3
Test name
Test status
Simulation time 6103622128 ps
CPU time 2.4 seconds
Started Aug 21 05:07:18 AM UTC 24
Finished Aug 21 05:07:22 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4075680222 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.4075680222
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.1850991091
Short name T79
Test name
Test status
Simulation time 156704557437 ps
CPU time 279.46 seconds
Started Aug 21 05:07:21 AM UTC 24
Finished Aug 21 05:12:08 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1850991091
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_str
ess_all.1850991091
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_alert_test.2885320707
Short name T443
Test name
Test status
Simulation time 514569902 ps
CPU time 2.81 seconds
Started Aug 21 05:30:08 AM UTC 24
Finished Aug 21 05:30:12 AM UTC 24
Peak memory 211164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2885320707 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2885320707
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/20.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.3337218663
Short name T339
Test name
Test status
Simulation time 330680143079 ps
CPU time 923.64 seconds
Started Aug 21 05:29:30 AM UTC 24
Finished Aug 21 05:45:03 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3337218663 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_c
lock_gating.3337218663
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/20.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt.855695456
Short name T467
Test name
Test status
Simulation time 331641158788 ps
CPU time 218.35 seconds
Started Aug 21 05:29:01 AM UTC 24
Finished Aug 21 05:32:42 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=855695456 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.855695456
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1545700339
Short name T495
Test name
Test status
Simulation time 329447055707 ps
CPU time 535.57 seconds
Started Aug 21 05:29:08 AM UTC 24
Finished Aug 21 05:38:10 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1545700339 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_interrupt_fixed.1545700339
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled.4269033604
Short name T287
Test name
Test status
Simulation time 165838627014 ps
CPU time 87.09 seconds
Started Aug 21 05:28:57 AM UTC 24
Finished Aug 21 05:30:27 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4269033604 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.4269033604
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled_fixed.152605539
Short name T568
Test name
Test status
Simulation time 494880327054 ps
CPU time 1185.1 seconds
Started Aug 21 05:29:01 AM UTC 24
Finished Aug 21 05:48:57 AM UTC 24
Peak memory 212604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=152605539 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_pol
led_fixed.152605539
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.3268174213
Short name T320
Test name
Test status
Simulation time 169051761189 ps
CPU time 331.85 seconds
Started Aug 21 05:29:12 AM UTC 24
Finished Aug 21 05:34:48 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3268174213 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl
_filters_wakeup.3268174213
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3056098216
Short name T452
Test name
Test status
Simulation time 394065890034 ps
CPU time 94.23 seconds
Started Aug 21 05:29:20 AM UTC 24
Finished Aug 21 05:30:56 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3056098216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 20.adc_ctrl_filters_wakeup_fixed.3056098216
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_fsm_reset.125918651
Short name T493
Test name
Test status
Simulation time 99411664325 ps
CPU time 465.23 seconds
Started Aug 21 05:29:52 AM UTC 24
Finished Aug 21 05:37:42 AM UTC 24
Peak memory 211704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=125918651 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.125918651
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/20.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_lowpower_counter.3743549902
Short name T444
Test name
Test status
Simulation time 36901061700 ps
CPU time 22.13 seconds
Started Aug 21 05:29:50 AM UTC 24
Finished Aug 21 05:30:13 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3743549902 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3743549902
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/20.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_poweron_counter.2952848639
Short name T441
Test name
Test status
Simulation time 2708326757 ps
CPU time 3.66 seconds
Started Aug 21 05:29:45 AM UTC 24
Finished Aug 21 05:29:50 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2952848639 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2952848639
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/20.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.3078829920
Short name T432
Test name
Test status
Simulation time 5675916641 ps
CPU time 24.43 seconds
Started Aug 21 05:28:45 AM UTC 24
Finished Aug 21 05:29:11 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3078829920 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3078829920
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/20.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.770247988
Short name T39
Test name
Test status
Simulation time 21559469686 ps
CPU time 28.91 seconds
Started Aug 21 05:29:52 AM UTC 24
Finished Aug 21 05:30:22 AM UTC 24
Peak memory 223992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=770247988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.770247988
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_alert_test.3113032542
Short name T453
Test name
Test status
Simulation time 351010266 ps
CPU time 1.23 seconds
Started Aug 21 05:30:56 AM UTC 24
Finished Aug 21 05:30:59 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3113032542 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3113032542
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/21.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.680971332
Short name T285
Test name
Test status
Simulation time 520629671028 ps
CPU time 433.83 seconds
Started Aug 21 05:30:30 AM UTC 24
Finished Aug 21 05:37:49 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=680971332 -a
ssert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_cl
ock_gating.680971332
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/21.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.3151505596
Short name T649
Test name
Test status
Simulation time 593375620877 ps
CPU time 1818.42 seconds
Started Aug 21 05:30:32 AM UTC 24
Finished Aug 21 06:01:10 AM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3151505596 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3151505596
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/21.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt.392359025
Short name T317
Test name
Test status
Simulation time 167109569636 ps
CPU time 63.19 seconds
Started Aug 21 05:30:16 AM UTC 24
Finished Aug 21 05:31:20 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=392359025 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.392359025
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2636726755
Short name T550
Test name
Test status
Simulation time 484018263622 ps
CPU time 965.84 seconds
Started Aug 21 05:30:23 AM UTC 24
Finished Aug 21 05:46:39 AM UTC 24
Peak memory 212612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2636726755 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_interrupt_fixed.2636726755
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled.242684851
Short name T485
Test name
Test status
Simulation time 329031680381 ps
CPU time 371.22 seconds
Started Aug 21 05:30:13 AM UTC 24
Finished Aug 21 05:36:29 AM UTC 24
Peak memory 211716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=242684851 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.242684851
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled_fixed.3029289616
Short name T469
Test name
Test status
Simulation time 168059127358 ps
CPU time 190.6 seconds
Started Aug 21 05:30:14 AM UTC 24
Finished Aug 21 05:33:28 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3029289616 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_po
lled_fixed.3029289616
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.819360932
Short name T258
Test name
Test status
Simulation time 214628298663 ps
CPU time 320.98 seconds
Started Aug 21 05:30:27 AM UTC 24
Finished Aug 21 05:35:52 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=819360932 -a
ssert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_
filters_wakeup.819360932
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1571611273
Short name T100
Test name
Test status
Simulation time 599116058691 ps
CPU time 1298.49 seconds
Started Aug 21 05:30:28 AM UTC 24
Finished Aug 21 05:52:19 AM UTC 24
Peak memory 212676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1571611273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 21.adc_ctrl_filters_wakeup_fixed.1571611273
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_lowpower_counter.983270593
Short name T466
Test name
Test status
Simulation time 33135290220 ps
CPU time 121.07 seconds
Started Aug 21 05:30:35 AM UTC 24
Finished Aug 21 05:32:39 AM UTC 24
Peak memory 211300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=983270593 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.983270593
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/21.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_poweron_counter.2437278305
Short name T449
Test name
Test status
Simulation time 2904535793 ps
CPU time 1.52 seconds
Started Aug 21 05:30:33 AM UTC 24
Finished Aug 21 05:30:36 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2437278305 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2437278305
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/21.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_smoke.353685359
Short name T448
Test name
Test status
Simulation time 6029036807 ps
CPU time 20.1 seconds
Started Aug 21 05:30:13 AM UTC 24
Finished Aug 21 05:30:35 AM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=353685359 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.353685359
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/21.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.3247292844
Short name T502
Test name
Test status
Simulation time 171162747060 ps
CPU time 475.7 seconds
Started Aug 21 05:30:54 AM UTC 24
Finished Aug 21 05:38:55 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3247292844
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_st
ress_all.3247292844
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2152883498
Short name T456
Test name
Test status
Simulation time 35022332511 ps
CPU time 31.19 seconds
Started Aug 21 05:30:53 AM UTC 24
Finished Aug 21 05:31:26 AM UTC 24
Peak memory 228120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2152883498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2152883498
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_alert_test.3886866270
Short name T462
Test name
Test status
Simulation time 589072065 ps
CPU time 0.87 seconds
Started Aug 21 05:32:21 AM UTC 24
Finished Aug 21 05:32:23 AM UTC 24
Peak memory 210348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3886866270 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3886866270
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/22.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.1592274914
Short name T266
Test name
Test status
Simulation time 203528710464 ps
CPU time 142.52 seconds
Started Aug 21 05:31:45 AM UTC 24
Finished Aug 21 05:34:10 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1592274914 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1592274914
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/22.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt.2707279461
Short name T276
Test name
Test status
Simulation time 323511912290 ps
CPU time 825.06 seconds
Started Aug 21 05:31:21 AM UTC 24
Finished Aug 21 05:45:14 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2707279461 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2707279461
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2406900547
Short name T527
Test name
Test status
Simulation time 331082548579 ps
CPU time 683.54 seconds
Started Aug 21 05:31:22 AM UTC 24
Finished Aug 21 05:42:53 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2406900547 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_interrupt_fixed.2406900547
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled.1042607806
Short name T313
Test name
Test status
Simulation time 171153361773 ps
CPU time 72.65 seconds
Started Aug 21 05:31:15 AM UTC 24
Finished Aug 21 05:32:29 AM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1042607806 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1042607806
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled_fixed.455731837
Short name T463
Test name
Test status
Simulation time 326838149494 ps
CPU time 70.73 seconds
Started Aug 21 05:31:17 AM UTC 24
Finished Aug 21 05:32:29 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=455731837 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_pol
led_fixed.455731837
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup.1040018210
Short name T582
Test name
Test status
Simulation time 443106593521 ps
CPU time 1190.13 seconds
Started Aug 21 05:31:25 AM UTC 24
Finished Aug 21 05:51:27 AM UTC 24
Peak memory 212572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1040018210 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl
_filters_wakeup.1040018210
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup_fixed.4050937359
Short name T483
Test name
Test status
Simulation time 588643664253 ps
CPU time 249.46 seconds
Started Aug 21 05:31:27 AM UTC 24
Finished Aug 21 05:35:40 AM UTC 24
Peak memory 211448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4050937359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 22.adc_ctrl_filters_wakeup_fixed.4050937359
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_fsm_reset.773921618
Short name T216
Test name
Test status
Simulation time 120281942156 ps
CPU time 432.04 seconds
Started Aug 21 05:32:03 AM UTC 24
Finished Aug 21 05:39:20 AM UTC 24
Peak memory 212092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=773921618 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.773921618
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/22.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_lowpower_counter.1463820855
Short name T465
Test name
Test status
Simulation time 42581852535 ps
CPU time 35.15 seconds
Started Aug 21 05:31:53 AM UTC 24
Finished Aug 21 05:32:30 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1463820855 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1463820855
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/22.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_poweron_counter.2038940074
Short name T459
Test name
Test status
Simulation time 3714167618 ps
CPU time 15.42 seconds
Started Aug 21 05:31:46 AM UTC 24
Finished Aug 21 05:32:03 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2038940074 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2038940074
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/22.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_smoke.1225272803
Short name T454
Test name
Test status
Simulation time 5970233586 ps
CPU time 13.06 seconds
Started Aug 21 05:30:59 AM UTC 24
Finished Aug 21 05:31:14 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1225272803 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1225272803
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/22.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.18295824
Short name T461
Test name
Test status
Simulation time 1642431843 ps
CPU time 8.66 seconds
Started Aug 21 05:32:12 AM UTC 24
Finished Aug 21 05:32:22 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18295824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.18295824
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_alert_test.1998511221
Short name T470
Test name
Test status
Simulation time 305540691 ps
CPU time 1.42 seconds
Started Aug 21 05:33:29 AM UTC 24
Finished Aug 21 05:33:31 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1998511221 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1998511221
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/23.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.2610000192
Short name T334
Test name
Test status
Simulation time 164688624011 ps
CPU time 155.08 seconds
Started Aug 21 05:32:40 AM UTC 24
Finished Aug 21 05:35:18 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2610000192 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_c
lock_gating.2610000192
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/23.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.4033681386
Short name T262
Test name
Test status
Simulation time 160766198813 ps
CPU time 276.58 seconds
Started Aug 21 05:32:40 AM UTC 24
Finished Aug 21 05:37:20 AM UTC 24
Peak memory 211696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4033681386 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.4033681386
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/23.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.1949297982
Short name T553
Test name
Test status
Simulation time 332391079856 ps
CPU time 864.17 seconds
Started Aug 21 05:32:30 AM UTC 24
Finished Aug 21 05:47:03 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1949297982 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1949297982
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3804508946
Short name T623
Test name
Test status
Simulation time 487902955210 ps
CPU time 1436.28 seconds
Started Aug 21 05:32:30 AM UTC 24
Finished Aug 21 05:56:42 AM UTC 24
Peak memory 212624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3804508946 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_interrupt_fixed.3804508946
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled.1981531830
Short name T499
Test name
Test status
Simulation time 498629585117 ps
CPU time 373.37 seconds
Started Aug 21 05:32:23 AM UTC 24
Finished Aug 21 05:38:40 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1981531830 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1981531830
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled_fixed.3884333980
Short name T506
Test name
Test status
Simulation time 158035566464 ps
CPU time 422.43 seconds
Started Aug 21 05:32:24 AM UTC 24
Finished Aug 21 05:39:31 AM UTC 24
Peak memory 211448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3884333980 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_po
lled_fixed.3884333980
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup.3959998762
Short name T305
Test name
Test status
Simulation time 346902792826 ps
CPU time 185.42 seconds
Started Aug 21 05:32:30 AM UTC 24
Finished Aug 21 05:35:38 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3959998762 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl
_filters_wakeup.3959998762
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup_fixed.4022655933
Short name T525
Test name
Test status
Simulation time 382730269377 ps
CPU time 560.72 seconds
Started Aug 21 05:32:31 AM UTC 24
Finished Aug 21 05:41:58 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4022655933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 23.adc_ctrl_filters_wakeup_fixed.4022655933
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.628277564
Short name T548
Test name
Test status
Simulation time 143776185461 ps
CPU time 819.09 seconds
Started Aug 21 05:32:47 AM UTC 24
Finished Aug 21 05:46:36 AM UTC 24
Peak memory 211820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=628277564 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.628277564
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/23.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_lowpower_counter.3690753184
Short name T477
Test name
Test status
Simulation time 35527352244 ps
CPU time 100.48 seconds
Started Aug 21 05:32:44 AM UTC 24
Finished Aug 21 05:34:27 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3690753184 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3690753184
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/23.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_poweron_counter.4194989380
Short name T468
Test name
Test status
Simulation time 4548267526 ps
CPU time 2.72 seconds
Started Aug 21 05:32:43 AM UTC 24
Finished Aug 21 05:32:47 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4194989380 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.4194989380
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/23.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_smoke.2896265423
Short name T464
Test name
Test status
Simulation time 5727727910 ps
CPU time 6.81 seconds
Started Aug 21 05:32:22 AM UTC 24
Finished Aug 21 05:32:29 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2896265423 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2896265423
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/23.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.1956561794
Short name T312
Test name
Test status
Simulation time 328691134012 ps
CPU time 620.97 seconds
Started Aug 21 05:33:26 AM UTC 24
Finished Aug 21 05:43:55 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1956561794
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_st
ress_all.1956561794
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1661260659
Short name T471
Test name
Test status
Simulation time 5060750488 ps
CPU time 27.02 seconds
Started Aug 21 05:33:08 AM UTC 24
Finished Aug 21 05:33:37 AM UTC 24
Peak memory 221956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1661260659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1661260659
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_alert_test.4167693707
Short name T482
Test name
Test status
Simulation time 514478601 ps
CPU time 1.31 seconds
Started Aug 21 05:35:33 AM UTC 24
Finished Aug 21 05:35:35 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4167693707 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.4167693707
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/24.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.2479674350
Short name T301
Test name
Test status
Simulation time 539002781290 ps
CPU time 345.9 seconds
Started Aug 21 05:34:11 AM UTC 24
Finished Aug 21 05:40:02 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2479674350 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_c
lock_gating.2479674350
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/24.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.2560513420
Short name T333
Test name
Test status
Simulation time 198238310861 ps
CPU time 586.75 seconds
Started Aug 21 05:34:27 AM UTC 24
Finished Aug 21 05:44:21 AM UTC 24
Peak memory 211564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2560513420 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2560513420
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/24.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt.2739106726
Short name T256
Test name
Test status
Simulation time 494196336205 ps
CPU time 611.04 seconds
Started Aug 21 05:33:49 AM UTC 24
Finished Aug 21 05:44:07 AM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2739106726 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2739106726
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2452829608
Short name T481
Test name
Test status
Simulation time 163038193907 ps
CPU time 96.13 seconds
Started Aug 21 05:33:54 AM UTC 24
Finished Aug 21 05:35:32 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2452829608 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_interrupt_fixed.2452829608
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled_fixed.40194495
Short name T523
Test name
Test status
Simulation time 487779769890 ps
CPU time 466.88 seconds
Started Aug 21 05:33:42 AM UTC 24
Finished Aug 21 05:41:34 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40194495 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_poll
ed_fixed.40194495
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup.1084061822
Short name T513
Test name
Test status
Simulation time 175737645976 ps
CPU time 382.29 seconds
Started Aug 21 05:33:57 AM UTC 24
Finished Aug 21 05:40:24 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1084061822 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl
_filters_wakeup.1084061822
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1354777353
Short name T494
Test name
Test status
Simulation time 410150868195 ps
CPU time 236.91 seconds
Started Aug 21 05:34:01 AM UTC 24
Finished Aug 21 05:38:01 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1354777353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 24.adc_ctrl_filters_wakeup_fixed.1354777353
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.3911994564
Short name T541
Test name
Test status
Simulation time 101955472507 ps
CPU time 566.36 seconds
Started Aug 21 05:34:53 AM UTC 24
Finished Aug 21 05:44:26 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3911994564 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3911994564
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/24.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_lowpower_counter.2824212704
Short name T480
Test name
Test status
Simulation time 26042830508 ps
CPU time 26.23 seconds
Started Aug 21 05:34:48 AM UTC 24
Finished Aug 21 05:35:16 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2824212704 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2824212704
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/24.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_poweron_counter.3144626373
Short name T479
Test name
Test status
Simulation time 4015215859 ps
CPU time 13.09 seconds
Started Aug 21 05:34:38 AM UTC 24
Finished Aug 21 05:34:53 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3144626373 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3144626373
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/24.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_smoke.3504543866
Short name T472
Test name
Test status
Simulation time 5924594276 ps
CPU time 8.42 seconds
Started Aug 21 05:33:32 AM UTC 24
Finished Aug 21 05:33:41 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3504543866 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3504543866
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/24.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.3615719828
Short name T609
Test name
Test status
Simulation time 498447230721 ps
CPU time 1208.76 seconds
Started Aug 21 05:35:19 AM UTC 24
Finished Aug 21 05:55:40 AM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3615719828
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_st
ress_all.3615719828
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1300291267
Short name T289
Test name
Test status
Simulation time 18342439240 ps
CPU time 22.2 seconds
Started Aug 21 05:35:18 AM UTC 24
Finished Aug 21 05:35:41 AM UTC 24
Peak memory 221900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1300291267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1300291267
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_alert_test.1651226742
Short name T489
Test name
Test status
Simulation time 494128459 ps
CPU time 3.03 seconds
Started Aug 21 05:37:12 AM UTC 24
Finished Aug 21 05:37:16 AM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1651226742 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1651226742
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/25.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.659271049
Short name T290
Test name
Test status
Simulation time 348625437566 ps
CPU time 237.09 seconds
Started Aug 21 05:36:22 AM UTC 24
Finished Aug 21 05:40:23 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=659271049 -a
ssert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_cl
ock_gating.659271049
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/25.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.1171146536
Short name T269
Test name
Test status
Simulation time 354992254662 ps
CPU time 277.27 seconds
Started Aug 21 05:36:26 AM UTC 24
Finished Aug 21 05:41:07 AM UTC 24
Peak memory 211696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1171146536 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1171146536
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/25.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt.3055697614
Short name T520
Test name
Test status
Simulation time 164859436324 ps
CPU time 310.26 seconds
Started Aug 21 05:35:42 AM UTC 24
Finished Aug 21 05:40:56 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3055697614 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3055697614
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3813020737
Short name T487
Test name
Test status
Simulation time 164185035714 ps
CPU time 66.41 seconds
Started Aug 21 05:35:49 AM UTC 24
Finished Aug 21 05:36:57 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3813020737 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_interrupt_fixed.3813020737
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled.1347162707
Short name T515
Test name
Test status
Simulation time 339453852720 ps
CPU time 288.45 seconds
Started Aug 21 05:35:39 AM UTC 24
Finished Aug 21 05:40:31 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1347162707 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1347162707
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled_fixed.3818845521
Short name T505
Test name
Test status
Simulation time 336498083420 ps
CPU time 220.93 seconds
Started Aug 21 05:35:41 AM UTC 24
Finished Aug 21 05:39:25 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3818845521 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_po
lled_fixed.3818845521
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1260034343
Short name T537
Test name
Test status
Simulation time 196120734785 ps
CPU time 463.73 seconds
Started Aug 21 05:36:16 AM UTC 24
Finished Aug 21 05:44:05 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1260034343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 25.adc_ctrl_filters_wakeup_fixed.1260034343
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_fsm_reset.2439848003
Short name T207
Test name
Test status
Simulation time 135451520147 ps
CPU time 658.22 seconds
Started Aug 21 05:36:47 AM UTC 24
Finished Aug 21 05:47:52 AM UTC 24
Peak memory 211820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2439848003 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2439848003
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/25.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_lowpower_counter.2897756938
Short name T497
Test name
Test status
Simulation time 39615406104 ps
CPU time 109.57 seconds
Started Aug 21 05:36:39 AM UTC 24
Finished Aug 21 05:38:31 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2897756938 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2897756938
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/25.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_poweron_counter.2220813236
Short name T486
Test name
Test status
Simulation time 4108184752 ps
CPU time 15.31 seconds
Started Aug 21 05:36:29 AM UTC 24
Finished Aug 21 05:36:46 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2220813236 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2220813236
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/25.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_smoke.2153685848
Short name T475
Test name
Test status
Simulation time 5572354839 ps
CPU time 11.72 seconds
Started Aug 21 05:35:36 AM UTC 24
Finished Aug 21 05:35:49 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2153685848 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2153685848
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/25.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all.2776390386
Short name T508
Test name
Test status
Simulation time 259843844050 ps
CPU time 152.84 seconds
Started Aug 21 05:37:05 AM UTC 24
Finished Aug 21 05:39:40 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2776390386
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_st
ress_all.2776390386
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2520128726
Short name T488
Test name
Test status
Simulation time 1799082820 ps
CPU time 4.94 seconds
Started Aug 21 05:36:58 AM UTC 24
Finished Aug 21 05:37:04 AM UTC 24
Peak memory 211360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2520128726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2520128726
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_alert_test.1163853754
Short name T500
Test name
Test status
Simulation time 494608964 ps
CPU time 2.6 seconds
Started Aug 21 05:38:39 AM UTC 24
Finished Aug 21 05:38:43 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1163853754 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1163853754
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/26.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_both.215377680
Short name T516
Test name
Test status
Simulation time 168277680493 ps
CPU time 151.02 seconds
Started Aug 21 05:38:02 AM UTC 24
Finished Aug 21 05:40:36 AM UTC 24
Peak memory 211572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=215377680 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.215377680
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/26.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1865971947
Short name T533
Test name
Test status
Simulation time 163258120222 ps
CPU time 354.96 seconds
Started Aug 21 05:37:43 AM UTC 24
Finished Aug 21 05:43:42 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1865971947 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_interrupt_fixed.1865971947
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled.2845568736
Short name T342
Test name
Test status
Simulation time 488942966122 ps
CPU time 201.85 seconds
Started Aug 21 05:37:21 AM UTC 24
Finished Aug 21 05:40:46 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2845568736 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2845568736
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled_fixed.83177117
Short name T604
Test name
Test status
Simulation time 323611752942 ps
CPU time 1029.42 seconds
Started Aug 21 05:37:33 AM UTC 24
Finished Aug 21 05:54:53 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=83177117 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_poll
ed_fixed.83177117
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup_fixed.612690889
Short name T535
Test name
Test status
Simulation time 587936934209 ps
CPU time 352.68 seconds
Started Aug 21 05:37:49 AM UTC 24
Finished Aug 21 05:43:47 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=612690889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 26.adc_ctrl_filters_wakeup_fixed.612690889
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_fsm_reset.1874140704
Short name T101
Test name
Test status
Simulation time 95366111616 ps
CPU time 830.17 seconds
Started Aug 21 05:38:21 AM UTC 24
Finished Aug 21 05:52:21 AM UTC 24
Peak memory 211852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1874140704 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1874140704
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/26.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_lowpower_counter.2739565927
Short name T501
Test name
Test status
Simulation time 36562727792 ps
CPU time 31.33 seconds
Started Aug 21 05:38:14 AM UTC 24
Finished Aug 21 05:38:47 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2739565927 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2739565927
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/26.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_poweron_counter.1681255080
Short name T496
Test name
Test status
Simulation time 3297202209 ps
CPU time 8.1 seconds
Started Aug 21 05:38:11 AM UTC 24
Finished Aug 21 05:38:20 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1681255080 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1681255080
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/26.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_smoke.902314583
Short name T492
Test name
Test status
Simulation time 5762836468 ps
CPU time 23.86 seconds
Started Aug 21 05:37:17 AM UTC 24
Finished Aug 21 05:37:42 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=902314583 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.902314583
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/26.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4181931026
Short name T498
Test name
Test status
Simulation time 4105553838 ps
CPU time 5.23 seconds
Started Aug 21 05:38:32 AM UTC 24
Finished Aug 21 05:38:38 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4181931026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.4181931026
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_alert_test.3331528706
Short name T509
Test name
Test status
Simulation time 455900774 ps
CPU time 1.81 seconds
Started Aug 21 05:39:41 AM UTC 24
Finished Aug 21 05:39:44 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3331528706 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3331528706
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/27.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.3570333847
Short name T279
Test name
Test status
Simulation time 488952832784 ps
CPU time 1522.21 seconds
Started Aug 21 05:39:08 AM UTC 24
Finished Aug 21 06:04:47 AM UTC 24
Peak memory 212616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3570333847 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_c
lock_gating.3570333847
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/27.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_both.2014367261
Short name T233
Test name
Test status
Simulation time 552907369627 ps
CPU time 1323.06 seconds
Started Aug 21 05:39:20 AM UTC 24
Finished Aug 21 06:01:37 AM UTC 24
Peak memory 212504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2014367261 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2014367261
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/27.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt.788126136
Short name T316
Test name
Test status
Simulation time 333453055363 ps
CPU time 1081.73 seconds
Started Aug 21 05:38:47 AM UTC 24
Finished Aug 21 05:57:00 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=788126136 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.788126136
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3470998931
Short name T524
Test name
Test status
Simulation time 159347020891 ps
CPU time 164.56 seconds
Started Aug 21 05:38:56 AM UTC 24
Finished Aug 21 05:41:43 AM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3470998931 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_interrupt_fixed.3470998931
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled.1679254896
Short name T657
Test name
Test status
Simulation time 488144187835 ps
CPU time 1356.5 seconds
Started Aug 21 05:38:41 AM UTC 24
Finished Aug 21 06:01:31 AM UTC 24
Peak memory 212756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1679254896 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1679254896
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled_fixed.3361388911
Short name T605
Test name
Test status
Simulation time 324590963632 ps
CPU time 989.79 seconds
Started Aug 21 05:38:43 AM UTC 24
Finished Aug 21 05:55:23 AM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3361388911 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_po
lled_fixed.3361388911
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup.1960214723
Short name T244
Test name
Test status
Simulation time 560684111533 ps
CPU time 931.95 seconds
Started Aug 21 05:38:56 AM UTC 24
Finished Aug 21 05:54:38 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1960214723 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl
_filters_wakeup.1960214723
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup_fixed.945584794
Short name T534
Test name
Test status
Simulation time 392609680466 ps
CPU time 276.99 seconds
Started Aug 21 05:39:03 AM UTC 24
Finished Aug 21 05:43:44 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=945584794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 27.adc_ctrl_filters_wakeup_fixed.945584794
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.3476187431
Short name T559
Test name
Test status
Simulation time 79030878900 ps
CPU time 530.74 seconds
Started Aug 21 05:39:27 AM UTC 24
Finished Aug 21 05:48:23 AM UTC 24
Peak memory 211776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3476187431 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3476187431
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/27.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_lowpower_counter.3675487913
Short name T514
Test name
Test status
Simulation time 29436504566 ps
CPU time 63.42 seconds
Started Aug 21 05:39:26 AM UTC 24
Finished Aug 21 05:40:31 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3675487913 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3675487913
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/27.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_poweron_counter.1813798457
Short name T507
Test name
Test status
Simulation time 3423285171 ps
CPU time 11.12 seconds
Started Aug 21 05:39:21 AM UTC 24
Finished Aug 21 05:39:33 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1813798457 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1813798457
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/27.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_smoke.3251257786
Short name T503
Test name
Test status
Simulation time 6042994583 ps
CPU time 14.46 seconds
Started Aug 21 05:38:40 AM UTC 24
Finished Aug 21 05:38:56 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3251257786 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3251257786
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/27.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3906520912
Short name T510
Test name
Test status
Simulation time 2247068744 ps
CPU time 14.37 seconds
Started Aug 21 05:39:32 AM UTC 24
Finished Aug 21 05:39:47 AM UTC 24
Peak memory 223732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3906520912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3906520912
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_alert_test.2526390974
Short name T521
Test name
Test status
Simulation time 524410672 ps
CPU time 2.4 seconds
Started Aug 21 05:40:57 AM UTC 24
Finished Aug 21 05:41:00 AM UTC 24
Peak memory 211296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2526390974 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2526390974
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/28.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_clock_gating.2365891426
Short name T294
Test name
Test status
Simulation time 483431941828 ps
CPU time 728.38 seconds
Started Aug 21 05:40:32 AM UTC 24
Finished Aug 21 05:52:48 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2365891426 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_c
lock_gating.2365891426
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/28.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt.1149869757
Short name T328
Test name
Test status
Simulation time 161615137671 ps
CPU time 133.75 seconds
Started Aug 21 05:40:02 AM UTC 24
Finished Aug 21 05:42:18 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1149869757 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1149869757
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3609588887
Short name T561
Test name
Test status
Simulation time 491005124373 ps
CPU time 481.45 seconds
Started Aug 21 05:40:18 AM UTC 24
Finished Aug 21 05:48:25 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3609588887 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_interrupt_fixed.3609588887
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled.1605915405
Short name T615
Test name
Test status
Simulation time 331786119550 ps
CPU time 956.43 seconds
Started Aug 21 05:39:48 AM UTC 24
Finished Aug 21 05:55:54 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1605915405 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1605915405
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled_fixed.2942360778
Short name T593
Test name
Test status
Simulation time 331681964475 ps
CPU time 809.67 seconds
Started Aug 21 05:39:51 AM UTC 24
Finished Aug 21 05:53:31 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2942360778 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_po
lled_fixed.2942360778
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.469544653
Short name T111
Test name
Test status
Simulation time 549490998331 ps
CPU time 1308.99 seconds
Started Aug 21 05:40:23 AM UTC 24
Finished Aug 21 06:02:25 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=469544653 -a
ssert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_
filters_wakeup.469544653
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1480672891
Short name T598
Test name
Test status
Simulation time 407908141317 ps
CPU time 824.41 seconds
Started Aug 21 05:40:24 AM UTC 24
Finished Aug 21 05:54:18 AM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1480672891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 28.adc_ctrl_filters_wakeup_fixed.1480672891
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_fsm_reset.2242879641
Short name T353
Test name
Test status
Simulation time 89224317625 ps
CPU time 500.44 seconds
Started Aug 21 05:40:47 AM UTC 24
Finished Aug 21 05:49:13 AM UTC 24
Peak memory 211896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2242879641 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2242879641
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/28.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_lowpower_counter.2275244855
Short name T529
Test name
Test status
Simulation time 32983729570 ps
CPU time 144.8 seconds
Started Aug 21 05:40:43 AM UTC 24
Finished Aug 21 05:43:10 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2275244855 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2275244855
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/28.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_poweron_counter.1110853450
Short name T517
Test name
Test status
Simulation time 4348499849 ps
CPU time 3.98 seconds
Started Aug 21 05:40:37 AM UTC 24
Finished Aug 21 05:40:42 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1110853450 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1110853450
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/28.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_smoke.2041435959
Short name T511
Test name
Test status
Simulation time 5941461602 ps
CPU time 4.11 seconds
Started Aug 21 05:39:45 AM UTC 24
Finished Aug 21 05:39:50 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2041435959 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2041435959
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/28.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all.221814871
Short name T275
Test name
Test status
Simulation time 405738448636 ps
CPU time 512.82 seconds
Started Aug 21 05:40:56 AM UTC 24
Finished Aug 21 05:49:34 AM UTC 24
Peak memory 211784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=221814871 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_str
ess_all.221814871
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3745793427
Short name T519
Test name
Test status
Simulation time 1054898002 ps
CPU time 5.11 seconds
Started Aug 21 05:40:49 AM UTC 24
Finished Aug 21 05:40:55 AM UTC 24
Peak memory 211296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3745793427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3745793427
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_alert_test.4158711402
Short name T531
Test name
Test status
Simulation time 302093237 ps
CPU time 1.47 seconds
Started Aug 21 05:43:22 AM UTC 24
Finished Aug 21 05:43:25 AM UTC 24
Peak memory 209988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4158711402 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.4158711402
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/29.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_clock_gating.2807492158
Short name T283
Test name
Test status
Simulation time 538660898419 ps
CPU time 1332.2 seconds
Started Aug 21 05:42:19 AM UTC 24
Finished Aug 21 06:04:44 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2807492158 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_c
lock_gating.2807492158
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/29.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.4023672404
Short name T551
Test name
Test status
Simulation time 490968619169 ps
CPU time 315.76 seconds
Started Aug 21 05:41:35 AM UTC 24
Finished Aug 21 05:46:55 AM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4023672404 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.4023672404
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3802241380
Short name T671
Test name
Test status
Simulation time 482567077647 ps
CPU time 1327.04 seconds
Started Aug 21 05:41:42 AM UTC 24
Finished Aug 21 06:04:02 AM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3802241380 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_interrupt_fixed.3802241380
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled.2075391544
Short name T218
Test name
Test status
Simulation time 164331244698 ps
CPU time 226.62 seconds
Started Aug 21 05:41:08 AM UTC 24
Finished Aug 21 05:44:58 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2075391544 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2075391544
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled_fixed.1908564393
Short name T544
Test name
Test status
Simulation time 321748701655 ps
CPU time 232.28 seconds
Started Aug 21 05:41:10 AM UTC 24
Finished Aug 21 05:45:06 AM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1908564393 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_po
lled_fixed.1908564393
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup.703082093
Short name T347
Test name
Test status
Simulation time 192863958490 ps
CPU time 476.65 seconds
Started Aug 21 05:41:45 AM UTC 24
Finished Aug 21 05:49:47 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=703082093 -a
ssert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_
filters_wakeup.703082093
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3242606299
Short name T634
Test name
Test status
Simulation time 395566592719 ps
CPU time 1019.98 seconds
Started Aug 21 05:41:59 AM UTC 24
Finished Aug 21 05:59:09 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3242606299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 29.adc_ctrl_filters_wakeup_fixed.3242606299
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_fsm_reset.2216581825
Short name T97
Test name
Test status
Simulation time 118049652354 ps
CPU time 529.24 seconds
Started Aug 21 05:42:54 AM UTC 24
Finished Aug 21 05:51:49 AM UTC 24
Peak memory 211704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2216581825 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2216581825
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/29.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_lowpower_counter.1683847316
Short name T530
Test name
Test status
Simulation time 31743059238 ps
CPU time 27.46 seconds
Started Aug 21 05:42:53 AM UTC 24
Finished Aug 21 05:43:22 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1683847316 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1683847316
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/29.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_poweron_counter.1618685661
Short name T528
Test name
Test status
Simulation time 4209146393 ps
CPU time 3.36 seconds
Started Aug 21 05:42:49 AM UTC 24
Finished Aug 21 05:42:53 AM UTC 24
Peak memory 211352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1618685661 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1618685661
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/29.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_smoke.200149963
Short name T522
Test name
Test status
Simulation time 5949431714 ps
CPU time 7.53 seconds
Started Aug 21 05:41:01 AM UTC 24
Finished Aug 21 05:41:10 AM UTC 24
Peak memory 211200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=200149963 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.200149963
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/29.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.2870334413
Short name T315
Test name
Test status
Simulation time 206716221400 ps
CPU time 42.97 seconds
Started Aug 21 05:43:11 AM UTC 24
Finished Aug 21 05:43:56 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2870334413
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_st
ress_all.2870334413
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2967256027
Short name T532
Test name
Test status
Simulation time 2140292187 ps
CPU time 23.21 seconds
Started Aug 21 05:43:10 AM UTC 24
Finished Aug 21 05:43:35 AM UTC 24
Peak memory 221828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2967256027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2967256027
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.451135825
Short name T43
Test name
Test status
Simulation time 433049849 ps
CPU time 2.63 seconds
Started Aug 21 05:07:32 AM UTC 24
Finished Aug 21 05:07:36 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=451135825 -ass
ert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.451135825
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.2197229146
Short name T55
Test name
Test status
Simulation time 331409363874 ps
CPU time 143.14 seconds
Started Aug 21 05:07:28 AM UTC 24
Finished Aug 21 05:09:55 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2197229146 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2197229146
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.648150162
Short name T199
Test name
Test status
Simulation time 162032443741 ps
CPU time 456.43 seconds
Started Aug 21 05:07:28 AM UTC 24
Finished Aug 21 05:15:11 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=648150162 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.648150162
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3261114463
Short name T404
Test name
Test status
Simulation time 324648427492 ps
CPU time 890.98 seconds
Started Aug 21 05:07:28 AM UTC 24
Finished Aug 21 05:22:29 AM UTC 24
Peak memory 212632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3261114463 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
interrupt_fixed.3261114463
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.855915519
Short name T219
Test name
Test status
Simulation time 320131430886 ps
CPU time 419.87 seconds
Started Aug 21 05:07:27 AM UTC 24
Finished Aug 21 05:14:32 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=855915519 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.855915519
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.1892296936
Short name T370
Test name
Test status
Simulation time 327596512909 ps
CPU time 403.8 seconds
Started Aug 21 05:07:27 AM UTC 24
Finished Aug 21 05:14:16 AM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1892296936 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_pol
led_fixed.1892296936
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.3746030013
Short name T19
Test name
Test status
Simulation time 173870109273 ps
CPU time 104.76 seconds
Started Aug 21 05:07:28 AM UTC 24
Finished Aug 21 05:09:15 AM UTC 24
Peak memory 211696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3746030013 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_
filters_wakeup.3746030013
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.824873463
Short name T88
Test name
Test status
Simulation time 410659419038 ps
CPU time 150.03 seconds
Started Aug 21 05:07:28 AM UTC 24
Finished Aug 21 05:10:01 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=824873463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 3.adc_ctrl_filters_wakeup_fixed.824873463
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.2713565651
Short name T62
Test name
Test status
Simulation time 100593932001 ps
CPU time 429.06 seconds
Started Aug 21 05:07:28 AM UTC 24
Finished Aug 21 05:14:43 AM UTC 24
Peak memory 212092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2713565651 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2713565651
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.3570658221
Short name T30
Test name
Test status
Simulation time 39992682808 ps
CPU time 30.89 seconds
Started Aug 21 05:07:28 AM UTC 24
Finished Aug 21 05:08:01 AM UTC 24
Peak memory 211300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3570658221 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3570658221
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.2404843481
Short name T10
Test name
Test status
Simulation time 5357300322 ps
CPU time 4.3 seconds
Started Aug 21 05:07:28 AM UTC 24
Finished Aug 21 05:07:35 AM UTC 24
Peak memory 211080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2404843481 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2404843481
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.3959565303
Short name T25
Test name
Test status
Simulation time 4260163608 ps
CPU time 7.97 seconds
Started Aug 21 05:07:30 AM UTC 24
Finished Aug 21 05:07:39 AM UTC 24
Peak memory 243560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3959565303 -ass
ert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3959565303
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.3702845671
Short name T27
Test name
Test status
Simulation time 5839649747 ps
CPU time 21.13 seconds
Started Aug 21 05:07:25 AM UTC 24
Finished Aug 21 05:07:48 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3702845671 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3702845671
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.3063717627
Short name T61
Test name
Test status
Simulation time 260576728151 ps
CPU time 931.55 seconds
Started Aug 21 05:07:29 AM UTC 24
Finished Aug 21 05:23:10 AM UTC 24
Peak memory 229320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3063717627
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_str
ess_all.3063717627
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1208653083
Short name T14
Test name
Test status
Simulation time 55340855165 ps
CPU time 33.68 seconds
Started Aug 21 05:07:28 AM UTC 24
Finished Aug 21 05:08:04 AM UTC 24
Peak memory 228108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1208653083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1208653083
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_alert_test.2857832718
Short name T540
Test name
Test status
Simulation time 489308862 ps
CPU time 1.36 seconds
Started Aug 21 05:44:21 AM UTC 24
Finished Aug 21 05:44:24 AM UTC 24
Peak memory 210348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2857832718 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2857832718
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/30.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.1955735862
Short name T337
Test name
Test status
Simulation time 340367960018 ps
CPU time 402.1 seconds
Started Aug 21 05:43:56 AM UTC 24
Finished Aug 21 05:50:43 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1955735862 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_c
lock_gating.1955735862
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/30.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_both.3712702051
Short name T107
Test name
Test status
Simulation time 503788725881 ps
CPU time 1092.9 seconds
Started Aug 21 05:43:58 AM UTC 24
Finished Aug 21 06:02:22 AM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3712702051 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3712702051
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/30.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1159702292
Short name T563
Test name
Test status
Simulation time 168526127665 ps
CPU time 275.1 seconds
Started Aug 21 05:43:48 AM UTC 24
Finished Aug 21 05:48:26 AM UTC 24
Peak memory 211444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1159702292 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_interrupt_fixed.1159702292
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled.2585997856
Short name T581
Test name
Test status
Simulation time 166023642565 ps
CPU time 457.3 seconds
Started Aug 21 05:43:36 AM UTC 24
Finished Aug 21 05:51:18 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2585997856 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2585997856
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled_fixed.3349285926
Short name T558
Test name
Test status
Simulation time 340423957586 ps
CPU time 271.23 seconds
Started Aug 21 05:43:43 AM UTC 24
Finished Aug 21 05:48:18 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3349285926 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_po
lled_fixed.3349285926
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup.4243696671
Short name T710
Test name
Test status
Simulation time 535690409846 ps
CPU time 1563.2 seconds
Started Aug 21 05:43:54 AM UTC 24
Finished Aug 21 06:10:12 AM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4243696671 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl
_filters_wakeup.4243696671
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3788741525
Short name T591
Test name
Test status
Simulation time 395349482721 ps
CPU time 561.3 seconds
Started Aug 21 05:43:55 AM UTC 24
Finished Aug 21 05:53:23 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3788741525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 30.adc_ctrl_filters_wakeup_fixed.3788741525
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_fsm_reset.1911772670
Short name T354
Test name
Test status
Simulation time 100613395644 ps
CPU time 343.93 seconds
Started Aug 21 05:44:07 AM UTC 24
Finished Aug 21 05:49:55 AM UTC 24
Peak memory 212040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1911772670 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1911772670
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/30.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_lowpower_counter.2581222696
Short name T543
Test name
Test status
Simulation time 46095962431 ps
CPU time 48.93 seconds
Started Aug 21 05:44:06 AM UTC 24
Finished Aug 21 05:44:57 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2581222696 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2581222696
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/30.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_poweron_counter.1228831948
Short name T538
Test name
Test status
Simulation time 2899309240 ps
CPU time 6.74 seconds
Started Aug 21 05:43:59 AM UTC 24
Finished Aug 21 05:44:07 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1228831948 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1228831948
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/30.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_smoke.1895401324
Short name T536
Test name
Test status
Simulation time 5981165506 ps
CPU time 26.24 seconds
Started Aug 21 05:43:25 AM UTC 24
Finished Aug 21 05:43:53 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1895401324 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1895401324
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/30.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.1268776969
Short name T265
Test name
Test status
Simulation time 416492430054 ps
CPU time 1356.94 seconds
Started Aug 21 05:44:17 AM UTC 24
Finished Aug 21 06:07:08 AM UTC 24
Peak memory 223272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1268776969
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_st
ress_all.1268776969
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2726331123
Short name T539
Test name
Test status
Simulation time 2986889285 ps
CPU time 7.29 seconds
Started Aug 21 05:44:08 AM UTC 24
Finished Aug 21 05:44:17 AM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2726331123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2726331123
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_alert_test.2908519595
Short name T549
Test name
Test status
Simulation time 435573941 ps
CPU time 1.63 seconds
Started Aug 21 05:46:33 AM UTC 24
Finished Aug 21 05:46:36 AM UTC 24
Peak memory 210348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2908519595 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2908519595
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/31.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_clock_gating.4248974011
Short name T557
Test name
Test status
Simulation time 166746951555 ps
CPU time 185.15 seconds
Started Aug 21 05:45:07 AM UTC 24
Finished Aug 21 05:48:15 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4248974011 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_c
lock_gating.4248974011
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/31.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_both.607577690
Short name T653
Test name
Test status
Simulation time 320121637139 ps
CPU time 960.46 seconds
Started Aug 21 05:45:15 AM UTC 24
Finished Aug 21 06:01:26 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=607577690 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.607577690
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/31.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.3830017505
Short name T597
Test name
Test status
Simulation time 170608567616 ps
CPU time 548.96 seconds
Started Aug 21 05:44:45 AM UTC 24
Finished Aug 21 05:54:00 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3830017505 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3830017505
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2047282289
Short name T560
Test name
Test status
Simulation time 327976252118 ps
CPU time 204.24 seconds
Started Aug 21 05:44:58 AM UTC 24
Finished Aug 21 05:48:25 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2047282289 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_interrupt_fixed.2047282289
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled.3349923792
Short name T570
Test name
Test status
Simulation time 156111490037 ps
CPU time 290.77 seconds
Started Aug 21 05:44:26 AM UTC 24
Finished Aug 21 05:49:21 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3349923792 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3349923792
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled_fixed.740200876
Short name T554
Test name
Test status
Simulation time 163474071630 ps
CPU time 165.24 seconds
Started Aug 21 05:44:36 AM UTC 24
Finished Aug 21 05:47:24 AM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=740200876 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_pol
led_fixed.740200876
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup.3812926680
Short name T618
Test name
Test status
Simulation time 267984887891 ps
CPU time 658.11 seconds
Started Aug 21 05:44:59 AM UTC 24
Finished Aug 21 05:56:04 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3812926680 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl
_filters_wakeup.3812926680
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2233554190
Short name T619
Test name
Test status
Simulation time 199621597551 ps
CPU time 657.75 seconds
Started Aug 21 05:45:04 AM UTC 24
Finished Aug 21 05:56:09 AM UTC 24
Peak memory 211864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2233554190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 31.adc_ctrl_filters_wakeup_fixed.2233554190
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_fsm_reset.154929388
Short name T585
Test name
Test status
Simulation time 75482075107 ps
CPU time 407.29 seconds
Started Aug 21 05:45:53 AM UTC 24
Finished Aug 21 05:52:45 AM UTC 24
Peak memory 211828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=154929388 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.154929388
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/31.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_lowpower_counter.2799445125
Short name T555
Test name
Test status
Simulation time 31645853276 ps
CPU time 121.94 seconds
Started Aug 21 05:45:46 AM UTC 24
Finished Aug 21 05:47:50 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2799445125 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2799445125
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/31.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_poweron_counter.2325261745
Short name T545
Test name
Test status
Simulation time 5060852983 ps
CPU time 12.12 seconds
Started Aug 21 05:45:39 AM UTC 24
Finished Aug 21 05:45:52 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2325261745 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2325261745
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/31.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_smoke.3027557896
Short name T542
Test name
Test status
Simulation time 5741489545 ps
CPU time 8.8 seconds
Started Aug 21 05:44:24 AM UTC 24
Finished Aug 21 05:44:34 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3027557896 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3027557896
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/31.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all.3761149055
Short name T547
Test name
Test status
Simulation time 11792131786 ps
CPU time 12.64 seconds
Started Aug 21 05:46:20 AM UTC 24
Finished Aug 21 05:46:34 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3761149055
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_st
ress_all.3761149055
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2685823002
Short name T546
Test name
Test status
Simulation time 4053904896 ps
CPU time 14.61 seconds
Started Aug 21 05:46:16 AM UTC 24
Finished Aug 21 05:46:32 AM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2685823002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2685823002
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_alert_test.4085556994
Short name T564
Test name
Test status
Simulation time 300694572 ps
CPU time 2.15 seconds
Started Aug 21 05:48:24 AM UTC 24
Finished Aug 21 05:48:27 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4085556994 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.4085556994
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/32.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_both.89137160
Short name T306
Test name
Test status
Simulation time 492821862033 ps
CPU time 1150.85 seconds
Started Aug 21 05:47:51 AM UTC 24
Finished Aug 21 06:07:13 AM UTC 24
Peak memory 212528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=89137160 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.89137160
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.4252066628
Short name T708
Test name
Test status
Simulation time 491450115904 ps
CPU time 1390.16 seconds
Started Aug 21 05:46:40 AM UTC 24
Finished Aug 21 06:10:04 AM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4252066628 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.4252066628
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt_fixed.237591785
Short name T102
Test name
Test status
Simulation time 493319275031 ps
CPU time 322.86 seconds
Started Aug 21 05:46:56 AM UTC 24
Finished Aug 21 05:52:23 AM UTC 24
Peak memory 211612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=237591785 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
interrupt_fixed.237591785
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled.319647779
Short name T594
Test name
Test status
Simulation time 163951317198 ps
CPU time 416.19 seconds
Started Aug 21 05:46:37 AM UTC 24
Finished Aug 21 05:53:38 AM UTC 24
Peak memory 211564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=319647779 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.319647779
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled_fixed.2158258378
Short name T578
Test name
Test status
Simulation time 319062196889 ps
CPU time 226.31 seconds
Started Aug 21 05:46:37 AM UTC 24
Finished Aug 21 05:50:26 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2158258378 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_po
lled_fixed.2158258378
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup.4148710566
Short name T596
Test name
Test status
Simulation time 180006972247 ps
CPU time 413.37 seconds
Started Aug 21 05:47:01 AM UTC 24
Finished Aug 21 05:53:59 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4148710566 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl
_filters_wakeup.4148710566
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3821531891
Short name T614
Test name
Test status
Simulation time 194579506688 ps
CPU time 522.85 seconds
Started Aug 21 05:47:04 AM UTC 24
Finished Aug 21 05:55:53 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3821531891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 32.adc_ctrl_filters_wakeup_fixed.3821531891
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_fsm_reset.1831916335
Short name T627
Test name
Test status
Simulation time 76751703714 ps
CPU time 569.58 seconds
Started Aug 21 05:48:07 AM UTC 24
Finished Aug 21 05:57:43 AM UTC 24
Peak memory 212100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1831916335 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1831916335
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/32.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_lowpower_counter.1084707850
Short name T567
Test name
Test status
Simulation time 34462690257 ps
CPU time 53.2 seconds
Started Aug 21 05:48:00 AM UTC 24
Finished Aug 21 05:48:55 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1084707850 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1084707850
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/32.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_poweron_counter.2091739164
Short name T556
Test name
Test status
Simulation time 2867705101 ps
CPU time 5.13 seconds
Started Aug 21 05:47:53 AM UTC 24
Finished Aug 21 05:47:59 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2091739164 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2091739164
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/32.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_smoke.285238800
Short name T552
Test name
Test status
Simulation time 5945424690 ps
CPU time 23.35 seconds
Started Aug 21 05:46:36 AM UTC 24
Finished Aug 21 05:47:00 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=285238800 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.285238800
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/32.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.339658597
Short name T562
Test name
Test status
Simulation time 1573732624 ps
CPU time 9.8 seconds
Started Aug 21 05:48:15 AM UTC 24
Finished Aug 21 05:48:26 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=339658597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.339658597
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_alert_test.11683655
Short name T573
Test name
Test status
Simulation time 512317993 ps
CPU time 1.84 seconds
Started Aug 21 05:49:33 AM UTC 24
Finished Aug 21 05:49:35 AM UTC 24
Peak memory 209804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11683655 -asse
rt nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.11683655
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/33.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.2191061173
Short name T571
Test name
Test status
Simulation time 176841476258 ps
CPU time 41.8 seconds
Started Aug 21 05:48:46 AM UTC 24
Finished Aug 21 05:49:29 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2191061173 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_c
lock_gating.2191061173
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/33.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_both.1578041120
Short name T325
Test name
Test status
Simulation time 328464488321 ps
CPU time 840.36 seconds
Started Aug 21 05:48:56 AM UTC 24
Finished Aug 21 06:03:06 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1578041120 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1578041120
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/33.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt.43626135
Short name T586
Test name
Test status
Simulation time 164840951575 ps
CPU time 263.98 seconds
Started Aug 21 05:48:27 AM UTC 24
Finished Aug 21 05:52:54 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=43626135 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.43626135
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1000294976
Short name T576
Test name
Test status
Simulation time 169917887369 ps
CPU time 90.38 seconds
Started Aug 21 05:48:28 AM UTC 24
Finished Aug 21 05:50:00 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1000294976 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_interrupt_fixed.1000294976
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled.1003976313
Short name T606
Test name
Test status
Simulation time 166087706846 ps
CPU time 413.53 seconds
Started Aug 21 05:48:26 AM UTC 24
Finished Aug 21 05:55:24 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1003976313 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1003976313
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled_fixed.2654054938
Short name T580
Test name
Test status
Simulation time 329229387513 ps
CPU time 165.94 seconds
Started Aug 21 05:48:27 AM UTC 24
Finished Aug 21 05:51:15 AM UTC 24
Peak memory 211716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2654054938 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_po
lled_fixed.2654054938
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup.4222191042
Short name T592
Test name
Test status
Simulation time 181465851820 ps
CPU time 287.57 seconds
Started Aug 21 05:48:32 AM UTC 24
Finished Aug 21 05:53:24 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4222191042 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl
_filters_wakeup.4222191042
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2174919158
Short name T630
Test name
Test status
Simulation time 192130198243 ps
CPU time 575.75 seconds
Started Aug 21 05:48:38 AM UTC 24
Finished Aug 21 05:58:21 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2174919158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 33.adc_ctrl_filters_wakeup_fixed.2174919158
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_fsm_reset.1350697436
Short name T611
Test name
Test status
Simulation time 79010853587 ps
CPU time 389.34 seconds
Started Aug 21 05:49:14 AM UTC 24
Finished Aug 21 05:55:48 AM UTC 24
Peak memory 211844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1350697436 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1350697436
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/33.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_lowpower_counter.2738056297
Short name T577
Test name
Test status
Simulation time 25384422486 ps
CPU time 76.8 seconds
Started Aug 21 05:49:02 AM UTC 24
Finished Aug 21 05:50:21 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2738056297 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2738056297
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/33.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_poweron_counter.3085791457
Short name T569
Test name
Test status
Simulation time 3322627241 ps
CPU time 1.89 seconds
Started Aug 21 05:48:58 AM UTC 24
Finished Aug 21 05:49:01 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3085791457 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3085791457
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/33.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_smoke.35177213
Short name T565
Test name
Test status
Simulation time 5653923421 ps
CPU time 10.22 seconds
Started Aug 21 05:48:26 AM UTC 24
Finished Aug 21 05:48:37 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35177213 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.35177213
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/33.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all.3523216077
Short name T626
Test name
Test status
Simulation time 224258181333 ps
CPU time 479.67 seconds
Started Aug 21 05:49:31 AM UTC 24
Finished Aug 21 05:57:36 AM UTC 24
Peak memory 221820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3523216077
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_st
ress_all.3523216077
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.722426926
Short name T574
Test name
Test status
Simulation time 6574578899 ps
CPU time 20.77 seconds
Started Aug 21 05:49:21 AM UTC 24
Finished Aug 21 05:49:43 AM UTC 24
Peak memory 221948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=722426926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.722426926
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_alert_test.2513626286
Short name T584
Test name
Test status
Simulation time 435360508 ps
CPU time 1.75 seconds
Started Aug 21 05:51:28 AM UTC 24
Finished Aug 21 05:51:31 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2513626286 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2513626286
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/34.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_clock_gating.770293690
Short name T243
Test name
Test status
Simulation time 179015449060 ps
CPU time 180.68 seconds
Started Aug 21 05:50:22 AM UTC 24
Finished Aug 21 05:53:26 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=770293690 -a
ssert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_cl
ock_gating.770293690
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/34.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_both.2961779205
Short name T648
Test name
Test status
Simulation time 229428010022 ps
CPU time 635.57 seconds
Started Aug 21 05:50:26 AM UTC 24
Finished Aug 21 06:01:09 AM UTC 24
Peak memory 211564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2961779205 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2961779205
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/34.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt.2049450886
Short name T590
Test name
Test status
Simulation time 327634981430 ps
CPU time 211.11 seconds
Started Aug 21 05:49:47 AM UTC 24
Finished Aug 21 05:53:21 AM UTC 24
Peak memory 211576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2049450886 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2049450886
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3205001827
Short name T742
Test name
Test status
Simulation time 497311277904 ps
CPU time 1474.56 seconds
Started Aug 21 05:49:55 AM UTC 24
Finished Aug 21 06:14:45 AM UTC 24
Peak memory 212564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3205001827 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_interrupt_fixed.3205001827
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.2445882416
Short name T672
Test name
Test status
Simulation time 330762790944 ps
CPU time 862.06 seconds
Started Aug 21 05:49:36 AM UTC 24
Finished Aug 21 06:04:07 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2445882416 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2445882416
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled_fixed.4044853088
Short name T718
Test name
Test status
Simulation time 495240084965 ps
CPU time 1259.75 seconds
Started Aug 21 05:49:44 AM UTC 24
Finished Aug 21 06:10:56 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4044853088 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_po
lled_fixed.4044853088
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup.2018706734
Short name T323
Test name
Test status
Simulation time 395125482327 ps
CPU time 78.18 seconds
Started Aug 21 05:49:55 AM UTC 24
Finished Aug 21 05:51:15 AM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2018706734 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl
_filters_wakeup.2018706734
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup_fixed.15271553
Short name T617
Test name
Test status
Simulation time 590440376957 ps
CPU time 356.2 seconds
Started Aug 21 05:50:01 AM UTC 24
Finished Aug 21 05:56:01 AM UTC 24
Peak memory 211600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=15271553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 34.adc_ctrl_filters_wakeup_fixed.15271553
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_fsm_reset.3558063698
Short name T633
Test name
Test status
Simulation time 99638200810 ps
CPU time 462.8 seconds
Started Aug 21 05:51:16 AM UTC 24
Finished Aug 21 05:59:04 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3558063698 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3558063698
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/34.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_lowpower_counter.3449719852
Short name T583
Test name
Test status
Simulation time 42596793094 ps
CPU time 38.11 seconds
Started Aug 21 05:50:49 AM UTC 24
Finished Aug 21 05:51:29 AM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3449719852 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3449719852
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/34.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_poweron_counter.640752940
Short name T579
Test name
Test status
Simulation time 3347540689 ps
CPU time 4.41 seconds
Started Aug 21 05:50:43 AM UTC 24
Finished Aug 21 05:50:49 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=640752940 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.640752940
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/34.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_smoke.2778084165
Short name T575
Test name
Test status
Simulation time 6064933840 ps
CPU time 18.34 seconds
Started Aug 21 05:49:35 AM UTC 24
Finished Aug 21 05:49:54 AM UTC 24
Peak memory 211356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2778084165 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2778084165
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/34.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.2973535398
Short name T109
Test name
Test status
Simulation time 467479644277 ps
CPU time 659.35 seconds
Started Aug 21 05:51:19 AM UTC 24
Finished Aug 21 06:02:24 AM UTC 24
Peak memory 221904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2973535398
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_st
ress_all.2973535398
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.716516893
Short name T91
Test name
Test status
Simulation time 4010103528 ps
CPU time 17.74 seconds
Started Aug 21 05:51:16 AM UTC 24
Finished Aug 21 05:51:34 AM UTC 24
Peak memory 221680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=716516893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.716516893
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_alert_test.2009395217
Short name T587
Test name
Test status
Simulation time 487670414 ps
CPU time 2.95 seconds
Started Aug 21 05:52:55 AM UTC 24
Finished Aug 21 05:52:59 AM UTC 24
Peak memory 211308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2009395217 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2009395217
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/35.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.3264941930
Short name T642
Test name
Test status
Simulation time 161405386002 ps
CPU time 517.76 seconds
Started Aug 21 05:51:55 AM UTC 24
Finished Aug 21 06:00:39 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3264941930 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_c
lock_gating.3264941930
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/35.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.292692931
Short name T612
Test name
Test status
Simulation time 333019414589 ps
CPU time 206.37 seconds
Started Aug 21 05:52:20 AM UTC 24
Finished Aug 21 05:55:50 AM UTC 24
Peak memory 211436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=292692931 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.292692931
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/35.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt.984891220
Short name T314
Test name
Test status
Simulation time 497694644716 ps
CPU time 1674.13 seconds
Started Aug 21 05:51:38 AM UTC 24
Finished Aug 21 06:19:50 AM UTC 24
Peak memory 212608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=984891220 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.984891220
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt_fixed.442522051
Short name T685
Test name
Test status
Simulation time 323007513023 ps
CPU time 825.59 seconds
Started Aug 21 05:51:39 AM UTC 24
Finished Aug 21 06:05:33 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=442522051 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
interrupt_fixed.442522051
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled.652351299
Short name T629
Test name
Test status
Simulation time 491769104009 ps
CPU time 396.03 seconds
Started Aug 21 05:51:31 AM UTC 24
Finished Aug 21 05:58:12 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=652351299 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.652351299
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled_fixed.1429052420
Short name T600
Test name
Test status
Simulation time 325709420496 ps
CPU time 172.83 seconds
Started Aug 21 05:51:35 AM UTC 24
Finished Aug 21 05:54:30 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1429052420 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_po
lled_fixed.1429052420
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup.3061737245
Short name T270
Test name
Test status
Simulation time 362133084710 ps
CPU time 1115.85 seconds
Started Aug 21 05:51:50 AM UTC 24
Finished Aug 21 06:10:38 AM UTC 24
Peak memory 212764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3061737245 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl
_filters_wakeup.3061737245
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1490298922
Short name T631
Test name
Test status
Simulation time 584263579679 ps
CPU time 399.35 seconds
Started Aug 21 05:51:51 AM UTC 24
Finished Aug 21 05:58:35 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1490298922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 35.adc_ctrl_filters_wakeup_fixed.1490298922
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_fsm_reset.3009794622
Short name T666
Test name
Test status
Simulation time 93342474068 ps
CPU time 642.08 seconds
Started Aug 21 05:52:31 AM UTC 24
Finished Aug 21 06:03:20 AM UTC 24
Peak memory 211816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3009794622 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3009794622
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/35.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_lowpower_counter.3951794284
Short name T588
Test name
Test status
Simulation time 36388280110 ps
CPU time 38.19 seconds
Started Aug 21 05:52:24 AM UTC 24
Finished Aug 21 05:53:03 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3951794284 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3951794284
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/35.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_poweron_counter.507313677
Short name T103
Test name
Test status
Simulation time 3180636667 ps
CPU time 7.44 seconds
Started Aug 21 05:52:22 AM UTC 24
Finished Aug 21 05:52:30 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=507313677 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.507313677
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/35.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_smoke.2239291384
Short name T96
Test name
Test status
Simulation time 5843176677 ps
CPU time 7.69 seconds
Started Aug 21 05:51:30 AM UTC 24
Finished Aug 21 05:51:39 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2239291384 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2239291384
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/35.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all.1657394593
Short name T635
Test name
Test status
Simulation time 420389087900 ps
CPU time 403.23 seconds
Started Aug 21 05:52:49 AM UTC 24
Finished Aug 21 05:59:37 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1657394593
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_st
ress_all.1657394593
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3975204219
Short name T92
Test name
Test status
Simulation time 52286608842 ps
CPU time 14.33 seconds
Started Aug 21 05:52:46 AM UTC 24
Finished Aug 21 05:53:01 AM UTC 24
Peak memory 221628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3975204219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3975204219
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_alert_test.1561616514
Short name T599
Test name
Test status
Simulation time 434750132 ps
CPU time 1.5 seconds
Started Aug 21 05:54:19 AM UTC 24
Finished Aug 21 05:54:21 AM UTC 24
Peak memory 210348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1561616514 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1561616514
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/36.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_clock_gating.4031668016
Short name T628
Test name
Test status
Simulation time 171061429157 ps
CPU time 265.26 seconds
Started Aug 21 05:53:24 AM UTC 24
Finished Aug 21 05:57:54 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4031668016 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_c
lock_gating.4031668016
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/36.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_both.4025204107
Short name T291
Test name
Test status
Simulation time 177820559170 ps
CPU time 110.25 seconds
Started Aug 21 05:53:27 AM UTC 24
Finished Aug 21 05:55:19 AM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4025204107 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.4025204107
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/36.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt.944996628
Short name T680
Test name
Test status
Simulation time 495947137651 ps
CPU time 677.6 seconds
Started Aug 21 05:53:15 AM UTC 24
Finished Aug 21 06:04:40 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=944996628 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.944996628
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt_fixed.55683232
Short name T644
Test name
Test status
Simulation time 165314292768 ps
CPU time 456.68 seconds
Started Aug 21 05:53:21 AM UTC 24
Finished Aug 21 06:01:04 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=55683232 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_i
nterrupt_fixed.55683232
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled.4248499013
Short name T768
Test name
Test status
Simulation time 499654636627 ps
CPU time 1544.75 seconds
Started Aug 21 05:53:02 AM UTC 24
Finished Aug 21 06:19:03 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4248499013 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.4248499013
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled_fixed.442675290
Short name T757
Test name
Test status
Simulation time 493403440053 ps
CPU time 1443.4 seconds
Started Aug 21 05:53:04 AM UTC 24
Finished Aug 21 06:17:22 AM UTC 24
Peak memory 212472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=442675290 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_pol
led_fixed.442675290
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup.4146720847
Short name T331
Test name
Test status
Simulation time 386706161469 ps
CPU time 1157.45 seconds
Started Aug 21 05:53:23 AM UTC 24
Finished Aug 21 06:12:53 AM UTC 24
Peak memory 212572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4146720847 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl
_filters_wakeup.4146720847
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2153639870
Short name T655
Test name
Test status
Simulation time 397362441838 ps
CPU time 479.59 seconds
Started Aug 21 05:53:23 AM UTC 24
Finished Aug 21 06:01:29 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2153639870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 36.adc_ctrl_filters_wakeup_fixed.2153639870
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_fsm_reset.4123571858
Short name T114
Test name
Test status
Simulation time 107428678702 ps
CPU time 544.81 seconds
Started Aug 21 05:53:40 AM UTC 24
Finished Aug 21 06:02:51 AM UTC 24
Peak memory 211976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4123571858 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.4123571858
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/36.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_lowpower_counter.2943220942
Short name T601
Test name
Test status
Simulation time 27031269358 ps
CPU time 50.8 seconds
Started Aug 21 05:53:39 AM UTC 24
Finished Aug 21 05:54:31 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2943220942 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2943220942
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/36.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_poweron_counter.3383706332
Short name T595
Test name
Test status
Simulation time 5609157549 ps
CPU time 6.29 seconds
Started Aug 21 05:53:32 AM UTC 24
Finished Aug 21 05:53:39 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3383706332 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3383706332
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/36.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_smoke.2584727223
Short name T589
Test name
Test status
Simulation time 5893885700 ps
CPU time 13.06 seconds
Started Aug 21 05:53:00 AM UTC 24
Finished Aug 21 05:53:14 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2584727223 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2584727223
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/36.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all.3702012759
Short name T112
Test name
Test status
Simulation time 213836217150 ps
CPU time 506.24 seconds
Started Aug 21 05:54:01 AM UTC 24
Finished Aug 21 06:02:33 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3702012759
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_st
ress_all.3702012759
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.239517102
Short name T603
Test name
Test status
Simulation time 175600052274 ps
CPU time 44.01 seconds
Started Aug 21 05:54:00 AM UTC 24
Finished Aug 21 05:54:45 AM UTC 24
Peak memory 221684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=239517102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.239517102
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_alert_test.4021810927
Short name T610
Test name
Test status
Simulation time 413969435 ps
CPU time 1.48 seconds
Started Aug 21 05:55:40 AM UTC 24
Finished Aug 21 05:55:43 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4021810927 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.4021810927
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/37.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_clock_gating.384218775
Short name T340
Test name
Test status
Simulation time 179138687088 ps
CPU time 544.13 seconds
Started Aug 21 05:54:55 AM UTC 24
Finished Aug 21 06:04:05 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=384218775 -a
ssert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_cl
ock_gating.384218775
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/37.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_both.926315928
Short name T646
Test name
Test status
Simulation time 157864379978 ps
CPU time 359.87 seconds
Started Aug 21 05:55:01 AM UTC 24
Finished Aug 21 06:01:05 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=926315928 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.926315928
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/37.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt.305115693
Short name T345
Test name
Test status
Simulation time 319119453492 ps
CPU time 294.81 seconds
Started Aug 21 05:54:32 AM UTC 24
Finished Aug 21 05:59:31 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=305115693 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.305115693
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1535140805
Short name T651
Test name
Test status
Simulation time 159879498872 ps
CPU time 397.5 seconds
Started Aug 21 05:54:36 AM UTC 24
Finished Aug 21 06:01:19 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1535140805 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_interrupt_fixed.1535140805
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled.2381647519
Short name T613
Test name
Test status
Simulation time 168804761900 ps
CPU time 86.09 seconds
Started Aug 21 05:54:22 AM UTC 24
Finished Aug 21 05:55:50 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2381647519 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2381647519
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled_fixed.1030478645
Short name T659
Test name
Test status
Simulation time 165703780216 ps
CPU time 424.66 seconds
Started Aug 21 05:54:31 AM UTC 24
Finished Aug 21 06:01:41 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1030478645 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_po
lled_fixed.1030478645
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup.2334808412
Short name T341
Test name
Test status
Simulation time 363655838825 ps
CPU time 142.75 seconds
Started Aug 21 05:54:38 AM UTC 24
Finished Aug 21 05:57:04 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2334808412 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl
_filters_wakeup.2334808412
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3962748459
Short name T780
Test name
Test status
Simulation time 617054829816 ps
CPU time 1659.58 seconds
Started Aug 21 05:54:46 AM UTC 24
Finished Aug 21 06:22:42 AM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3962748459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 37.adc_ctrl_filters_wakeup_fixed.3962748459
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_fsm_reset.3772915877
Short name T643
Test name
Test status
Simulation time 86085162643 ps
CPU time 313.46 seconds
Started Aug 21 05:55:25 AM UTC 24
Finished Aug 21 06:00:42 AM UTC 24
Peak memory 212092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3772915877 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3772915877
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/37.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_lowpower_counter.3581120939
Short name T621
Test name
Test status
Simulation time 37713270082 ps
CPU time 50.55 seconds
Started Aug 21 05:55:24 AM UTC 24
Finished Aug 21 05:56:16 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3581120939 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3581120939
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/37.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_poweron_counter.2177614254
Short name T607
Test name
Test status
Simulation time 3529865414 ps
CPU time 4.45 seconds
Started Aug 21 05:55:20 AM UTC 24
Finished Aug 21 05:55:25 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2177614254 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2177614254
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/37.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_smoke.2360612000
Short name T602
Test name
Test status
Simulation time 6050312499 ps
CPU time 13.2 seconds
Started Aug 21 05:54:21 AM UTC 24
Finished Aug 21 05:54:35 AM UTC 24
Peak memory 211224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2360612000 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2360612000
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/37.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all.3035267609
Short name T691
Test name
Test status
Simulation time 340546794065 ps
CPU time 687.46 seconds
Started Aug 21 05:55:37 AM UTC 24
Finished Aug 21 06:07:12 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3035267609
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_st
ress_all.3035267609
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.674704912
Short name T608
Test name
Test status
Simulation time 30978483314 ps
CPU time 9.27 seconds
Started Aug 21 05:55:26 AM UTC 24
Finished Aug 21 05:55:36 AM UTC 24
Peak memory 221680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=674704912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.674704912
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_alert_test.4214354049
Short name T624
Test name
Test status
Simulation time 472261090 ps
CPU time 1.82 seconds
Started Aug 21 05:56:48 AM UTC 24
Finished Aug 21 05:56:51 AM UTC 24
Peak memory 210348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4214354049 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.4214354049
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/38.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_clock_gating.3491788247
Short name T309
Test name
Test status
Simulation time 336893785600 ps
CPU time 820.76 seconds
Started Aug 21 05:56:03 AM UTC 24
Finished Aug 21 06:09:53 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3491788247 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_c
lock_gating.3491788247
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/38.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_both.2747193189
Short name T332
Test name
Test status
Simulation time 347083667525 ps
CPU time 1064.35 seconds
Started Aug 21 05:56:05 AM UTC 24
Finished Aug 21 06:14:01 AM UTC 24
Peak memory 212476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2747193189 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2747193189
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt.1715912971
Short name T645
Test name
Test status
Simulation time 329680088362 ps
CPU time 308.77 seconds
Started Aug 21 05:55:51 AM UTC 24
Finished Aug 21 06:01:04 AM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1715912971 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1715912971
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1448549481
Short name T658
Test name
Test status
Simulation time 480058914138 ps
CPU time 342.19 seconds
Started Aug 21 05:55:53 AM UTC 24
Finished Aug 21 06:01:40 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1448549481 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_interrupt_fixed.1448549481
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled.1021520148
Short name T636
Test name
Test status
Simulation time 330428530153 ps
CPU time 228.12 seconds
Started Aug 21 05:55:48 AM UTC 24
Finished Aug 21 05:59:39 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1021520148 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1021520148
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled_fixed.52758452
Short name T688
Test name
Test status
Simulation time 493944220853 ps
CPU time 642.34 seconds
Started Aug 21 05:55:50 AM UTC 24
Finished Aug 21 06:06:39 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=52758452 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_poll
ed_fixed.52758452
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup.3878985135
Short name T343
Test name
Test status
Simulation time 388071887105 ps
CPU time 335.21 seconds
Started Aug 21 05:55:55 AM UTC 24
Finished Aug 21 06:01:35 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3878985135 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl
_filters_wakeup.3878985135
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3551765866
Short name T792
Test name
Test status
Simulation time 620363561688 ps
CPU time 1977.24 seconds
Started Aug 21 05:55:57 AM UTC 24
Finished Aug 21 06:29:13 AM UTC 24
Peak memory 212676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3551765866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 38.adc_ctrl_filters_wakeup_fixed.3551765866
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_lowpower_counter.2065201332
Short name T622
Test name
Test status
Simulation time 32755102897 ps
CPU time 18.85 seconds
Started Aug 21 05:56:14 AM UTC 24
Finished Aug 21 05:56:34 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2065201332 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2065201332
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/38.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_poweron_counter.4209030362
Short name T620
Test name
Test status
Simulation time 4909527630 ps
CPU time 2.04 seconds
Started Aug 21 05:56:10 AM UTC 24
Finished Aug 21 05:56:13 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4209030362 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.4209030362
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/38.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_smoke.1280332349
Short name T616
Test name
Test status
Simulation time 6042058879 ps
CPU time 11.67 seconds
Started Aug 21 05:55:43 AM UTC 24
Finished Aug 21 05:55:56 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1280332349 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1280332349
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/38.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all.2937299513
Short name T321
Test name
Test status
Simulation time 525342324872 ps
CPU time 376.03 seconds
Started Aug 21 05:56:43 AM UTC 24
Finished Aug 21 06:03:04 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2937299513
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_st
ress_all.2937299513
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2857370802
Short name T93
Test name
Test status
Simulation time 4034845846 ps
CPU time 11.19 seconds
Started Aug 21 05:56:35 AM UTC 24
Finished Aug 21 05:56:47 AM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2857370802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2857370802
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_alert_test.851601278
Short name T637
Test name
Test status
Simulation time 519728378 ps
CPU time 2.82 seconds
Started Aug 21 05:59:38 AM UTC 24
Finished Aug 21 05:59:42 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=851601278 -ass
ert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.851601278
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/39.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_clock_gating.531970103
Short name T346
Test name
Test status
Simulation time 554627041447 ps
CPU time 1208.16 seconds
Started Aug 21 05:58:13 AM UTC 24
Finished Aug 21 06:18:33 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=531970103 -a
ssert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_cl
ock_gating.531970103
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/39.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_both.2621556861
Short name T303
Test name
Test status
Simulation time 554971078884 ps
CPU time 1488.63 seconds
Started Aug 21 05:58:22 AM UTC 24
Finished Aug 21 06:23:25 AM UTC 24
Peak memory 212700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2621556861 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2621556861
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/39.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt.3655401066
Short name T641
Test name
Test status
Simulation time 162258894117 ps
CPU time 181.94 seconds
Started Aug 21 05:57:04 AM UTC 24
Finished Aug 21 06:00:09 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3655401066 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3655401066
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3394425464
Short name T705
Test name
Test status
Simulation time 497544818684 ps
CPU time 707.99 seconds
Started Aug 21 05:57:37 AM UTC 24
Finished Aug 21 06:09:32 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3394425464 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_interrupt_fixed.3394425464
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled.2011296026
Short name T669
Test name
Test status
Simulation time 162401777921 ps
CPU time 396.6 seconds
Started Aug 21 05:57:01 AM UTC 24
Finished Aug 21 06:03:42 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2011296026 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2011296026
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled_fixed.3426068930
Short name T670
Test name
Test status
Simulation time 157792673361 ps
CPU time 406.67 seconds
Started Aug 21 05:57:01 AM UTC 24
Finished Aug 21 06:03:53 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3426068930 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_po
lled_fixed.3426068930
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup.4272090567
Short name T110
Test name
Test status
Simulation time 361483970217 ps
CPU time 277.24 seconds
Started Aug 21 05:57:44 AM UTC 24
Finished Aug 21 06:02:25 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4272090567 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl
_filters_wakeup.4272090567
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup_fixed.4261513461
Short name T677
Test name
Test status
Simulation time 391909162382 ps
CPU time 389.05 seconds
Started Aug 21 05:57:55 AM UTC 24
Finished Aug 21 06:04:29 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4261513461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 39.adc_ctrl_filters_wakeup_fixed.4261513461
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_fsm_reset.3735381158
Short name T716
Test name
Test status
Simulation time 117886268746 ps
CPU time 690.59 seconds
Started Aug 21 05:59:04 AM UTC 24
Finished Aug 21 06:10:42 AM UTC 24
Peak memory 211896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3735381158 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3735381158
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/39.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_lowpower_counter.1652600334
Short name T640
Test name
Test status
Simulation time 27039781071 ps
CPU time 57.24 seconds
Started Aug 21 05:58:54 AM UTC 24
Finished Aug 21 05:59:53 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1652600334 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1652600334
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/39.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_poweron_counter.2590558370
Short name T632
Test name
Test status
Simulation time 3664674212 ps
CPU time 15.69 seconds
Started Aug 21 05:58:36 AM UTC 24
Finished Aug 21 05:58:53 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2590558370 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2590558370
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/39.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_smoke.1065809055
Short name T625
Test name
Test status
Simulation time 5874284320 ps
CPU time 7.3 seconds
Started Aug 21 05:56:52 AM UTC 24
Finished Aug 21 05:57:01 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1065809055 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1065809055
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/39.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all.4259303983
Short name T702
Test name
Test status
Simulation time 198642007684 ps
CPU time 589.71 seconds
Started Aug 21 05:59:32 AM UTC 24
Finished Aug 21 06:09:29 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4259303983
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_st
ress_all.4259303983
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1993569303
Short name T639
Test name
Test status
Simulation time 6940770726 ps
CPU time 40.05 seconds
Started Aug 21 05:59:10 AM UTC 24
Finished Aug 21 05:59:52 AM UTC 24
Peak memory 221956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1993569303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1993569303
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.742283767
Short name T28
Test name
Test status
Simulation time 379666131 ps
CPU time 1.61 seconds
Started Aug 21 05:07:49 AM UTC 24
Finished Aug 21 05:07:51 AM UTC 24
Peak memory 210344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=742283767 -ass
ert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.742283767
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.228172292
Short name T237
Test name
Test status
Simulation time 585124332080 ps
CPU time 1709.87 seconds
Started Aug 21 05:07:39 AM UTC 24
Finished Aug 21 05:36:26 AM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=228172292 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.228172292
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.1637716242
Short name T148
Test name
Test status
Simulation time 162515228776 ps
CPU time 191.58 seconds
Started Aug 21 05:07:36 AM UTC 24
Finished Aug 21 05:10:51 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1637716242 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1637716242
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.733605628
Short name T184
Test name
Test status
Simulation time 331200557459 ps
CPU time 552.45 seconds
Started Aug 21 05:07:35 AM UTC 24
Finished Aug 21 05:16:54 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=733605628 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.733605628
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.249174330
Short name T16
Test name
Test status
Simulation time 167243599564 ps
CPU time 48.69 seconds
Started Aug 21 05:07:36 AM UTC 24
Finished Aug 21 05:08:26 AM UTC 24
Peak memory 211436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=249174330 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_poll
ed_fixed.249174330
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.467071615
Short name T373
Test name
Test status
Simulation time 205017667896 ps
CPU time 470.02 seconds
Started Aug 21 05:07:38 AM UTC 24
Finished Aug 21 05:15:34 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=467071615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 4.adc_ctrl_filters_wakeup_fixed.467071615
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.167171138
Short name T46
Test name
Test status
Simulation time 34246126176 ps
CPU time 40.86 seconds
Started Aug 21 05:07:44 AM UTC 24
Finished Aug 21 05:08:26 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=167171138 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.167171138
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.1342077191
Short name T29
Test name
Test status
Simulation time 4302112192 ps
CPU time 17.99 seconds
Started Aug 21 05:07:42 AM UTC 24
Finished Aug 21 05:08:01 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1342077191 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1342077191
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.933688846
Short name T44
Test name
Test status
Simulation time 7582019809 ps
CPU time 22.05 seconds
Started Aug 21 05:07:49 AM UTC 24
Finished Aug 21 05:08:12 AM UTC 24
Peak memory 243504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=933688846 -asse
rt nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.933688846
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.2966840251
Short name T24
Test name
Test status
Simulation time 5939970122 ps
CPU time 4.88 seconds
Started Aug 21 05:07:32 AM UTC 24
Finished Aug 21 05:07:38 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2966840251 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2966840251
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.3313508581
Short name T145
Test name
Test status
Simulation time 201791937419 ps
CPU time 588.58 seconds
Started Aug 21 05:07:47 AM UTC 24
Finished Aug 21 05:17:42 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3313508581
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_str
ess_all.3313508581
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1996398544
Short name T15
Test name
Test status
Simulation time 11672861357 ps
CPU time 32.17 seconds
Started Aug 21 05:07:45 AM UTC 24
Finished Aug 21 05:08:19 AM UTC 24
Peak memory 221768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1996398544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1996398544
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_alert_test.2301822452
Short name T650
Test name
Test status
Simulation time 442316984 ps
CPU time 1.34 seconds
Started Aug 21 06:01:11 AM UTC 24
Finished Aug 21 06:01:13 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2301822452 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2301822452
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/40.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_clock_gating.2640955171
Short name T728
Test name
Test status
Simulation time 523840195526 ps
CPU time 678.06 seconds
Started Aug 21 06:00:32 AM UTC 24
Finished Aug 21 06:11:58 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2640955171 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_c
lock_gating.2640955171
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/40.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt.1824720273
Short name T173
Test name
Test status
Simulation time 329808860833 ps
CPU time 95.52 seconds
Started Aug 21 05:59:53 AM UTC 24
Finished Aug 21 06:01:30 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1824720273 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1824720273
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1683305782
Short name T664
Test name
Test status
Simulation time 168270588250 ps
CPU time 185.42 seconds
Started Aug 21 05:59:54 AM UTC 24
Finished Aug 21 06:03:02 AM UTC 24
Peak memory 211864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1683305782 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_interrupt_fixed.1683305782
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled.1720075058
Short name T656
Test name
Test status
Simulation time 163520192119 ps
CPU time 106.23 seconds
Started Aug 21 05:59:43 AM UTC 24
Finished Aug 21 06:01:31 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1720075058 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1720075058
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled_fixed.1624991772
Short name T769
Test name
Test status
Simulation time 494792214470 ps
CPU time 1155.95 seconds
Started Aug 21 05:59:48 AM UTC 24
Finished Aug 21 06:19:14 AM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1624991772 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_po
lled_fixed.1624991772
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup.3703524769
Short name T663
Test name
Test status
Simulation time 189211086168 ps
CPU time 169.2 seconds
Started Aug 21 06:00:10 AM UTC 24
Finished Aug 21 06:03:02 AM UTC 24
Peak memory 211756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3703524769 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl
_filters_wakeup.3703524769
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2405843313
Short name T113
Test name
Test status
Simulation time 201340654865 ps
CPU time 143.47 seconds
Started Aug 21 06:00:22 AM UTC 24
Finished Aug 21 06:02:48 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2405843313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 40.adc_ctrl_filters_wakeup_fixed.2405843313
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_fsm_reset.3589689035
Short name T697
Test name
Test status
Simulation time 86479458486 ps
CPU time 463.81 seconds
Started Aug 21 06:01:05 AM UTC 24
Finished Aug 21 06:08:54 AM UTC 24
Peak memory 212092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3589689035 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3589689035
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/40.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_lowpower_counter.1053558008
Short name T675
Test name
Test status
Simulation time 45134812521 ps
CPU time 198.28 seconds
Started Aug 21 06:01:04 AM UTC 24
Finished Aug 21 06:04:26 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1053558008 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1053558008
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/40.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_poweron_counter.241029582
Short name T647
Test name
Test status
Simulation time 5265283099 ps
CPU time 24.1 seconds
Started Aug 21 06:00:43 AM UTC 24
Finished Aug 21 06:01:09 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=241029582 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.241029582
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/40.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_smoke.4199149441
Short name T638
Test name
Test status
Simulation time 5907814753 ps
CPU time 5.6 seconds
Started Aug 21 05:59:40 AM UTC 24
Finished Aug 21 05:59:47 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4199149441 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.4199149441
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/40.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all.478311898
Short name T696
Test name
Test status
Simulation time 99027118460 ps
CPU time 435.57 seconds
Started Aug 21 06:01:09 AM UTC 24
Finished Aug 21 06:08:30 AM UTC 24
Peak memory 211784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=478311898 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_str
ess_all.478311898
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2077877036
Short name T654
Test name
Test status
Simulation time 16473430314 ps
CPU time 20.27 seconds
Started Aug 21 06:01:05 AM UTC 24
Finished Aug 21 06:01:27 AM UTC 24
Peak memory 221900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2077877036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2077877036
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_alert_test.996118352
Short name T661
Test name
Test status
Simulation time 494732806 ps
CPU time 2.71 seconds
Started Aug 21 06:01:56 AM UTC 24
Finished Aug 21 06:01:59 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=996118352 -ass
ert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.996118352
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/41.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.2403964962
Short name T272
Test name
Test status
Simulation time 359842470924 ps
CPU time 140.56 seconds
Started Aug 21 06:01:31 AM UTC 24
Finished Aug 21 06:03:54 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2403964962 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_c
lock_gating.2403964962
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/41.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt.3515403387
Short name T174
Test name
Test status
Simulation time 490461620488 ps
CPU time 113.77 seconds
Started Aug 21 06:01:22 AM UTC 24
Finished Aug 21 06:03:18 AM UTC 24
Peak memory 211436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3515403387 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3515403387
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1514931609
Short name T706
Test name
Test status
Simulation time 161947192646 ps
CPU time 491.7 seconds
Started Aug 21 06:01:27 AM UTC 24
Finished Aug 21 06:09:45 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1514931609 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_interrupt_fixed.1514931609
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled.423764704
Short name T707
Test name
Test status
Simulation time 325144796169 ps
CPU time 508.46 seconds
Started Aug 21 06:01:14 AM UTC 24
Finished Aug 21 06:09:48 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=423764704 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.423764704
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled_fixed.3904530962
Short name T791
Test name
Test status
Simulation time 495157746644 ps
CPU time 1576.44 seconds
Started Aug 21 06:01:20 AM UTC 24
Finished Aug 21 06:27:52 AM UTC 24
Peak memory 212564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3904530962 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_po
lled_fixed.3904530962
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup.1211808686
Short name T713
Test name
Test status
Simulation time 527952568349 ps
CPU time 521.61 seconds
Started Aug 21 06:01:28 AM UTC 24
Finished Aug 21 06:10:16 AM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1211808686 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl
_filters_wakeup.1211808686
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2338186595
Short name T695
Test name
Test status
Simulation time 212473213843 ps
CPU time 407.08 seconds
Started Aug 21 06:01:29 AM UTC 24
Finished Aug 21 06:08:21 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2338186595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 41.adc_ctrl_filters_wakeup_fixed.2338186595
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_fsm_reset.2124178765
Short name T700
Test name
Test status
Simulation time 107527593223 ps
CPU time 462.24 seconds
Started Aug 21 06:01:37 AM UTC 24
Finished Aug 21 06:09:25 AM UTC 24
Peak memory 211844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2124178765 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2124178765
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/41.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_lowpower_counter.2417633488
Short name T108
Test name
Test status
Simulation time 44532374871 ps
CPU time 45.64 seconds
Started Aug 21 06:01:36 AM UTC 24
Finished Aug 21 06:02:23 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2417633488 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2417633488
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/41.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_poweron_counter.2964677517
Short name T660
Test name
Test status
Simulation time 4626092810 ps
CPU time 20.98 seconds
Started Aug 21 06:01:32 AM UTC 24
Finished Aug 21 06:01:55 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2964677517 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2964677517
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/41.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_smoke.2960163532
Short name T652
Test name
Test status
Simulation time 6166948893 ps
CPU time 9.47 seconds
Started Aug 21 06:01:11 AM UTC 24
Finished Aug 21 06:01:21 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2960163532 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2960163532
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/41.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all.3371601278
Short name T721
Test name
Test status
Simulation time 381826874891 ps
CPU time 562.34 seconds
Started Aug 21 06:01:41 AM UTC 24
Finished Aug 21 06:11:10 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3371601278
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_st
ress_all.3371601278
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_alert_test.1421257475
Short name T665
Test name
Test status
Simulation time 513160505 ps
CPU time 1.37 seconds
Started Aug 21 06:03:05 AM UTC 24
Finished Aug 21 06:03:07 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1421257475 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1421257475
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/42.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_both.3154081258
Short name T693
Test name
Test status
Simulation time 580872890058 ps
CPU time 323.53 seconds
Started Aug 21 06:02:33 AM UTC 24
Finished Aug 21 06:08:01 AM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3154081258 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3154081258
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/42.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt.69389325
Short name T784
Test name
Test status
Simulation time 489460426735 ps
CPU time 1349.69 seconds
Started Aug 21 06:02:23 AM UTC 24
Finished Aug 21 06:25:07 AM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=69389325 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.69389325
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt_fixed.4061809884
Short name T678
Test name
Test status
Simulation time 498841519500 ps
CPU time 122.66 seconds
Started Aug 21 06:02:24 AM UTC 24
Finished Aug 21 06:04:29 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4061809884 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_interrupt_fixed.4061809884
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled.1640000526
Short name T731
Test name
Test status
Simulation time 326128526404 ps
CPU time 614.28 seconds
Started Aug 21 06:02:02 AM UTC 24
Finished Aug 21 06:12:23 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1640000526 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1640000526
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled_fixed.770187290
Short name T774
Test name
Test status
Simulation time 331804484289 ps
CPU time 1075.77 seconds
Started Aug 21 06:02:09 AM UTC 24
Finished Aug 21 06:20:16 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=770187290 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_pol
led_fixed.770187290
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup.2197540843
Short name T682
Test name
Test status
Simulation time 426422778675 ps
CPU time 156.23 seconds
Started Aug 21 06:02:25 AM UTC 24
Finished Aug 21 06:05:04 AM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2197540843 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl
_filters_wakeup.2197540843
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2159066619
Short name T703
Test name
Test status
Simulation time 199569791125 ps
CPU time 417.24 seconds
Started Aug 21 06:02:26 AM UTC 24
Finished Aug 21 06:09:29 AM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2159066619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 42.adc_ctrl_filters_wakeup_fixed.2159066619
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_fsm_reset.2113359966
Short name T712
Test name
Test status
Simulation time 77886509274 ps
CPU time 428.63 seconds
Started Aug 21 06:03:02 AM UTC 24
Finished Aug 21 06:10:15 AM UTC 24
Peak memory 211816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2113359966 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2113359966
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/42.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_lowpower_counter.611232572
Short name T668
Test name
Test status
Simulation time 28749628220 ps
CPU time 34.37 seconds
Started Aug 21 06:02:51 AM UTC 24
Finished Aug 21 06:03:27 AM UTC 24
Peak memory 211196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=611232572 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.611232572
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/42.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_poweron_counter.3278390597
Short name T662
Test name
Test status
Simulation time 5114027361 ps
CPU time 12.09 seconds
Started Aug 21 06:02:48 AM UTC 24
Finished Aug 21 06:03:02 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3278390597 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3278390597
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/42.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_smoke.2855596500
Short name T106
Test name
Test status
Simulation time 5590428751 ps
CPU time 7.12 seconds
Started Aug 21 06:02:00 AM UTC 24
Finished Aug 21 06:02:08 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2855596500 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2855596500
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/42.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all.2592677063
Short name T797
Test name
Test status
Simulation time 481761103017 ps
CPU time 1694.84 seconds
Started Aug 21 06:03:03 AM UTC 24
Finished Aug 21 06:31:34 AM UTC 24
Peak memory 212880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2592677063
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_st
ress_all.2592677063
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1461294386
Short name T329
Test name
Test status
Simulation time 185352363014 ps
CPU time 41.06 seconds
Started Aug 21 06:03:03 AM UTC 24
Finished Aug 21 06:03:45 AM UTC 24
Peak memory 221628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1461294386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1461294386
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_alert_test.2028968104
Short name T676
Test name
Test status
Simulation time 297214423 ps
CPU time 2.02 seconds
Started Aug 21 06:04:25 AM UTC 24
Finished Aug 21 06:04:28 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2028968104 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2028968104
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/43.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_clock_gating.1124708194
Short name T344
Test name
Test status
Simulation time 402242017479 ps
CPU time 1043.37 seconds
Started Aug 21 06:03:45 AM UTC 24
Finished Aug 21 06:21:19 AM UTC 24
Peak memory 212760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1124708194 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_c
lock_gating.1124708194
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/43.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.1748995254
Short name T319
Test name
Test status
Simulation time 542013442440 ps
CPU time 1488.95 seconds
Started Aug 21 06:03:53 AM UTC 24
Finished Aug 21 06:28:58 AM UTC 24
Peak memory 212832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1748995254 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1748995254
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/43.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt.3228974676
Short name T787
Test name
Test status
Simulation time 481722977927 ps
CPU time 1368.64 seconds
Started Aug 21 06:03:21 AM UTC 24
Finished Aug 21 06:26:23 AM UTC 24
Peak memory 212584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3228974676 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3228974676
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2938834445
Short name T690
Test name
Test status
Simulation time 333902280412 ps
CPU time 223.47 seconds
Started Aug 21 06:03:22 AM UTC 24
Finished Aug 21 06:07:08 AM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2938834445 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_interrupt_fixed.2938834445
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled.2331829766
Short name T752
Test name
Test status
Simulation time 322110016644 ps
CPU time 743.14 seconds
Started Aug 21 06:03:08 AM UTC 24
Finished Aug 21 06:15:38 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2331829766 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2331829766
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled_fixed.587752406
Short name T788
Test name
Test status
Simulation time 491212060359 ps
CPU time 1412.55 seconds
Started Aug 21 06:03:19 AM UTC 24
Finished Aug 21 06:27:06 AM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=587752406 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_pol
led_fixed.587752406
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup.3068094841
Short name T684
Test name
Test status
Simulation time 165483488050 ps
CPU time 119.98 seconds
Started Aug 21 06:03:28 AM UTC 24
Finished Aug 21 06:05:30 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3068094841 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl
_filters_wakeup.3068094841
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup_fixed.714247962
Short name T776
Test name
Test status
Simulation time 400202072327 ps
CPU time 1060.7 seconds
Started Aug 21 06:03:43 AM UTC 24
Finished Aug 21 06:21:35 AM UTC 24
Peak memory 212484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=714247962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 43.adc_ctrl_filters_wakeup_fixed.714247962
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_fsm_reset.3123711070
Short name T750
Test name
Test status
Simulation time 120828284192 ps
CPU time 680.62 seconds
Started Aug 21 06:04:06 AM UTC 24
Finished Aug 21 06:15:34 AM UTC 24
Peak memory 211784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3123711070 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3123711070
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/43.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_lowpower_counter.2762156691
Short name T681
Test name
Test status
Simulation time 40151807319 ps
CPU time 35.31 seconds
Started Aug 21 06:04:03 AM UTC 24
Finished Aug 21 06:04:41 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2762156691 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2762156691
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/43.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_poweron_counter.260345840
Short name T673
Test name
Test status
Simulation time 5311197237 ps
CPU time 22.86 seconds
Started Aug 21 06:03:54 AM UTC 24
Finished Aug 21 06:04:18 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=260345840 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.260345840
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/43.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_smoke.663886419
Short name T667
Test name
Test status
Simulation time 5748878512 ps
CPU time 13.33 seconds
Started Aug 21 06:03:07 AM UTC 24
Finished Aug 21 06:03:21 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=663886419 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.663886419
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/43.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all.980249460
Short name T214
Test name
Test status
Simulation time 157186271044 ps
CPU time 1000.14 seconds
Started Aug 21 06:04:20 AM UTC 24
Finished Aug 21 06:21:11 AM UTC 24
Peak memory 211848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=980249460 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_str
ess_all.980249460
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2735643089
Short name T674
Test name
Test status
Simulation time 4656747572 ps
CPU time 15.26 seconds
Started Aug 21 06:04:08 AM UTC 24
Finished Aug 21 06:04:24 AM UTC 24
Peak memory 211876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2735643089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2735643089
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_alert_test.2512852843
Short name T687
Test name
Test status
Simulation time 527010576 ps
CPU time 1.96 seconds
Started Aug 21 06:06:14 AM UTC 24
Finished Aug 21 06:06:17 AM UTC 24
Peak memory 210348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2512852843 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2512852843
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/44.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_clock_gating.342288825
Short name T176
Test name
Test status
Simulation time 605854451864 ps
CPU time 210.5 seconds
Started Aug 21 06:04:44 AM UTC 24
Finished Aug 21 06:08:18 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=342288825 -a
ssert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_cl
ock_gating.342288825
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/44.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt.1830131462
Short name T778
Test name
Test status
Simulation time 331109798248 ps
CPU time 1063.72 seconds
Started Aug 21 06:04:30 AM UTC 24
Finished Aug 21 06:22:25 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1830131462 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1830131462
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1271447238
Short name T692
Test name
Test status
Simulation time 162565580906 ps
CPU time 164.74 seconds
Started Aug 21 06:04:36 AM UTC 24
Finished Aug 21 06:07:24 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1271447238 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_interrupt_fixed.1271447238
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled.2567300106
Short name T786
Test name
Test status
Simulation time 499283364047 ps
CPU time 1291.2 seconds
Started Aug 21 06:04:29 AM UTC 24
Finished Aug 21 06:26:13 AM UTC 24
Peak memory 212160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2567300106 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2567300106
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled_fixed.1605936479
Short name T761
Test name
Test status
Simulation time 490393353487 ps
CPU time 792.82 seconds
Started Aug 21 06:04:29 AM UTC 24
Finished Aug 21 06:17:50 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1605936479 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_po
lled_fixed.1605936479
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.4133997456
Short name T790
Test name
Test status
Simulation time 528406306179 ps
CPU time 1367.34 seconds
Started Aug 21 06:04:41 AM UTC 24
Finished Aug 21 06:27:41 AM UTC 24
Peak memory 212632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4133997456 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl
_filters_wakeup.4133997456
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1882875085
Short name T754
Test name
Test status
Simulation time 611026469658 ps
CPU time 680.66 seconds
Started Aug 21 06:04:41 AM UTC 24
Finished Aug 21 06:16:10 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1882875085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 44.adc_ctrl_filters_wakeup_fixed.1882875085
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_fsm_reset.3747551532
Short name T734
Test name
Test status
Simulation time 99755162588 ps
CPU time 436.95 seconds
Started Aug 21 06:05:31 AM UTC 24
Finished Aug 21 06:12:52 AM UTC 24
Peak memory 211712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3747551532 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3747551532
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/44.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_lowpower_counter.3867625921
Short name T686
Test name
Test status
Simulation time 24814567023 ps
CPU time 59.46 seconds
Started Aug 21 06:05:13 AM UTC 24
Finished Aug 21 06:06:14 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3867625921 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3867625921
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/44.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_poweron_counter.1214994259
Short name T683
Test name
Test status
Simulation time 5045698910 ps
CPU time 6.27 seconds
Started Aug 21 06:05:05 AM UTC 24
Finished Aug 21 06:05:12 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1214994259 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1214994259
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/44.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_smoke.1925763419
Short name T679
Test name
Test status
Simulation time 5704402025 ps
CPU time 7.22 seconds
Started Aug 21 06:04:27 AM UTC 24
Finished Aug 21 06:04:35 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1925763419 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1925763419
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/44.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.3171476645
Short name T351
Test name
Test status
Simulation time 84315741505 ps
CPU time 303.88 seconds
Started Aug 21 06:05:50 AM UTC 24
Finished Aug 21 06:10:57 AM UTC 24
Peak memory 221900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3171476645
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_st
ress_all.3171476645
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_alert_test.363797128
Short name T698
Test name
Test status
Simulation time 492931121 ps
CPU time 2.79 seconds
Started Aug 21 06:08:54 AM UTC 24
Finished Aug 21 06:08:58 AM UTC 24
Peak memory 211296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=363797128 -ass
ert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.363797128
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/45.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.669926336
Short name T759
Test name
Test status
Simulation time 186889523108 ps
CPU time 611.05 seconds
Started Aug 21 06:07:25 AM UTC 24
Finished Aug 21 06:17:43 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=669926336 -a
ssert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_cl
ock_gating.669926336
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/45.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_both.3112108278
Short name T717
Test name
Test status
Simulation time 167082774783 ps
CPU time 164.75 seconds
Started Aug 21 06:08:02 AM UTC 24
Finished Aug 21 06:10:49 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3112108278 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3112108278
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/45.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt.1819157293
Short name T730
Test name
Test status
Simulation time 162870657021 ps
CPU time 301.43 seconds
Started Aug 21 06:07:09 AM UTC 24
Finished Aug 21 06:12:15 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1819157293 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1819157293
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1598248220
Short name T740
Test name
Test status
Simulation time 165871708896 ps
CPU time 439.32 seconds
Started Aug 21 06:07:09 AM UTC 24
Finished Aug 21 06:14:34 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1598248220 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_interrupt_fixed.1598248220
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled.82189105
Short name T741
Test name
Test status
Simulation time 171022459596 ps
CPU time 472.14 seconds
Started Aug 21 06:06:40 AM UTC 24
Finished Aug 21 06:14:38 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=82189105 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.82189105
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled_fixed.2481173886
Short name T729
Test name
Test status
Simulation time 493348725018 ps
CPU time 320.59 seconds
Started Aug 21 06:06:41 AM UTC 24
Finished Aug 21 06:12:06 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2481173886 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_po
lled_fixed.2481173886
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup.2295805598
Short name T746
Test name
Test status
Simulation time 527660654168 ps
CPU time 479.16 seconds
Started Aug 21 06:07:12 AM UTC 24
Finished Aug 21 06:15:18 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2295805598 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl
_filters_wakeup.2295805598
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2195672753
Short name T771
Test name
Test status
Simulation time 214557247913 ps
CPU time 751.12 seconds
Started Aug 21 06:07:15 AM UTC 24
Finished Aug 21 06:19:54 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2195672753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 45.adc_ctrl_filters_wakeup_fixed.2195672753
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_fsm_reset.210346234
Short name T779
Test name
Test status
Simulation time 95302135257 ps
CPU time 839.26 seconds
Started Aug 21 06:08:21 AM UTC 24
Finished Aug 21 06:22:30 AM UTC 24
Peak memory 211820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=210346234 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.210346234
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/45.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_lowpower_counter.1646959444
Short name T699
Test name
Test status
Simulation time 40796123142 ps
CPU time 51.46 seconds
Started Aug 21 06:08:19 AM UTC 24
Finished Aug 21 06:09:12 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1646959444 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1646959444
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/45.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_poweron_counter.4153797521
Short name T694
Test name
Test status
Simulation time 4846309335 ps
CPU time 10.5 seconds
Started Aug 21 06:08:09 AM UTC 24
Finished Aug 21 06:08:21 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4153797521 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4153797521
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/45.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_smoke.699289304
Short name T689
Test name
Test status
Simulation time 5621838174 ps
CPU time 20.63 seconds
Started Aug 21 06:06:18 AM UTC 24
Finished Aug 21 06:06:40 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=699289304 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.699289304
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/45.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all.684442193
Short name T785
Test name
Test status
Simulation time 336164565917 ps
CPU time 995.82 seconds
Started Aug 21 06:08:31 AM UTC 24
Finished Aug 21 06:25:18 AM UTC 24
Peak memory 212776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=684442193 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_str
ess_all.684442193
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2002323775
Short name T73
Test name
Test status
Simulation time 14437124705 ps
CPU time 45.87 seconds
Started Aug 21 06:08:22 AM UTC 24
Finished Aug 21 06:09:10 AM UTC 24
Peak memory 221976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2002323775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2002323775
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_alert_test.1539218694
Short name T711
Test name
Test status
Simulation time 403060319 ps
CPU time 1.67 seconds
Started Aug 21 06:10:12 AM UTC 24
Finished Aug 21 06:10:15 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1539218694 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1539218694
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/46.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_clock_gating.1423076426
Short name T764
Test name
Test status
Simulation time 165906368902 ps
CPU time 513.82 seconds
Started Aug 21 06:09:30 AM UTC 24
Finished Aug 21 06:18:10 AM UTC 24
Peak memory 211440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1423076426 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_c
lock_gating.1423076426
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/46.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_both.925862486
Short name T739
Test name
Test status
Simulation time 326033379257 ps
CPU time 268.35 seconds
Started Aug 21 06:09:33 AM UTC 24
Finished Aug 21 06:14:05 AM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=925862486 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.925862486
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/46.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt.4197846400
Short name T756
Test name
Test status
Simulation time 164627544421 ps
CPU time 440.33 seconds
Started Aug 21 06:09:26 AM UTC 24
Finished Aug 21 06:16:51 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4197846400 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.4197846400
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3829267198
Short name T753
Test name
Test status
Simulation time 166355026443 ps
CPU time 376.72 seconds
Started Aug 21 06:09:26 AM UTC 24
Finished Aug 21 06:15:47 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3829267198 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_interrupt_fixed.3829267198
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.2307761746
Short name T720
Test name
Test status
Simulation time 170718805488 ps
CPU time 117.27 seconds
Started Aug 21 06:09:11 AM UTC 24
Finished Aug 21 06:11:10 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2307761746 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2307761746
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled_fixed.2682509357
Short name T732
Test name
Test status
Simulation time 331996718662 ps
CPU time 191.2 seconds
Started Aug 21 06:09:13 AM UTC 24
Finished Aug 21 06:12:27 AM UTC 24
Peak memory 211448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2682509357 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_po
lled_fixed.2682509357
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup.3977048266
Short name T308
Test name
Test status
Simulation time 516761315123 ps
CPU time 756.36 seconds
Started Aug 21 06:09:26 AM UTC 24
Finished Aug 21 06:22:10 AM UTC 24
Peak memory 211756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3977048266 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl
_filters_wakeup.3977048266
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3308459596
Short name T751
Test name
Test status
Simulation time 607016435081 ps
CPU time 363.18 seconds
Started Aug 21 06:09:30 AM UTC 24
Finished Aug 21 06:15:38 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3308459596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 46.adc_ctrl_filters_wakeup_fixed.3308459596
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_fsm_reset.3690063395
Short name T782
Test name
Test status
Simulation time 131969446697 ps
CPU time 785.88 seconds
Started Aug 21 06:09:53 AM UTC 24
Finished Aug 21 06:23:07 AM UTC 24
Peak memory 211712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3690063395 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3690063395
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/46.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_lowpower_counter.4009532356
Short name T715
Test name
Test status
Simulation time 43327548182 ps
CPU time 47.28 seconds
Started Aug 21 06:09:49 AM UTC 24
Finished Aug 21 06:10:38 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4009532356 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.4009532356
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/46.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_poweron_counter.3416068452
Short name T709
Test name
Test status
Simulation time 5389667186 ps
CPU time 24.71 seconds
Started Aug 21 06:09:45 AM UTC 24
Finished Aug 21 06:10:11 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3416068452 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3416068452
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/46.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_smoke.4210516452
Short name T701
Test name
Test status
Simulation time 5785828572 ps
CPU time 24.62 seconds
Started Aug 21 06:08:59 AM UTC 24
Finished Aug 21 06:09:25 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4210516452 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.4210516452
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/46.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all.771922131
Short name T758
Test name
Test status
Simulation time 209526325865 ps
CPU time 443.08 seconds
Started Aug 21 06:10:11 AM UTC 24
Finished Aug 21 06:17:39 AM UTC 24
Peak memory 211824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=771922131 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_str
ess_all.771922131
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3602364341
Short name T295
Test name
Test status
Simulation time 7397171557 ps
CPU time 21.56 seconds
Started Aug 21 06:10:05 AM UTC 24
Finished Aug 21 06:10:28 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3602364341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3602364341
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_alert_test.1819577656
Short name T724
Test name
Test status
Simulation time 300957961 ps
CPU time 1.49 seconds
Started Aug 21 06:11:26 AM UTC 24
Finished Aug 21 06:11:28 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1819577656 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1819577656
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/47.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_clock_gating.1793188868
Short name T743
Test name
Test status
Simulation time 330196378212 ps
CPU time 251.83 seconds
Started Aug 21 06:10:42 AM UTC 24
Finished Aug 21 06:14:57 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1793188868 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_c
lock_gating.1793188868
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/47.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_both.2673485216
Short name T284
Test name
Test status
Simulation time 375176660453 ps
CPU time 313.75 seconds
Started Aug 21 06:10:50 AM UTC 24
Finished Aug 21 06:16:08 AM UTC 24
Peak memory 211820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2673485216 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2673485216
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/47.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt.3556753256
Short name T777
Test name
Test status
Simulation time 168789157209 ps
CPU time 671.48 seconds
Started Aug 21 06:10:25 AM UTC 24
Finished Aug 21 06:21:45 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3556753256 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3556753256
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2690734458
Short name T773
Test name
Test status
Simulation time 330023369382 ps
CPU time 574.29 seconds
Started Aug 21 06:10:29 AM UTC 24
Finished Aug 21 06:20:10 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2690734458 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_interrupt_fixed.2690734458
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled.513213163
Short name T770
Test name
Test status
Simulation time 158341355301 ps
CPU time 532.4 seconds
Started Aug 21 06:10:17 AM UTC 24
Finished Aug 21 06:19:15 AM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=513213163 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.513213163
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled_fixed.3628951678
Short name T727
Test name
Test status
Simulation time 334177138086 ps
CPU time 95.9 seconds
Started Aug 21 06:10:17 AM UTC 24
Finished Aug 21 06:11:55 AM UTC 24
Peak memory 211452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3628951678 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_po
lled_fixed.3628951678
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1429169150
Short name T772
Test name
Test status
Simulation time 614085615804 ps
CPU time 554.82 seconds
Started Aug 21 06:10:39 AM UTC 24
Finished Aug 21 06:20:01 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1429169150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 47.adc_ctrl_filters_wakeup_fixed.1429169150
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_fsm_reset.916746802
Short name T775
Test name
Test status
Simulation time 109367192746 ps
CPU time 551.25 seconds
Started Aug 21 06:11:04 AM UTC 24
Finished Aug 21 06:20:22 AM UTC 24
Peak memory 211816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=916746802 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.916746802
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/47.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_lowpower_counter.2610978997
Short name T723
Test name
Test status
Simulation time 23316956053 ps
CPU time 25.74 seconds
Started Aug 21 06:10:58 AM UTC 24
Finished Aug 21 06:11:25 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2610978997 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2610978997
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/47.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_poweron_counter.1871490681
Short name T719
Test name
Test status
Simulation time 4384942222 ps
CPU time 5.36 seconds
Started Aug 21 06:10:57 AM UTC 24
Finished Aug 21 06:11:04 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1871490681 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1871490681
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/47.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_smoke.1065542655
Short name T714
Test name
Test status
Simulation time 5804072812 ps
CPU time 6.56 seconds
Started Aug 21 06:10:15 AM UTC 24
Finished Aug 21 06:10:23 AM UTC 24
Peak memory 211224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1065542655 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1065542655
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/47.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all.1170659650
Short name T726
Test name
Test status
Simulation time 181711695832 ps
CPU time 32.09 seconds
Started Aug 21 06:11:10 AM UTC 24
Finished Aug 21 06:11:44 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1170659650
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_st
ress_all.1170659650
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2241069180
Short name T722
Test name
Test status
Simulation time 3202578818 ps
CPU time 13.45 seconds
Started Aug 21 06:11:10 AM UTC 24
Finished Aug 21 06:11:25 AM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2241069180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2241069180
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_alert_test.2308460181
Short name T737
Test name
Test status
Simulation time 359171662 ps
CPU time 2.21 seconds
Started Aug 21 06:13:42 AM UTC 24
Finished Aug 21 06:13:45 AM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2308460181 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2308460181
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/48.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.2559139247
Short name T799
Test name
Test status
Simulation time 489265242823 ps
CPU time 1516.11 seconds
Started Aug 21 06:12:15 AM UTC 24
Finished Aug 21 06:37:47 AM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2559139247 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_c
lock_gating.2559139247
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/48.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.3009929820
Short name T783
Test name
Test status
Simulation time 560127086219 ps
CPU time 752.69 seconds
Started Aug 21 06:12:24 AM UTC 24
Finished Aug 21 06:25:05 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3009929820 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3009929820
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/48.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt.746012205
Short name T762
Test name
Test status
Simulation time 159645631126 ps
CPU time 370.76 seconds
Started Aug 21 06:11:45 AM UTC 24
Finished Aug 21 06:18:00 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=746012205 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.746012205
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3116794370
Short name T744
Test name
Test status
Simulation time 331556983419 ps
CPU time 190.28 seconds
Started Aug 21 06:11:56 AM UTC 24
Finished Aug 21 06:15:09 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3116794370 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_interrupt_fixed.3116794370
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled_fixed.2230763122
Short name T704
Test name
Test status
Simulation time 327234625299 ps
CPU time 203.72 seconds
Started Aug 21 06:11:39 AM UTC 24
Finished Aug 21 06:15:05 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2230763122 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_po
lled_fixed.2230763122
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.2278466533
Short name T760
Test name
Test status
Simulation time 183715616533 ps
CPU time 339.73 seconds
Started Aug 21 06:11:59 AM UTC 24
Finished Aug 21 06:17:43 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2278466533 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl
_filters_wakeup.2278466533
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup_fixed.4040598668
Short name T795
Test name
Test status
Simulation time 381333663910 ps
CPU time 1102.34 seconds
Started Aug 21 06:12:06 AM UTC 24
Finished Aug 21 06:30:39 AM UTC 24
Peak memory 212564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4040598668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 48.adc_ctrl_filters_wakeup_fixed.4040598668
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_fsm_reset.1117163585
Short name T767
Test name
Test status
Simulation time 73407321159 ps
CPU time 359.9 seconds
Started Aug 21 06:12:53 AM UTC 24
Finished Aug 21 06:18:56 AM UTC 24
Peak memory 211820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1117163585 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1117163585
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/48.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_lowpower_counter.442218835
Short name T736
Test name
Test status
Simulation time 28399974432 ps
CPU time 65.45 seconds
Started Aug 21 06:12:33 AM UTC 24
Finished Aug 21 06:13:41 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=442218835 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.442218835
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/48.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_poweron_counter.2315073701
Short name T733
Test name
Test status
Simulation time 2964483725 ps
CPU time 4.06 seconds
Started Aug 21 06:12:27 AM UTC 24
Finished Aug 21 06:12:33 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2315073701 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2315073701
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/48.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_smoke.3460578566
Short name T725
Test name
Test status
Simulation time 5556901512 ps
CPU time 11.08 seconds
Started Aug 21 06:11:26 AM UTC 24
Finished Aug 21 06:11:38 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3460578566 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3460578566
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/48.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all.1901200983
Short name T247
Test name
Test status
Simulation time 548805066187 ps
CPU time 166.47 seconds
Started Aug 21 06:13:32 AM UTC 24
Finished Aug 21 06:16:21 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1901200983
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_st
ress_all.1901200983
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3617518135
Short name T735
Test name
Test status
Simulation time 71006819657 ps
CPU time 35.88 seconds
Started Aug 21 06:12:54 AM UTC 24
Finished Aug 21 06:13:31 AM UTC 24
Peak memory 228272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3617518135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3617518135
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_alert_test.167643761
Short name T749
Test name
Test status
Simulation time 428242814 ps
CPU time 2.14 seconds
Started Aug 21 06:15:27 AM UTC 24
Finished Aug 21 06:15:30 AM UTC 24
Peak memory 211296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=167643761 -ass
ert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.167643761
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/49.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.2542651165
Short name T766
Test name
Test status
Simulation time 354129808604 ps
CPU time 216.87 seconds
Started Aug 21 06:14:58 AM UTC 24
Finished Aug 21 06:18:38 AM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2542651165 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_c
lock_gating.2542651165
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/49.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.2008996461
Short name T796
Test name
Test status
Simulation time 358499914447 ps
CPU time 946.16 seconds
Started Aug 21 06:15:06 AM UTC 24
Finished Aug 21 06:31:01 AM UTC 24
Peak memory 212884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2008996461 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2008996461
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/49.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.2463102754
Short name T781
Test name
Test status
Simulation time 485600930547 ps
CPU time 527.87 seconds
Started Aug 21 06:14:06 AM UTC 24
Finished Aug 21 06:23:00 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2463102754 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2463102754
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3355256968
Short name T794
Test name
Test status
Simulation time 336398554857 ps
CPU time 941.35 seconds
Started Aug 21 06:14:35 AM UTC 24
Finished Aug 21 06:30:26 AM UTC 24
Peak memory 212608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3355256968 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_interrupt_fixed.3355256968
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled.1261019849
Short name T755
Test name
Test status
Simulation time 171145545641 ps
CPU time 130.61 seconds
Started Aug 21 06:14:00 AM UTC 24
Finished Aug 21 06:16:13 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1261019849 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1261019849
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled_fixed.1775252064
Short name T765
Test name
Test status
Simulation time 325257053633 ps
CPU time 246.76 seconds
Started Aug 21 06:14:01 AM UTC 24
Finished Aug 21 06:18:12 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1775252064 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_po
lled_fixed.1775252064
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.3767262282
Short name T798
Test name
Test status
Simulation time 531495438578 ps
CPU time 1281.44 seconds
Started Aug 21 06:14:39 AM UTC 24
Finished Aug 21 06:36:13 AM UTC 24
Peak memory 212572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3767262282 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl
_filters_wakeup.3767262282
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup_fixed.550917072
Short name T793
Test name
Test status
Simulation time 610558808279 ps
CPU time 923.4 seconds
Started Aug 21 06:14:46 AM UTC 24
Finished Aug 21 06:30:18 AM UTC 24
Peak memory 212624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=550917072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 49.adc_ctrl_filters_wakeup_fixed.550917072
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_fsm_reset.1260163261
Short name T789
Test name
Test status
Simulation time 121685858656 ps
CPU time 702.08 seconds
Started Aug 21 06:15:18 AM UTC 24
Finished Aug 21 06:27:08 AM UTC 24
Peak memory 211784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1260163261 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1260163261
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/49.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_lowpower_counter.3001052417
Short name T747
Test name
Test status
Simulation time 23949716254 ps
CPU time 5.72 seconds
Started Aug 21 06:15:11 AM UTC 24
Finished Aug 21 06:15:18 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3001052417 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3001052417
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/49.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_poweron_counter.2766122917
Short name T745
Test name
Test status
Simulation time 4400869123 ps
CPU time 5.93 seconds
Started Aug 21 06:15:10 AM UTC 24
Finished Aug 21 06:15:17 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2766122917 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2766122917
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/49.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_smoke.875922794
Short name T738
Test name
Test status
Simulation time 5849377821 ps
CPU time 12.45 seconds
Started Aug 21 06:13:46 AM UTC 24
Finished Aug 21 06:14:00 AM UTC 24
Peak memory 211200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=875922794 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.875922794
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/49.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.3749302377
Short name T763
Test name
Test status
Simulation time 195099640677 ps
CPU time 168.97 seconds
Started Aug 21 06:15:18 AM UTC 24
Finished Aug 21 06:18:10 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3749302377
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_st
ress_all.3749302377
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3033130928
Short name T748
Test name
Test status
Simulation time 2387375016 ps
CPU time 7.2 seconds
Started Aug 21 06:15:18 AM UTC 24
Finished Aug 21 06:15:26 AM UTC 24
Peak memory 221748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3033130928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3033130928
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.2518529672
Short name T56
Test name
Test status
Simulation time 370562383 ps
CPU time 0.99 seconds
Started Aug 21 05:08:55 AM UTC 24
Finished Aug 21 05:08:58 AM UTC 24
Peak memory 210344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2518529672 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2518529672
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.3225298065
Short name T21
Test name
Test status
Simulation time 167016950281 ps
CPU time 63.57 seconds
Started Aug 21 05:08:20 AM UTC 24
Finished Aug 21 05:09:25 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3225298065 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3225298065
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.1389664491
Short name T139
Test name
Test status
Simulation time 165991510061 ps
CPU time 294.69 seconds
Started Aug 21 05:08:02 AM UTC 24
Finished Aug 21 05:13:01 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1389664491 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1389664491
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.279307295
Short name T229
Test name
Test status
Simulation time 327613504188 ps
CPU time 209.27 seconds
Started Aug 21 05:08:05 AM UTC 24
Finished Aug 21 05:11:37 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=279307295 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_i
nterrupt_fixed.279307295
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.2077552080
Short name T142
Test name
Test status
Simulation time 164706335527 ps
CPU time 476.46 seconds
Started Aug 21 05:08:02 AM UTC 24
Finished Aug 21 05:16:04 AM UTC 24
Peak memory 211628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2077552080 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2077552080
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.4206153657
Short name T361
Test name
Test status
Simulation time 334127926649 ps
CPU time 233.32 seconds
Started Aug 21 05:08:02 AM UTC 24
Finished Aug 21 05:11:59 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4206153657 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_pol
led_fixed.4206153657
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.462309579
Short name T378
Test name
Test status
Simulation time 201167038147 ps
CPU time 490.95 seconds
Started Aug 21 05:08:13 AM UTC 24
Finished Aug 21 05:16:29 AM UTC 24
Peak memory 211448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=462309579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 5.adc_ctrl_filters_wakeup_fixed.462309579
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.1997615935
Short name T59
Test name
Test status
Simulation time 78816126196 ps
CPU time 426.6 seconds
Started Aug 21 05:08:27 AM UTC 24
Finished Aug 21 05:15:38 AM UTC 24
Peak memory 211624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1997615935 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1997615935
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.4155711229
Short name T158
Test name
Test status
Simulation time 28610272264 ps
CPU time 94.45 seconds
Started Aug 21 05:08:27 AM UTC 24
Finished Aug 21 05:10:03 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4155711229 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.4155711229
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.2831154407
Short name T48
Test name
Test status
Simulation time 4732029476 ps
CPU time 9.9 seconds
Started Aug 21 05:08:27 AM UTC 24
Finished Aug 21 05:08:38 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2831154407 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2831154407
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.2893941799
Short name T45
Test name
Test status
Simulation time 5836582710 ps
CPU time 24.42 seconds
Started Aug 21 05:07:52 AM UTC 24
Finished Aug 21 05:08:17 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2893941799 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2893941799
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.293956845
Short name T60
Test name
Test status
Simulation time 134731262587 ps
CPU time 361.81 seconds
Started Aug 21 05:08:38 AM UTC 24
Finished Aug 21 05:14:44 AM UTC 24
Peak memory 221884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=293956845 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stre
ss_all.293956845
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3176306977
Short name T31
Test name
Test status
Simulation time 2602237408 ps
CPU time 15.4 seconds
Started Aug 21 05:08:38 AM UTC 24
Finished Aug 21 05:08:55 AM UTC 24
Peak memory 221956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3176306977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3176306977
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.1239473948
Short name T146
Test name
Test status
Simulation time 413205736 ps
CPU time 2.55 seconds
Started Aug 21 05:10:07 AM UTC 24
Finished Aug 21 05:10:10 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1239473948 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1239473948
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.2684031225
Short name T143
Test name
Test status
Simulation time 160053804645 ps
CPU time 394.01 seconds
Started Aug 21 05:09:29 AM UTC 24
Finished Aug 21 05:16:08 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2684031225 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2684031225
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.2860201511
Short name T168
Test name
Test status
Simulation time 335395729105 ps
CPU time 671.85 seconds
Started Aug 21 05:09:15 AM UTC 24
Finished Aug 21 05:20:34 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2860201511 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2860201511
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1446495406
Short name T177
Test name
Test status
Simulation time 496605201513 ps
CPU time 429.75 seconds
Started Aug 21 05:09:17 AM UTC 24
Finished Aug 21 05:16:32 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1446495406 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
interrupt_fixed.1446495406
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.3365620463
Short name T170
Test name
Test status
Simulation time 487516385244 ps
CPU time 1164.43 seconds
Started Aug 21 05:09:06 AM UTC 24
Finished Aug 21 05:28:42 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3365620463 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3365620463
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.1135472827
Short name T363
Test name
Test status
Simulation time 170252352970 ps
CPU time 174.56 seconds
Started Aug 21 05:09:09 AM UTC 24
Finished Aug 21 05:12:07 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1135472827 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_pol
led_fixed.1135472827
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.704833534
Short name T163
Test name
Test status
Simulation time 357494989125 ps
CPU time 949.75 seconds
Started Aug 21 05:09:19 AM UTC 24
Finished Aug 21 05:25:18 AM UTC 24
Peak memory 212620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=704833534 -a
ssert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_f
ilters_wakeup.704833534
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2448966253
Short name T504
Test name
Test status
Simulation time 590975304610 ps
CPU time 1779.94 seconds
Started Aug 21 05:09:21 AM UTC 24
Finished Aug 21 05:39:19 AM UTC 24
Peak memory 212572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2448966253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 6.adc_ctrl_filters_wakeup_fixed.2448966253
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2912094837
Short name T63
Test name
Test status
Simulation time 89539311849 ps
CPU time 506.98 seconds
Started Aug 21 05:09:57 AM UTC 24
Finished Aug 21 05:18:30 AM UTC 24
Peak memory 212040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2912094837 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2912094837
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.1544128381
Short name T358
Test name
Test status
Simulation time 34158547148 ps
CPU time 77.94 seconds
Started Aug 21 05:09:57 AM UTC 24
Finished Aug 21 05:11:16 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1544128381 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1544128381
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.44263652
Short name T157
Test name
Test status
Simulation time 4610577892 ps
CPU time 9.39 seconds
Started Aug 21 05:09:43 AM UTC 24
Finished Aug 21 05:09:54 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=44263652 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.44263652
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.3530797995
Short name T89
Test name
Test status
Simulation time 5982903711 ps
CPU time 7.47 seconds
Started Aug 21 05:08:59 AM UTC 24
Finished Aug 21 05:09:07 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3530797995 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3530797995
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.3972498931
Short name T78
Test name
Test status
Simulation time 3902975273 ps
CPU time 14.53 seconds
Started Aug 21 05:10:04 AM UTC 24
Finished Aug 21 05:10:19 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3972498931
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_str
ess_all.3972498931
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.2865663753
Short name T360
Test name
Test status
Simulation time 343244911 ps
CPU time 1.2 seconds
Started Aug 21 05:11:33 AM UTC 24
Finished Aug 21 05:11:35 AM UTC 24
Peak memory 210344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2865663753 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2865663753
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.2209230606
Short name T178
Test name
Test status
Simulation time 394080804922 ps
CPU time 362.64 seconds
Started Aug 21 05:10:27 AM UTC 24
Finished Aug 21 05:16:34 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2209230606 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_cl
ock_gating.2209230606
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.2888435484
Short name T161
Test name
Test status
Simulation time 162682488502 ps
CPU time 280.21 seconds
Started Aug 21 05:10:36 AM UTC 24
Finished Aug 21 05:15:20 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2888435484 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2888435484
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.3990475963
Short name T195
Test name
Test status
Simulation time 496125396835 ps
CPU time 1181.75 seconds
Started Aug 21 05:10:19 AM UTC 24
Finished Aug 21 05:30:13 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3990475963 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3990475963
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2561999237
Short name T200
Test name
Test status
Simulation time 335827450331 ps
CPU time 286.56 seconds
Started Aug 21 05:10:20 AM UTC 24
Finished Aug 21 05:15:11 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2561999237 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
interrupt_fixed.2561999237
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.2764001281
Short name T310
Test name
Test status
Simulation time 492230515865 ps
CPU time 1357.02 seconds
Started Aug 21 05:10:16 AM UTC 24
Finished Aug 21 05:33:08 AM UTC 24
Peak memory 212768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2764001281 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2764001281
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.954197677
Short name T382
Test name
Test status
Simulation time 323572611140 ps
CPU time 421.79 seconds
Started Aug 21 05:10:17 AM UTC 24
Finished Aug 21 05:17:23 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=954197677 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_poll
ed_fixed.954197677
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.1867703864
Short name T152
Test name
Test status
Simulation time 335571862766 ps
CPU time 351.26 seconds
Started Aug 21 05:10:21 AM UTC 24
Finished Aug 21 05:16:17 AM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1867703864 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_
filters_wakeup.1867703864
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.292288826
Short name T473
Test name
Test status
Simulation time 603272646205 ps
CPU time 1392.25 seconds
Started Aug 21 05:10:22 AM UTC 24
Finished Aug 21 05:33:48 AM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=292288826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 7.adc_ctrl_filters_wakeup_fixed.292288826
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.2023205604
Short name T205
Test name
Test status
Simulation time 93259220238 ps
CPU time 365.64 seconds
Started Aug 21 05:11:12 AM UTC 24
Finished Aug 21 05:17:22 AM UTC 24
Peak memory 211704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2023205604 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2023205604
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.2033129229
Short name T359
Test name
Test status
Simulation time 31964616684 ps
CPU time 24.93 seconds
Started Aug 21 05:11:04 AM UTC 24
Finished Aug 21 05:11:30 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2033129229 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2033129229
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.522605978
Short name T149
Test name
Test status
Simulation time 4959950587 ps
CPU time 10.77 seconds
Started Aug 21 05:10:51 AM UTC 24
Finished Aug 21 05:11:03 AM UTC 24
Peak memory 211296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=522605978 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.522605978
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.456935119
Short name T147
Test name
Test status
Simulation time 5639547261 ps
CPU time 2.57 seconds
Started Aug 21 05:10:13 AM UTC 24
Finished Aug 21 05:10:17 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=456935119 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.456935119
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.4289858487
Short name T40
Test name
Test status
Simulation time 667997478618 ps
CPU time 1012.71 seconds
Started Aug 21 05:11:31 AM UTC 24
Finished Aug 21 05:28:35 AM UTC 24
Peak memory 212608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4289858487
-assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_str
ess_all.4289858487
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2384983941
Short name T50
Test name
Test status
Simulation time 25135936729 ps
CPU time 12.88 seconds
Started Aug 21 05:11:17 AM UTC 24
Finished Aug 21 05:11:31 AM UTC 24
Peak memory 221768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2384983941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2384983941
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.2447461172
Short name T366
Test name
Test status
Simulation time 413760888 ps
CPU time 1.35 seconds
Started Aug 21 05:13:06 AM UTC 24
Finished Aug 21 05:13:08 AM UTC 24
Peak memory 209804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2447461172 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2447461172
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.1528963993
Short name T260
Test name
Test status
Simulation time 326591415675 ps
CPU time 1085.52 seconds
Started Aug 21 05:11:50 AM UTC 24
Finished Aug 21 05:30:08 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1528963993 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1528963993
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2640377787
Short name T387
Test name
Test status
Simulation time 497054506162 ps
CPU time 426.57 seconds
Started Aug 21 05:11:56 AM UTC 24
Finished Aug 21 05:19:07 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2640377787 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
interrupt_fixed.2640377787
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.3722331142
Short name T140
Test name
Test status
Simulation time 164183642714 ps
CPU time 171.01 seconds
Started Aug 21 05:11:38 AM UTC 24
Finished Aug 21 05:14:31 AM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3722331142 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3722331142
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.1597881712
Short name T377
Test name
Test status
Simulation time 329629356306 ps
CPU time 248.66 seconds
Started Aug 21 05:11:40 AM UTC 24
Finished Aug 21 05:15:52 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1597881712 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_pol
led_fixed.1597881712
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.3236249667
Short name T141
Test name
Test status
Simulation time 348418405619 ps
CPU time 168.79 seconds
Started Aug 21 05:12:00 AM UTC 24
Finished Aug 21 05:14:52 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3236249667 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_
filters_wakeup.3236249667
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3365010393
Short name T254
Test name
Test status
Simulation time 194358701980 ps
CPU time 115.43 seconds
Started Aug 21 05:12:01 AM UTC 24
Finished Aug 21 05:13:58 AM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3365010393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 8.adc_ctrl_filters_wakeup_fixed.3365010393
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.1532451439
Short name T211
Test name
Test status
Simulation time 85946041102 ps
CPU time 749.14 seconds
Started Aug 21 05:12:37 AM UTC 24
Finished Aug 21 05:25:15 AM UTC 24
Peak memory 212088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1532451439 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1532451439
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.3246460516
Short name T369
Test name
Test status
Simulation time 29361668341 ps
CPU time 86.24 seconds
Started Aug 21 05:12:15 AM UTC 24
Finished Aug 21 05:13:43 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3246460516 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3246460516
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.4192957412
Short name T364
Test name
Test status
Simulation time 3700586414 ps
CPU time 5.65 seconds
Started Aug 21 05:12:08 AM UTC 24
Finished Aug 21 05:12:15 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4192957412 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.4192957412
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.489277154
Short name T362
Test name
Test status
Simulation time 5652395618 ps
CPU time 23.93 seconds
Started Aug 21 05:11:36 AM UTC 24
Finished Aug 21 05:12:01 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=489277154 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.489277154
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.718845989
Short name T187
Test name
Test status
Simulation time 245199996511 ps
CPU time 304.68 seconds
Started Aug 21 05:13:02 AM UTC 24
Finished Aug 21 05:18:10 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=718845989 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stre
ss_all.718845989
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1104911606
Short name T51
Test name
Test status
Simulation time 11430544559 ps
CPU time 15.82 seconds
Started Aug 21 05:12:47 AM UTC 24
Finished Aug 21 05:13:04 AM UTC 24
Peak memory 211696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1104911606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1104911606
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.1332137131
Short name T198
Test name
Test status
Simulation time 409398534 ps
CPU time 1.25 seconds
Started Aug 21 05:14:58 AM UTC 24
Finished Aug 21 05:15:00 AM UTC 24
Peak memory 210344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1332137131 -as
sert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1332137131
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.1886959167
Short name T180
Test name
Test status
Simulation time 161614872151 ps
CPU time 132.41 seconds
Started Aug 21 05:14:32 AM UTC 24
Finished Aug 21 05:16:47 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1886959167 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1886959167
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.4181993537
Short name T185
Test name
Test status
Simulation time 326936088117 ps
CPU time 203.45 seconds
Started Aug 21 05:13:30 AM UTC 24
Finished Aug 21 05:16:56 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4181993537 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.4181993537
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1931813968
Short name T401
Test name
Test status
Simulation time 164723921590 ps
CPU time 484.75 seconds
Started Aug 21 05:13:44 AM UTC 24
Finished Aug 21 05:21:55 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1931813968 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
interrupt_fixed.1931813968
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.11423876
Short name T402
Test name
Test status
Simulation time 325289178549 ps
CPU time 516.32 seconds
Started Aug 21 05:13:16 AM UTC 24
Finished Aug 21 05:21:59 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11423876 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polle
d_fixed.11423876
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3623675884
Short name T403
Test name
Test status
Simulation time 620399104949 ps
CPU time 491.03 seconds
Started Aug 21 05:14:00 AM UTC 24
Finished Aug 21 05:22:17 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3623675884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 9.adc_ctrl_filters_wakeup_fixed.3623675884
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.3223436320
Short name T209
Test name
Test status
Simulation time 119101646301 ps
CPU time 563.7 seconds
Started Aug 21 05:14:44 AM UTC 24
Finished Aug 21 05:24:13 AM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3223436320 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3223436320
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_fsm_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.1308576044
Short name T201
Test name
Test status
Simulation time 41097934568 ps
CPU time 28.09 seconds
Started Aug 21 05:14:43 AM UTC 24
Finished Aug 21 05:15:12 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1308576044 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1308576044
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_lowpower_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.3200056743
Short name T371
Test name
Test status
Simulation time 4967355976 ps
CPU time 6.85 seconds
Started Aug 21 05:14:33 AM UTC 24
Finished Aug 21 05:14:41 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3200056743 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3200056743
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_poweron_counter/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.1466487148
Short name T367
Test name
Test status
Simulation time 6011602162 ps
CPU time 7.28 seconds
Started Aug 21 05:13:07 AM UTC 24
Finished Aug 21 05:13:15 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1466487148 -assert nopostproc +UVM_TESTN
AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1466487148
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.409344299
Short name T226
Test name
Test status
Simulation time 218467085322 ps
CPU time 708.75 seconds
Started Aug 21 05:14:53 AM UTC 24
Finished Aug 21 05:26:50 AM UTC 24
Peak memory 211696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=409344299 -
assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stre
ss_all.409344299
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3699290002
Short name T52
Test name
Test status
Simulation time 70460778661 ps
CPU time 38.63 seconds
Started Aug 21 05:14:45 AM UTC 24
Finished Aug 21 05:15:25 AM UTC 24
Peak memory 222292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3699290002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3699290002
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest
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