ADC_CTRL Lint Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Tool: ASCENTLINT

Build Mode Flow Infos Flow Warnings Flow Errors Lint Infos Lint Warnings Lint Errors
default 0 0 0 196 1 1

Messages for Build Mode 'default'

Lint Infos

I   FSM_DEFAULT_REQ:   prim_sync_reqack.sv:253   Next state register 'gen_nrz_hs_protocol.src_fsm_ns' has no assignment in the default branch of the case statement for this finite state machine                 New                            

I   FSM_DEFAULT_REQ:   prim_sync_reqack.sv:297   Next state register 'gen_nrz_hs_protocol.dst_fsm_ns' has no assignment in the default branch of the case statement for this finite state machine                 New                            

I   FSM_DEFAULT_REQ:   prim_diff_decode.sv:158   Next state register 'gen_async.state_d' has no assignment in the default branch of the case statement for this finite state machine                              New                            

I   NESTED_SUBPROG:   tlul_pkg.sv:143   Function 'prim_mubi_pkg::mubi4_test_invalid' is called from within a function                 New                            

I   CASE_INC:   adc_ctrl_fsm.sv:207        Case statement tag not specified for value 'b10001 and 14 other values                 New                            

I   CASE_INC:   prim_alert_sender.sv:199   Case statement tag not specified for value 'b111                                       New                            

I   CASE_INC:   prim_diff_decode.sv:115    Case statement tag not specified for value 'b11                                        New                            

I   CASE_INC:   prim_reg_cdc_arb.sv:197    Case statement tag not specified for value 'b10 and 1 other value                      New                            

I   CASE_INC:   tlul_err.sv:62             Case statement tag not specified for value 'h3                                         New                            

I   ONE_BIT_VEC:   adc_ctrl.sv:12                  Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'AlertAsyncOn' has a length of one, instance 'adc_ctrl' of module 'adc_ctrl' (NumAlerts=1)                                                                                                                                       New                            

I   ONE_BIT_VEC:   adc_ctrl.sv:24                  Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_rx_i' has a length of one, instance 'adc_ctrl' of module 'adc_ctrl' (NumAlerts=1)                                                                                                                                         New                            

I   ONE_BIT_VEC:   adc_ctrl.sv:25                  Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_tx_o' has a length of one, instance 'adc_ctrl' of module 'adc_ctrl' (NumAlerts=1)                                                                                                                                         New                            

I   ONE_BIT_VEC:   adc_ctrl.sv:48                  Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_test' has a length of one, instance 'adc_ctrl' of module 'adc_ctrl' (NumAlerts=1)                                                                                                                                         New                            

I   ONE_BIT_VEC:   adc_ctrl_reg_top.sv:147         Declaration range '[0:0]' of 'adc_fsm_rst_qs' has a length of one                                                                                                                                                                                                                 New                            

I   ONE_BIT_VEC:   adc_ctrl_reg_top.sv:386         Declaration range '[0:0]' of 'aon_adc_fsm_rst_qs' has a length of one                                                                                                                                                                                                             New                            

I   ONE_BIT_VEC:   adc_ctrl_reg_top.sv:387         Declaration range '[0:0]' of 'aon_adc_fsm_rst_wdata' has a length of one                                                                                                                                                                                                          New                            

I   ONE_BIT_VEC:   adc_ctrl_reg_top.sv:1412        Declaration range '[0:0]' of 'intr_test_flds_we' has a length of one                                                                                                                                                                                                              New                            

I   ONE_BIT_VEC:   adc_ctrl_reg_top.sv:1432        Declaration range '[0:0]' of 'alert_test_flds_we' has a length of one                                                                                                                                                                                                             New                            

I   ONE_BIT_VEC:   adc_ctrl_reg_top.sv:3956        Declaration range '[0:0]' of 'adc_fsm_state_flds_we' has a length of one                                                                                                                                                                                                          New                            

I   ONE_BIT_VEC:   prim_buf.sv:24                  Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'adc_ctrl.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf' of module 'prim_buf' (Width=1)                                                                             New                            

I   ONE_BIT_VEC:   prim_buf.sv:25                  Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'adc_ctrl.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf' of module 'prim_buf' (Width=1)                                                                            New                            

I   ONE_BIT_VEC:   prim_flop.sv:22                 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'adc_ctrl.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1' of module 'prim_flop' (Width=1)                                                    New                            

I   ONE_BIT_VEC:   prim_flop.sv:27                 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'adc_ctrl.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1' of module 'prim_flop' (Width=1)                                                           New                            

I   ONE_BIT_VEC:   prim_flop.sv:28                 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'adc_ctrl.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1' of module 'prim_flop' (Width=1)                                                           New                            

I   ONE_BIT_VEC:   prim_flop_2sync.sv:19           Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'adc_ctrl.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync' of module 'prim_flop_2sync' (Width=1)                                                                                  New                            

I   ONE_BIT_VEC:   prim_flop_2sync.sv:25           Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'adc_ctrl.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync' of module 'prim_flop_2sync' (Width=1)                                                                                         New                            

I   ONE_BIT_VEC:   prim_flop_2sync.sv:26           Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'adc_ctrl.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync' of module 'prim_flop_2sync' (Width=1)                                                                                         New                            

I   ONE_BIT_VEC:   prim_intr_hw.sv:44              Declaration range '[Width - 1:0]' ([0:0]) of 'event_intr_i' has a length of one, instance 'adc_ctrl.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o' of module 'prim_intr_hw' (Width=1)                                                                                         New                            

I   ONE_BIT_VEC:   prim_intr_hw.sv:47              Declaration range '[Width - 1:0]' ([0:0]) of 'reg2hw_intr_enable_q_i' has a length of one, instance 'adc_ctrl.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o' of module 'prim_intr_hw' (Width=1)                                                                               New                            

I   ONE_BIT_VEC:   prim_intr_hw.sv:48              Declaration range '[Width - 1:0]' ([0:0]) of 'reg2hw_intr_test_q_i' has a length of one, instance 'adc_ctrl.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o' of module 'prim_intr_hw' (Width=1)                                                                                 New                            

I   ONE_BIT_VEC:   prim_intr_hw.sv:50              Declaration range '[Width - 1:0]' ([0:0]) of 'reg2hw_intr_state_q_i' has a length of one, instance 'adc_ctrl.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o' of module 'prim_intr_hw' (Width=1)                                                                                New                            

I   ONE_BIT_VEC:   prim_intr_hw.sv:52              Declaration range '[Width - 1:0]' ([0:0]) of 'hw2reg_intr_state_d_o' has a length of one, instance 'adc_ctrl.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o' of module 'prim_intr_hw' (Width=1)                                                                                New                            

I   ONE_BIT_VEC:   prim_intr_hw.sv:55              Declaration range '[Width - 1:0]' ([0:0]) of 'intr_o' has a length of one, instance 'adc_ctrl.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o' of module 'prim_intr_hw' (Width=1)                                                                                               New                            

I   ONE_BIT_VEC:   prim_intr_hw.sv:58              Declaration range '[Width - 1:0]' ([0:0]) of 'status' has a length of one, instance 'adc_ctrl.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o' of module 'prim_intr_hw' (Width=1)                                                                                               New                            

I   ONE_BIT_VEC:   prim_intr_hw.sv:72              Declaration range '[Width - 1:0]' ([0:0]) of 'g_intr_status.test_q' has a length of one, instance 'adc_ctrl.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o' of module 'prim_intr_hw' (Width=1)                                                                                 New                            

I   ONE_BIT_VEC:   prim_generic_buf.sv:10          Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'adc_ctrl.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1)                                          New                            

I   ONE_BIT_VEC:   prim_generic_buf.sv:11          Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'adc_ctrl.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1)                                         New                            

I   ONE_BIT_VEC:   prim_generic_buf.sv:14          Declaration range '[Width - 1:0]' ([0:0]) of 'inv' has a length of one, instance 'adc_ctrl.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1)                                           New                            

I   ONE_BIT_VEC:   prim_generic_flop.sv:9          Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'adc_ctrl.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1)                 New                            

I   ONE_BIT_VEC:   prim_generic_flop.sv:13         Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'adc_ctrl.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1)                        New                            

I   ONE_BIT_VEC:   prim_generic_flop.sv:14         Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'adc_ctrl.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1)                        New                            

I   ONE_BIT_VEC:   prim_generic_flop_2sync.sv:9    Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'adc_ctrl.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1)                                               New                            

I   ONE_BIT_VEC:   prim_generic_flop_2sync.sv:14   Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'adc_ctrl.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1)                                                      New                            

I   ONE_BIT_VEC:   prim_generic_flop_2sync.sv:15   Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'adc_ctrl.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1)                                                      New                            

I   ONE_BIT_VEC:   prim_generic_flop_2sync.sv:18   Declaration range '[Width - 1:0]' ([0:0]) of 'd_o' has a length of one, instance 'adc_ctrl.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1)                                                      New                            

I   ONE_BIT_VEC:   prim_generic_flop_2sync.sv:19   Declaration range '[Width - 1:0]' ([0:0]) of 'intq' has a length of one, instance 'adc_ctrl.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1)                                                     New                            

I   ONE_BIT_VEC:   prim_sec_anchor_buf.sv:10       Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'adc_ctrl.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req' of module 'prim_sec_anchor_buf' (Width=1)                                                                                      New                            

I   ONE_BIT_VEC:   prim_sec_anchor_buf.sv:11       Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'adc_ctrl.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req' of module 'prim_sec_anchor_buf' (Width=1)                                                                                     New                            

I   ONE_BIT_VEC:   prim_reg_cdc.sv:30              Declaration range '[DataWidth - 1:0]' ([0:0]) of 'ResetVal' has a length of one, instance 'adc_ctrl.u_reg.u_adc_fsm_rst_cdc' of module 'prim_reg_cdc' (DataWidth=1)                                                                                                               New                            

I   ONE_BIT_VEC:   prim_reg_cdc.sv:31              Declaration range '[DataWidth - 1:0]' ([0:0]) of 'BitMask' has a length of one, instance 'adc_ctrl.u_reg.u_adc_fsm_rst_cdc' of module 'prim_reg_cdc' (DataWidth=1)                                                                                                                New                            

I   ONE_BIT_VEC:   prim_reg_cdc.sv:42              Declaration range '[DataWidth - 1:0]' ([0:0]) of 'src_wd_i' has a length of one, instance 'adc_ctrl.u_reg.u_adc_fsm_rst_cdc' of module 'prim_reg_cdc' (DataWidth=1)                                                                                                               New                            

I   ONE_BIT_VEC:   prim_reg_cdc.sv:44              Declaration range '[DataWidth - 1:0]' ([0:0]) of 'src_qs_o' has a length of one, instance 'adc_ctrl.u_reg.u_adc_fsm_rst_cdc' of module 'prim_reg_cdc' (DataWidth=1)                                                                                                               New                            

I   ONE_BIT_VEC:   prim_reg_cdc.sv:45              Declaration range '[DataWidth - 1:0]' ([0:0]) of 'dst_ds_i' has a length of one, instance 'adc_ctrl.u_reg.u_adc_fsm_rst_cdc' of module 'prim_reg_cdc' (DataWidth=1)                                                                                                               New                            

I   ONE_BIT_VEC:   prim_reg_cdc.sv:46              Declaration range '[DataWidth - 1:0]' ([0:0]) of 'dst_qs_i' has a length of one, instance 'adc_ctrl.u_reg.u_adc_fsm_rst_cdc' of module 'prim_reg_cdc' (DataWidth=1)                                                                                                               New                            

I   ONE_BIT_VEC:   prim_reg_cdc.sv:51              Declaration range '[DataWidth - 1:0]' ([0:0]) of 'dst_wd_o' has a length of one, instance 'adc_ctrl.u_reg.u_adc_fsm_rst_cdc' of module 'prim_reg_cdc' (DataWidth=1)                                                                                                               New                            

I   ONE_BIT_VEC:   prim_reg_cdc.sv:61              Declaration range '[DataWidth - 1:0]' ([0:0]) of 'src_q' has a length of one, instance 'adc_ctrl.u_reg.u_adc_fsm_rst_cdc' of module 'prim_reg_cdc' (DataWidth=1)                                                                                                                  New                            

I   ONE_BIT_VEC:   prim_reg_cdc.sv:112             Declaration range '[DataWidth - 1:0]' ([0:0]) of 'dst_qs' has a length of one, instance 'adc_ctrl.u_reg.u_adc_fsm_rst_cdc' of module 'prim_reg_cdc' (DataWidth=1)                                                                                                                 New                            

I   ONE_BIT_VEC:   prim_reg_cdc_arb.sv:54          Declaration range '[DataWidth - 1:0]' ([0:0]) of 'ResetVal' has a length of one, instance 'adc_ctrl.u_reg.u_adc_fsm_rst_cdc.u_arb' of module 'prim_reg_cdc_arb' (DataWidth=1)                                                                                                     New                            

I   ONE_BIT_VEC:   prim_reg_cdc_arb.sv:80          Declaration range '[DataWidth - 1:0]' ([0:0]) of 'dst_ds_i' has a length of one, instance 'adc_ctrl.u_reg.u_adc_fsm_rst_cdc.u_arb' of module 'prim_reg_cdc_arb' (DataWidth=1)                                                                                                     New                            

I   ONE_BIT_VEC:   prim_reg_cdc_arb.sv:81          Declaration range '[DataWidth - 1:0]' ([0:0]) of 'dst_qs_i' has a length of one, instance 'adc_ctrl.u_reg.u_adc_fsm_rst_cdc.u_arb' of module 'prim_reg_cdc_arb' (DataWidth=1)                                                                                                     New                            

I   ONE_BIT_VEC:   prim_reg_cdc_arb.sv:82          Declaration range '[DataWidth - 1:0]' ([0:0]) of 'dst_qs_o' has a length of one, instance 'adc_ctrl.u_reg.u_adc_fsm_rst_cdc.u_arb' of module 'prim_reg_cdc_arb' (DataWidth=1)                                                                                                     New                            

I   ONE_BIT_VEC:   prim_subreg.sv:12               Declaration range '[DW - 1:0]' ([0:0]) of 'RESVAL' has a length of one, instance 'adc_ctrl.u_reg.u_intr_state' of module 'prim_subreg' (DW=1)                                                                                                                                     New                            

I   ONE_BIT_VEC:   prim_subreg.sv:21               Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'adc_ctrl.u_reg.u_intr_state' of module 'prim_subreg' (DW=1)                                                                                                                                         New                            

I   ONE_BIT_VEC:   prim_subreg.sv:25               Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'adc_ctrl.u_reg.u_intr_state' of module 'prim_subreg' (DW=1)                                                                                                                                          New                            

I   ONE_BIT_VEC:   prim_subreg.sv:29               Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'adc_ctrl.u_reg.u_intr_state' of module 'prim_subreg' (DW=1)                                                                                                                                          New                            

I   ONE_BIT_VEC:   prim_subreg.sv:34               Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'adc_ctrl.u_reg.u_intr_state' of module 'prim_subreg' (DW=1)                                                                                                                                         New                            

I   ONE_BIT_VEC:   prim_subreg.sv:35               Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'adc_ctrl.u_reg.u_intr_state' of module 'prim_subreg' (DW=1)                                                                                                                                         New                            

I   ONE_BIT_VEC:   prim_subreg.sv:39               Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'adc_ctrl.u_reg.u_intr_state' of module 'prim_subreg' (DW=1)                                                                                                                                    New                            

I   ONE_BIT_VEC:   prim_subreg_arb.sv:17           Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'adc_ctrl.u_reg.u_intr_state.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1)                                                                                                                      New                            

I   ONE_BIT_VEC:   prim_subreg_arb.sv:21           Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'adc_ctrl.u_reg.u_intr_state.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1)                                                                                                                       New                            

I   ONE_BIT_VEC:   prim_subreg_arb.sv:24           Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'adc_ctrl.u_reg.u_intr_state.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1)                                                                                                                       New                            

I   ONE_BIT_VEC:   prim_subreg_arb.sv:28           Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'adc_ctrl.u_reg.u_intr_state.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1)                                                                                                                 New                            

I   ONE_BIT_VEC:   prim_subreg_arb.sv:36           Declaration range '[DW - 1:0]' ([0:0]) of 'gen_w.unused_q' has a length of one, instance 'adc_ctrl.u_reg.u_intr_enable.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1)                                                                                                         New                            

I   ONE_BIT_VEC:   prim_subreg_arb.sv:47           Declaration range '[DW - 1:0]' ([0:0]) of 'gen_ro.unused_wd' has a length of one, instance 'adc_ctrl.u_reg.u_intr_state.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1)                                                                                                        New                            

I   ONE_BIT_VEC:   prim_subreg_arb.sv:48           Declaration range '[DW - 1:0]' ([0:0]) of 'gen_ro.unused_q' has a length of one, instance 'adc_ctrl.u_reg.u_intr_state.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1)                                                                                                         New                            

I   ONE_BIT_VEC:   prim_subreg_ext.sv:12           Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'adc_ctrl.u_reg.u_intr_test' of module 'prim_subreg_ext' (DW=1)                                                                                                                                      New                            

I   ONE_BIT_VEC:   prim_subreg_ext.sv:14           Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'adc_ctrl.u_reg.u_intr_test' of module 'prim_subreg_ext' (DW=1)                                                                                                                                       New                            

I   ONE_BIT_VEC:   prim_subreg_ext.sv:19           Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'adc_ctrl.u_reg.u_intr_test' of module 'prim_subreg_ext' (DW=1)                                                                                                                                       New                            

I   ONE_BIT_VEC:   prim_subreg_ext.sv:20           Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'adc_ctrl.u_reg.u_intr_test' of module 'prim_subreg_ext' (DW=1)                                                                                                                                      New                            

I   ONE_BIT_VEC:   prim_subreg_ext.sv:21           Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'adc_ctrl.u_reg.u_intr_test' of module 'prim_subreg_ext' (DW=1)                                                                                                                                      New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'd_sink' has a length of one                                                                                                                                                                                               New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl' has a length of one                                                                                                                                                                                                   New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d2h_t' has a length of one                                                                                                                                                                                             New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_i' has a length of one                                                                                                                                                                                                 New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o' has a length of one                                                                                                                                                                                                 New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o_pre' has a length of one                                                                                                                                                                                             New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_reg_d2h' has a length of one                                                                                                                                                                                           New                            

I   EXPLICIT_BITLEN:   prim_util_pkg.sv:85   Bit length not specified for constant '1'                   New                            

I   EXPLICIT_BITLEN:   tlul_err.sv:69        Bit length not specified for constant "'h1"                 New                            

I   EXPLICIT_BITLEN:   tlul_err.sv:77        Bit length not specified for constant "'h2"                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:22    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:26    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:30    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:35    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:41    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:44    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:50    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:53    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:56    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:61    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:65    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:69    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:74    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:77    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:80    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:83    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:89    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:92    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:95    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:98    Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:104   Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:107   Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:113   Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:116   Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:122   Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:125   Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:128   Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:134   Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:137   Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:140   Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:145   Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:151   Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:155   Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:159   Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:163   Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:170   Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:174   Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:181   Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:185   Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:189   Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   adc_ctrl_reg_pkg.sv:195   Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:80       Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:80       Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:85       Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:106      Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:106      Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:111      Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:124      Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:124      Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:131      Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:131      Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:212      Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:212      Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:217      Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:238      Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:238      Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:243      Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:256      Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:256      Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:263      Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:263      Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:344      Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:344      Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:349      Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:370      Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:370      Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:375      Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:388      Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:388      Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:395      Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:395      Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:476      Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:476      Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:481      Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:502      Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:502      Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:507      Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:520      Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:520      Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:527      Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:527      Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subreg.sv:25         Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subreg.sv:29         Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subreg_arb.sv:21     Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subreg_arb.sv:24     Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subreg_ext.sv:14     Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subreg_ext.sv:19     Name 'q' is shorter than minimum length 2                 New                            

I   CONST_OUTPUT:   adc_ctrl_core.sv:92       Output 'adc_chn_val_o[0].adc_chn_value_ext.de' is driven by constant zero                                                            New                            

I   CONST_OUTPUT:   adc_ctrl_core.sv:93       Output 'adc_chn_val_o[0].adc_chn_value_ext.d' is driven by constant zeros                                                            New                            

I   CONST_OUTPUT:   adc_ctrl_core.sv:94       Output 'adc_chn_val_o[1].adc_chn_value_ext.de' is driven by constant zero                                                            New                            

I   CONST_OUTPUT:   adc_ctrl_core.sv:95       Output 'adc_chn_val_o[1].adc_chn_value_ext.d' is driven by constant zeros                                                            New                            

I   CONST_OUTPUT:   adc_ctrl_core.sv:97       Output 'adc_chn_val_o[0].adc_chn_value_intr_ext.de' is driven by constant zero                                                       New                            

I   CONST_OUTPUT:   adc_ctrl_core.sv:98       Output 'adc_chn_val_o[0].adc_chn_value_intr_ext.d' is driven by constant zeros                                                       New                            

I   CONST_OUTPUT:   adc_ctrl_core.sv:99       Output 'adc_chn_val_o[1].adc_chn_value_intr_ext.de' is driven by constant zero                                                       New                            

I   CONST_OUTPUT:   adc_ctrl_core.sv:100      Output 'adc_chn_val_o[1].adc_chn_value_intr_ext.d' is driven by constant zeros                                                       New                            

I   CONST_OUTPUT:   adc_ctrl_core.sv:191      Output 'adc_intr_status_o.oneshot.d' is driven by constant one by port 'u_adc_ctrl_intr.adc_intr_status_o.oneshot.d'                 New                            

I   CONST_OUTPUT:   adc_ctrl_core.sv:191      Output 'adc_intr_status_o.trans.d' is driven by constant one by port 'u_adc_ctrl_intr.adc_intr_status_o.trans.d'                     New                            

I   CONST_OUTPUT:   adc_ctrl_core.sv:191      Output 'intr_state_o.de' is driven by constant one by port 'u_adc_ctrl_intr.intr_state_o.de'                                         New                            

I   CONST_OUTPUT:   adc_ctrl_intr.sv:107      Output 'adc_intr_status_o.trans.d' is driven by constant one                                                                         New                            

I   CONST_OUTPUT:   adc_ctrl_intr.sv:116      Output 'adc_intr_status_o.oneshot.d' is driven by constant one                                                                       New                            

I   CONST_OUTPUT:   adc_ctrl_intr.sv:124      Output 'intr_state_o.de' is driven by constant one by port 'i_adc_ctrl_intr_o.hw2reg_intr_state_de_o'                                New                            

I   CONST_OUTPUT:   prim_intr_hw.sv:80        Output 'hw2reg_intr_state_de_o' is driven by constant one in module 'prim_intr_hw' (IntrT="Status")                                  New                            

I   CONST_OUTPUT:   prim_reg_cdc_arb.sv:287   Output 'src_update_o' is driven by constant zero                                                                                     New                            

I   CONST_OUTPUT:   prim_reg_cdc_arb.sv:287   Output 'src_update_o' is driven by constant zero in module 'prim_reg_cdc_arb' (DataWidth=2)                                          New                            

I   CONST_OUTPUT:   tlul_adapter_reg.sv:91    Output 'addr_o[1:0]' is driven by constant zeros in module 'tlul_adapter_reg' (RegAw=7)                                              New                            

I   CONST_OUTPUT:   tlul_adapter_reg.sv:195   Output 'intg_error_o' is driven by constant zero in module 'tlul_adapter_reg' (RegAw=7)                                              New                            

Lint Warnings

W   STAR_PORT_CONN_USE:   prim_flop_2sync.sv:35   '.*' wild card port connection encountered on instance 'gen_generic.u_impl_generic'                 New                                                                  

Lint Errors

E   IFDEF_CODE:   prim_generic_flop_2sync.sv:35   Assignment to 'unused_sig' contained within `else block at prim_generic_flop_2sync.sv:33   prim_generic_flop_2sync.sv:33   New                            

Past Results