AES/MASKED Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: `83db9403d`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	70.074us	1	1	100.00
V1	smoke	aes_smoke	31.000s	946.979us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	7.000s	79.620us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	192.002us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.327ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	579.549us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	77.283us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	192.002us	20	20	100.00
		aes_csr_aliasing	6.000s	579.549us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	31.000s	946.979us	50	50	100.00
		aes_config_error	31.000s	1.089ms	50	50	100.00
		aes_stress	3.800m	3.274ms	50	50	100.00
V2	key_length	aes_smoke	31.000s	946.979us	50	50	100.00
		aes_config_error	31.000s	1.089ms	50	50	100.00
		aes_stress	3.800m	3.274ms	50	50	100.00
V2	back2back	aes_stress	3.800m	3.274ms	50	50	100.00
		aes_b2b	34.000s	416.246us	50	50	100.00
V2	backpressure	aes_stress	3.800m	3.274ms	50	50	100.00
V2	multi_message	aes_smoke	31.000s	946.979us	50	50	100.00
		aes_config_error	31.000s	1.089ms	50	50	100.00
		aes_stress	3.800m	3.274ms	50	50	100.00
		aes_alert_reset	1.150m	2.813ms	50	50	100.00
V2	failure_test	aes_config_error	31.000s	1.089ms	50	50	100.00
		aes_alert_reset	1.150m	2.813ms	50	50	100.00
		aes_man_cfg_err	13.000s	434.978us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.400m	2.639ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	532.418us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.150m	2.813ms	50	50	100.00
V2	stress	aes_stress	3.800m	3.274ms	50	50	100.00
V2	sideload	aes_stress	3.800m	3.274ms	50	50	100.00
		aes_sideload	9.000s	517.342us	50	50	100.00
V2	deinitialization	aes_deinit	7.000s	122.491us	50	50	100.00
V2	alert_test	aes_alert_test	4.000s	53.444us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	827.089us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	827.089us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	7.000s	79.620us	5	5	100.00
		aes_csr_rw	4.000s	192.002us	20	20	100.00
		aes_csr_aliasing	6.000s	579.549us	5	5	100.00
		aes_same_csr_outstanding	5.000s	133.083us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	7.000s	79.620us	5	5	100.00
		aes_csr_rw	4.000s	192.002us	20	20	100.00
		aes_csr_aliasing	6.000s	579.549us	5	5	100.00
		aes_same_csr_outstanding	5.000s	133.083us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	2.867m	1.918ms	50	50	100.00
V2S	fault_inject	aes_fi	28.000s	4.741ms	50	50	100.00
		aes_control_fi	37.000s	10.006ms	288	300	96.00
		aes_cipher_fi	51.000s	10.005ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	139.184us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	139.184us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	139.184us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	139.184us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	278.758us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	281.018us	5	5	100.00
		aes_tl_intg_err	5.000s	291.058us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	291.058us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.150m	2.813ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	139.184us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	31.000s	946.979us	50	50	100.00
		aes_stress	3.800m	3.274ms	50	50	100.00
		aes_alert_reset	1.150m	2.813ms	50	50	100.00
		aes_core_fi	1.417m	10.004ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	139.184us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	3.800m	3.274ms	50	50	100.00
		aes_readability	8.000s	335.971us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	3.800m	3.274ms	50	50	100.00
		aes_sideload	9.000s	517.342us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	335.971us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	335.971us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	335.971us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	335.971us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	335.971us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	3.800m	3.274ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	3.800m	3.274ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	28.000s	4.741ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	28.000s	4.741ms	50	50	100.00
		aes_control_fi	37.000s	10.006ms	288	300	96.00
		aes_cipher_fi	51.000s	10.005ms	341	350	97.43
		aes_ctr_fi	6.000s	236.220us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	28.000s	4.741ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	28.000s	4.741ms	50	50	100.00
		aes_control_fi	37.000s	10.006ms	288	300	96.00
		aes_cipher_fi	51.000s	10.005ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	10.005ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	28.000s	4.741ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	28.000s	4.741ms	50	50	100.00
		aes_control_fi	37.000s	10.006ms	288	300	96.00
		aes_ctr_fi	6.000s	236.220us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	28.000s	4.741ms	50	50	100.00
		aes_control_fi	37.000s	10.006ms	288	300	96.00
		aes_cipher_fi	51.000s	10.005ms	341	350	97.43
		aes_ctr_fi	6.000s	236.220us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.150m	2.813ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	28.000s	4.741ms	50	50	100.00
		aes_control_fi	37.000s	10.006ms	288	300	96.00
		aes_cipher_fi	51.000s	10.005ms	341	350	97.43
		aes_ctr_fi	6.000s	236.220us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	28.000s	4.741ms	50	50	100.00
		aes_control_fi	37.000s	10.006ms	288	300	96.00
		aes_cipher_fi	51.000s	10.005ms	341	350	97.43
		aes_ctr_fi	6.000s	236.220us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	28.000s	4.741ms	50	50	100.00
		aes_control_fi	37.000s	10.006ms	288	300	96.00
		aes_ctr_fi	6.000s	236.220us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	28.000s	4.741ms	50	50	100.00
		aes_control_fi	37.000s	10.006ms	288	300	96.00
		aes_cipher_fi	51.000s	10.005ms	341	350	97.43
V2S		TOTAL			962	985	97.66
V3		TOTAL			0	0	--
		TOTAL			1559	1582	98.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	8	72.73

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.48	99.02	97.58	99.41	95.96	95.60	97.78	98.67	92.29

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test aes_control_fi has 7 failures.
  - 8.aes_control_fi.2148667036
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  Job ID: smart:0ade4fba-50b6-481b-878a-8fffd62ef36c
```
  - 137.aes_control_fi.2370588675
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/137.aes_control_fi/latest/run.log
```
  Job ID: smart:377d8797-456d-44c5-8ce5-3e57f6a2e393
```
  - ... and 5 more failures.
- Test aes_cipher_fi has 4 failures.
  - 57.aes_cipher_fi.923667257
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/57.aes_cipher_fi/latest/run.log
```
  Job ID: smart:7de0eeba-251d-450d-9dbb-a25f5f95c85b
```
  - 107.aes_cipher_fi.849058301
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/107.aes_cipher_fi/latest/run.log
```
  Job ID: smart:09039d83-a4d8-4681-b582-c9dcf63e7215
```
  - ... and 2 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:

Test aes_control_fi has 5 failures.

50.aes_control_fi.2817614305
Line 282, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/50.aes_control_fi/latest/run.log

  UVM_FATAL @ 10006063006 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006063006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

82.aes_control_fi.369212164
Line 277, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/82.aes_control_fi/latest/run.log

  UVM_FATAL @ 10012286241 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012286241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:

Test aes_cipher_fi has 5 failures.

94.aes_cipher_fi.3757246936
Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/94.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10055378450 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10055378450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

167.aes_cipher_fi.1635797332
Line 281, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/167.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10006807881 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006807881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

58.aes_core_fi.203578332
Line 274, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/58.aes_core_fi/latest/run.log

  UVM_FATAL @ 10004331014 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004331014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

59.aes_core_fi.3957066784
Line 273, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/59.aes_core_fi/latest/run.log

  UVM_FATAL @ 10038068417 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10038068417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---