AES/MASKED Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: `94eb0df12`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 77475240

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	60.289us	1	1	100.00
V1	smoke	aes_smoke	16.000s	878.427us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	89.949us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	68.504us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	988.920us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	134.680us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	137.097us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	68.504us	20	20	100.00
		aes_csr_aliasing	5.000s	134.680us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	16.000s	878.427us	50	50	100.00
		aes_config_error	53.000s	1.555ms	50	50	100.00
		aes_stress	2.717m	2.257ms	50	50	100.00
V2	key_length	aes_smoke	16.000s	878.427us	50	50	100.00
		aes_config_error	53.000s	1.555ms	50	50	100.00
		aes_stress	2.717m	2.257ms	50	50	100.00
V2	back2back	aes_stress	2.717m	2.257ms	50	50	100.00
		aes_b2b	1.000m	843.783us	50	50	100.00
V2	backpressure	aes_stress	2.717m	2.257ms	50	50	100.00
V2	multi_message	aes_smoke	16.000s	878.427us	50	50	100.00
		aes_config_error	53.000s	1.555ms	50	50	100.00
		aes_stress	2.717m	2.257ms	50	50	100.00
		aes_alert_reset	20.000s	745.871us	50	50	100.00
V2	failure_test	aes_config_error	53.000s	1.555ms	50	50	100.00
		aes_alert_reset	20.000s	745.871us	50	50	100.00
		aes_man_cfg_err	12.000s	416.055us	50	50	100.00
V2	trigger_clear_test	aes_clear	13.000s	386.799us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	661.841us	1	1	100.00
V2	reset_recovery	aes_alert_reset	20.000s	745.871us	50	50	100.00
V2	stress	aes_stress	2.717m	2.257ms	50	50	100.00
V2	sideload	aes_stress	2.717m	2.257ms	50	50	100.00
		aes_sideload	12.000s	421.761us	50	50	100.00
V2	deinitialization	aes_deinit	25.000s	3.659ms	50	50	100.00
V2	alert_test	aes_alert_test	4.000s	52.401us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	226.583us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	226.583us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	89.949us	5	5	100.00
		aes_csr_rw	4.000s	68.504us	20	20	100.00
		aes_csr_aliasing	5.000s	134.680us	5	5	100.00
		aes_same_csr_outstanding	5.000s	98.738us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	89.949us	5	5	100.00
		aes_csr_rw	4.000s	68.504us	20	20	100.00
		aes_csr_aliasing	5.000s	134.680us	5	5	100.00
		aes_same_csr_outstanding	5.000s	98.738us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	3.217m	2.009ms	50	50	100.00
V2S	fault_inject	aes_fi	17.000s	3.086ms	50	50	100.00
		aes_control_fi	48.000s	10.009ms	286	300	95.33
		aes_cipher_fi	49.000s	10.015ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	89.846us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	89.846us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	89.846us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	89.846us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	1.118ms	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.428ms	5	5	100.00
		aes_tl_intg_err	6.000s	517.678us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	517.678us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	20.000s	745.871us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	89.846us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	16.000s	878.427us	50	50	100.00
		aes_stress	2.717m	2.257ms	50	50	100.00
		aes_alert_reset	20.000s	745.871us	50	50	100.00
		aes_core_fi	50.000s	10.005ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	89.846us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	2.717m	2.257ms	50	50	100.00
		aes_readability	5.000s	67.443us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	2.717m	2.257ms	50	50	100.00
		aes_sideload	12.000s	421.761us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	67.443us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	67.443us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	67.443us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	67.443us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	67.443us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.717m	2.257ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	2.717m	2.257ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	17.000s	3.086ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	17.000s	3.086ms	50	50	100.00
		aes_control_fi	48.000s	10.009ms	286	300	95.33
		aes_cipher_fi	49.000s	10.015ms	337	350	96.29
		aes_ctr_fi	18.000s	643.196us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	17.000s	3.086ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	17.000s	3.086ms	50	50	100.00
		aes_control_fi	48.000s	10.009ms	286	300	95.33
		aes_cipher_fi	49.000s	10.015ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.015ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	17.000s	3.086ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	17.000s	3.086ms	50	50	100.00
		aes_control_fi	48.000s	10.009ms	286	300	95.33
		aes_ctr_fi	18.000s	643.196us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	17.000s	3.086ms	50	50	100.00
		aes_control_fi	48.000s	10.009ms	286	300	95.33
		aes_cipher_fi	49.000s	10.015ms	337	350	96.29
		aes_ctr_fi	18.000s	643.196us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	20.000s	745.871us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	17.000s	3.086ms	50	50	100.00
		aes_control_fi	48.000s	10.009ms	286	300	95.33
		aes_cipher_fi	49.000s	10.015ms	337	350	96.29
		aes_ctr_fi	18.000s	643.196us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	17.000s	3.086ms	50	50	100.00
		aes_control_fi	48.000s	10.009ms	286	300	95.33
		aes_cipher_fi	49.000s	10.015ms	337	350	96.29
		aes_ctr_fi	18.000s	643.196us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	17.000s	3.086ms	50	50	100.00
		aes_control_fi	48.000s	10.009ms	286	300	95.33
		aes_ctr_fi	18.000s	643.196us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	17.000s	3.086ms	50	50	100.00
		aes_control_fi	48.000s	10.009ms	286	300	95.33
		aes_cipher_fi	49.000s	10.015ms	337	350	96.29
V2S		TOTAL			956	985	97.06
V3		TOTAL			0	0	--
		TOTAL			1553	1582	98.17

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	8	72.73

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.47	99.01	97.60	99.36	95.98	95.66	98.52	98.67	92.70

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
- Test aes_cipher_fi has 6 failures.
  - 3.aes_cipher_fi.3024951474
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  Job ID: smart:3d0960e5-da9e-4a23-9370-14827fae81db
```
  - 7.aes_cipher_fi.2688825698
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_cipher_fi/latest/run.log
```
  Job ID: smart:39d4756f-6576-4ccc-a7df-ab4388aa571e
```
  - ... and 4 more failures.
- Test aes_control_fi has 10 failures.
  - 7.aes_control_fi.2705690879
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job ID: smart:c136bd65-98f8-4f5d-95eb-0a7ff26859ad
```
  - 29.aes_control_fi.61954924
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  Job ID: smart:614d66e0-8e67-4982-a3bf-03c37e55d097
```
  - ... and 8 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:

Test aes_cipher_fi has 7 failures.

18.aes_cipher_fi.149892436
Line 276, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10008885230 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008885230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.aes_cipher_fi.3827748547
Line 275, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/23.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10014940625 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014940625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:

Test aes_control_fi has 4 failures.

54.aes_control_fi.3828588871
Line 283, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/54.aes_control_fi/latest/run.log

  UVM_FATAL @ 10014800927 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014800927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

55.aes_control_fi.2151139400
Line 271, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/55.aes_control_fi/latest/run.log

  UVM_FATAL @ 10009368514 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009368514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

57.aes_core_fi.3932385688
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/57.aes_core_fi/latest/run.log

  UVM_FATAL @ 10200601632 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10200601632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

62.aes_core_fi.785080294
Line 282, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/62.aes_core_fi/latest/run.log

  UVM_FATAL @ 10004873054 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004873054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---