AES/MASKED Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: `213e792ea`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	428.156us	1	1	100.00
V1	smoke	aes_smoke	11.000s	428.078us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	84.360us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	65.738us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.958ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	1.107ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	238.981us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	65.738us	20	20	100.00
		aes_csr_aliasing	5.000s	1.107ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	11.000s	428.078us	50	50	100.00
		aes_config_error	20.000s	692.790us	50	50	100.00
		aes_stress	3.467m	2.893ms	50	50	100.00
V2	key_length	aes_smoke	11.000s	428.078us	50	50	100.00
		aes_config_error	20.000s	692.790us	50	50	100.00
		aes_stress	3.467m	2.893ms	50	50	100.00
V2	back2back	aes_stress	3.467m	2.893ms	50	50	100.00
		aes_b2b	38.000s	439.127us	50	50	100.00
V2	backpressure	aes_stress	3.467m	2.893ms	50	50	100.00
V2	multi_message	aes_smoke	11.000s	428.078us	50	50	100.00
		aes_config_error	20.000s	692.790us	50	50	100.00
		aes_stress	3.467m	2.893ms	50	50	100.00
		aes_alert_reset	16.000s	717.431us	50	50	100.00
V2	failure_test	aes_config_error	20.000s	692.790us	50	50	100.00
		aes_alert_reset	16.000s	717.431us	50	50	100.00
		aes_man_cfg_err	5.000s	103.557us	50	50	100.00
V2	trigger_clear_test	aes_clear	39.000s	2.303ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	369.860us	1	1	100.00
V2	reset_recovery	aes_alert_reset	16.000s	717.431us	50	50	100.00
V2	stress	aes_stress	3.467m	2.893ms	50	50	100.00
V2	sideload	aes_stress	3.467m	2.893ms	50	50	100.00
		aes_sideload	1.683m	3.718ms	50	50	100.00
V2	deinitialization	aes_deinit	11.000s	304.974us	50	50	100.00
V2	alert_test	aes_alert_test	4.000s	53.063us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	589.421us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	589.421us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	84.360us	5	5	100.00
		aes_csr_rw	4.000s	65.738us	20	20	100.00
		aes_csr_aliasing	5.000s	1.107ms	5	5	100.00
		aes_same_csr_outstanding	5.000s	100.015us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	84.360us	5	5	100.00
		aes_csr_rw	4.000s	65.738us	20	20	100.00
		aes_csr_aliasing	5.000s	1.107ms	5	5	100.00
		aes_same_csr_outstanding	5.000s	100.015us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	2.633m	1.922ms	49	50	98.00
V2S	fault_inject	aes_fi	27.000s	1.008ms	50	50	100.00
		aes_control_fi	50.000s	10.004ms	287	300	95.67
		aes_cipher_fi	49.000s	10.004ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	77.029us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	77.029us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	77.029us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	77.029us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	186.937us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	494.025us	5	5	100.00
		aes_tl_intg_err	5.000s	352.612us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	352.612us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	16.000s	717.431us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	77.029us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	428.078us	50	50	100.00
		aes_stress	3.467m	2.893ms	50	50	100.00
		aes_alert_reset	16.000s	717.431us	50	50	100.00
		aes_core_fi	1.833m	10.036ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	77.029us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	3.467m	2.893ms	50	50	100.00
		aes_readability	6.000s	219.023us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	3.467m	2.893ms	50	50	100.00
		aes_sideload	1.683m	3.718ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	219.023us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	219.023us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	219.023us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	219.023us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	219.023us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	3.467m	2.893ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	3.467m	2.893ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	27.000s	1.008ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	27.000s	1.008ms	50	50	100.00
		aes_control_fi	50.000s	10.004ms	287	300	95.67
		aes_cipher_fi	49.000s	10.004ms	337	350	96.29
		aes_ctr_fi	5.000s	196.430us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	27.000s	1.008ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	27.000s	1.008ms	50	50	100.00
		aes_control_fi	50.000s	10.004ms	287	300	95.67
		aes_cipher_fi	49.000s	10.004ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.004ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	27.000s	1.008ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	27.000s	1.008ms	50	50	100.00
		aes_control_fi	50.000s	10.004ms	287	300	95.67
		aes_ctr_fi	5.000s	196.430us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	27.000s	1.008ms	50	50	100.00
		aes_control_fi	50.000s	10.004ms	287	300	95.67
		aes_cipher_fi	49.000s	10.004ms	337	350	96.29
		aes_ctr_fi	5.000s	196.430us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	16.000s	717.431us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	27.000s	1.008ms	50	50	100.00
		aes_control_fi	50.000s	10.004ms	287	300	95.67
		aes_cipher_fi	49.000s	10.004ms	337	350	96.29
		aes_ctr_fi	5.000s	196.430us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	27.000s	1.008ms	50	50	100.00
		aes_control_fi	50.000s	10.004ms	287	300	95.67
		aes_cipher_fi	49.000s	10.004ms	337	350	96.29
		aes_ctr_fi	5.000s	196.430us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	27.000s	1.008ms	50	50	100.00
		aes_control_fi	50.000s	10.004ms	287	300	95.67
		aes_ctr_fi	5.000s	196.430us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	27.000s	1.008ms	50	50	100.00
		aes_control_fi	50.000s	10.004ms	287	300	95.67
		aes_cipher_fi	49.000s	10.004ms	337	350	96.29
V2S		TOTAL			954	985	96.85
V3		TOTAL			0	0	--
		TOTAL			1551	1582	98.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	7	63.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.45	99.01	97.53	99.41	95.81	95.60	97.78	98.67	92.09

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
- Test aes_control_fi has 11 failures.
  - 3.aes_control_fi.4077629581
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job ID: smart:a0ac8451-566b-4627-8dd4-e58fded28d44
```
  - 23.aes_control_fi.225581159
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  Job ID: smart:137e9981-904b-48e0-bc1e-dc05f38654c4
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 7 failures.
  - 49.aes_cipher_fi.4038379280
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/49.aes_cipher_fi/latest/run.log
```
  Job ID: smart:bb964765-f814-412e-a320-22221ae42c76
```
  - 100.aes_cipher_fi.296576677
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/100.aes_cipher_fi/latest/run.log
```
  Job ID: smart:cbd96e63-cea9-41df-b671-a72aacec7e26
```
  - ... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:

Test aes_cipher_fi has 6 failures.

22.aes_cipher_fi.231181544
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/22.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10009157411 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009157411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.aes_cipher_fi.1508884023
Line 282, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/30.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10034304824 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10034304824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:

Test aes_core_fi has 3 failures.

8.aes_core_fi.3639736064
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_core_fi/latest/run.log

  UVM_FATAL @ 10020758834 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020758834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.aes_core_fi.923039340
Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/38.aes_core_fi/latest/run.log

  UVM_FATAL @ 10008761224 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008761224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_control_fi has 2 failures.

39.aes_control_fi.2717376483
Line 277, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/39.aes_control_fi/latest/run.log

  UVM_FATAL @ 10010619523 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010619523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

272.aes_control_fi.354028224
Line 277, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/272.aes_control_fi/latest/run.log

  UVM_FATAL @ 10004139072 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004139072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_scoreboard.sv:621) scoreboard [scoreboard] # * has 1 failures:

Test aes_reseed has 1 failures.

16.aes_reseed.190508289
Line 15780, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_reseed/latest/run.log

  UVM_FATAL @  51325986 ps: (aes_scoreboard.sv:621) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
            TEST FAILED MESSAGES DID NOT MATCH
  
                 0 85      2b      1f      0
                 1 00      0b      69      0

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 60.aes_core_fi.4174819760
    Line 270, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/60.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10035935052 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x5852d884) == 0x0
  UVM_INFO @ 10035935052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```