AES/MASKED Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2359737659

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	85.152us	1	1	100.00
V1	smoke	aes_smoke	8.000s	219.390us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	62.065us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	61.258us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	3.913ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	903.718us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	315.788us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	61.258us	20	20	100.00
		aes_csr_aliasing	6.000s	903.718us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	219.390us	50	50	100.00
		aes_config_error	25.000s	931.498us	50	50	100.00
		aes_stress	2.600m	2.030ms	50	50	100.00
V2	key_length	aes_smoke	8.000s	219.390us	50	50	100.00
		aes_config_error	25.000s	931.498us	50	50	100.00
		aes_stress	2.600m	2.030ms	50	50	100.00
V2	back2back	aes_stress	2.600m	2.030ms	50	50	100.00
		aes_b2b	1.183m	973.417us	50	50	100.00
V2	backpressure	aes_stress	2.600m	2.030ms	50	50	100.00
V2	multi_message	aes_smoke	8.000s	219.390us	50	50	100.00
		aes_config_error	25.000s	931.498us	50	50	100.00
		aes_stress	2.600m	2.030ms	50	50	100.00
		aes_alert_reset	46.000s	1.617ms	50	50	100.00
V2	failure_test	aes_config_error	25.000s	931.498us	50	50	100.00
		aes_alert_reset	46.000s	1.617ms	50	50	100.00
		aes_man_cfg_err	5.000s	76.392us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.650m	3.513ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	574.081us	1	1	100.00
V2	reset_recovery	aes_alert_reset	46.000s	1.617ms	50	50	100.00
V2	stress	aes_stress	2.600m	2.030ms	50	50	100.00
V2	sideload	aes_stress	2.600m	2.030ms	50	50	100.00
		aes_sideload	25.000s	1.998ms	50	50	100.00
V2	deinitialization	aes_deinit	11.000s	279.045us	50	50	100.00
V2	alert_test	aes_alert_test	4.000s	110.194us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	85.906us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	85.906us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	62.065us	5	5	100.00
		aes_csr_rw	4.000s	61.258us	20	20	100.00
		aes_csr_aliasing	6.000s	903.718us	5	5	100.00
		aes_same_csr_outstanding	4.000s	71.215us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	62.065us	5	5	100.00
		aes_csr_rw	4.000s	61.258us	20	20	100.00
		aes_csr_aliasing	6.000s	903.718us	5	5	100.00
		aes_same_csr_outstanding	4.000s	71.215us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	2.533m	1.906ms	50	50	100.00
V2S	fault_inject	aes_fi	17.000s	586.627us	50	50	100.00
		aes_control_fi	50.000s	10.021ms	282	300	94.00
		aes_cipher_fi	45.000s	10.009ms	343	350	98.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	98.355us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	98.355us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	98.355us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	98.355us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	194.549us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	1.340ms	5	5	100.00
		aes_tl_intg_err	5.000s	645.441us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	645.441us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	46.000s	1.617ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	98.355us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	219.390us	50	50	100.00
		aes_stress	2.600m	2.030ms	50	50	100.00
		aes_alert_reset	46.000s	1.617ms	50	50	100.00
		aes_core_fi	1.350m	10.010ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	98.355us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	2.600m	2.030ms	50	50	100.00
		aes_readability	6.000s	64.495us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	2.600m	2.030ms	50	50	100.00
		aes_sideload	25.000s	1.998ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	64.495us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	64.495us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	64.495us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	64.495us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	64.495us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.600m	2.030ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	2.600m	2.030ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	17.000s	586.627us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	17.000s	586.627us	50	50	100.00
		aes_control_fi	50.000s	10.021ms	282	300	94.00
		aes_cipher_fi	45.000s	10.009ms	343	350	98.00
		aes_ctr_fi	6.000s	64.879us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	17.000s	586.627us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	17.000s	586.627us	50	50	100.00
		aes_control_fi	50.000s	10.021ms	282	300	94.00
		aes_cipher_fi	45.000s	10.009ms	343	350	98.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	45.000s	10.009ms	343	350	98.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	17.000s	586.627us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	17.000s	586.627us	50	50	100.00
		aes_control_fi	50.000s	10.021ms	282	300	94.00
		aes_ctr_fi	6.000s	64.879us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	17.000s	586.627us	50	50	100.00
		aes_control_fi	50.000s	10.021ms	282	300	94.00
		aes_cipher_fi	45.000s	10.009ms	343	350	98.00
		aes_ctr_fi	6.000s	64.879us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	46.000s	1.617ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	17.000s	586.627us	50	50	100.00
		aes_control_fi	50.000s	10.021ms	282	300	94.00
		aes_cipher_fi	45.000s	10.009ms	343	350	98.00
		aes_ctr_fi	6.000s	64.879us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	17.000s	586.627us	50	50	100.00
		aes_control_fi	50.000s	10.021ms	282	300	94.00
		aes_cipher_fi	45.000s	10.009ms	343	350	98.00
		aes_ctr_fi	6.000s	64.879us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	17.000s	586.627us	50	50	100.00
		aes_control_fi	50.000s	10.021ms	282	300	94.00
		aes_ctr_fi	6.000s	64.879us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	17.000s	586.627us	50	50	100.00
		aes_control_fi	50.000s	10.021ms	282	300	94.00
		aes_cipher_fi	45.000s	10.009ms	343	350	98.00
V2S		TOTAL			959	985	97.36
V3		TOTAL			0	0	--
		TOTAL			1556	1582	98.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	8	72.73

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.48	99.03	97.60	99.42	95.85	95.66	97.78	98.67	92.09

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 19 failures:
- Test aes_control_fi has 15 failures.
  - 10.aes_control_fi.3120174694
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job ID: smart:2403de3f-745d-40c0-9464-f10f094fc493
```
  - 43.aes_control_fi.1217157622
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  Job ID: smart:4f53e8cc-feaf-4025-8719-c1a6b224dbb4
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 4 failures.
  - 135.aes_cipher_fi.3044191748
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/135.aes_cipher_fi/latest/run.log
```
  Job ID: smart:dcd63a7d-adda-470a-a5b5-506d2dbbc9b7
```
  - 188.aes_cipher_fi.2385212371
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/188.aes_cipher_fi/latest/run.log
```
  Job ID: smart:47b26361-5294-4dfe-a093-ae21b4b20e64
```
  - ... and 2 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:

Test aes_cipher_fi has 3 failures.

15.aes_cipher_fi.1315520099
Line 273, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/15.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10011561111 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011561111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.aes_cipher_fi.1863047317
Line 276, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/37.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10017549472 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017549472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:

Test aes_control_fi has 3 failures.

77.aes_control_fi.711876725
Line 289, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/77.aes_control_fi/latest/run.log

  UVM_FATAL @ 10021363898 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021363898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

79.aes_control_fi.2827282099
Line 282, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/79.aes_control_fi/latest/run.log

  UVM_FATAL @ 10008788488 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008788488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 11.aes_core_fi.1535110274
    Line 280, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010116481 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010116481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```