AES/MASKED Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2869101736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	67.003us	1	1	100.00
V1	smoke	aes_smoke	20.000s	710.551us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	54.222us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	81.038us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.750ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	162.593us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	84.584us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	81.038us	20	20	100.00
		aes_csr_aliasing	4.000s	162.593us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	20.000s	710.551us	50	50	100.00
		aes_config_error	30.000s	1.465ms	50	50	100.00
		aes_stress	2.650m	3.826ms	50	50	100.00
V2	key_length	aes_smoke	20.000s	710.551us	50	50	100.00
		aes_config_error	30.000s	1.465ms	50	50	100.00
		aes_stress	2.650m	3.826ms	50	50	100.00
V2	back2back	aes_stress	2.650m	3.826ms	50	50	100.00
		aes_b2b	52.000s	706.421us	50	50	100.00
V2	backpressure	aes_stress	2.650m	3.826ms	50	50	100.00
V2	multi_message	aes_smoke	20.000s	710.551us	50	50	100.00
		aes_config_error	30.000s	1.465ms	50	50	100.00
		aes_stress	2.650m	3.826ms	50	50	100.00
		aes_alert_reset	1.017m	4.847ms	49	50	98.00
V2	failure_test	aes_config_error	30.000s	1.465ms	50	50	100.00
		aes_alert_reset	1.017m	4.847ms	49	50	98.00
		aes_man_cfg_err	6.000s	120.708us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.517m	3.341ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	2.118ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.017m	4.847ms	49	50	98.00
V2	stress	aes_stress	2.650m	3.826ms	50	50	100.00
V2	sideload	aes_stress	2.650m	3.826ms	50	50	100.00
		aes_sideload	40.000s	3.909ms	50	50	100.00
V2	deinitialization	aes_deinit	18.000s	728.596us	50	50	100.00
V2	alert_test	aes_alert_test	6.000s	55.749us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	94.480us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	94.480us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	54.222us	5	5	100.00
		aes_csr_rw	4.000s	81.038us	20	20	100.00
		aes_csr_aliasing	4.000s	162.593us	5	5	100.00
		aes_same_csr_outstanding	4.000s	232.961us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	54.222us	5	5	100.00
		aes_csr_rw	4.000s	81.038us	20	20	100.00
		aes_csr_aliasing	4.000s	162.593us	5	5	100.00
		aes_same_csr_outstanding	4.000s	232.961us	20	20	100.00
V2		TOTAL			490	491	99.80
V2S	reseeding	aes_reseed	2.700m	2.017ms	50	50	100.00
V2S	fault_inject	aes_fi	48.000s	1.683ms	50	50	100.00
		aes_control_fi	41.000s	10.007ms	285	300	95.00
		aes_cipher_fi	49.000s	10.006ms	339	350	96.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	166.750us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	166.750us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	166.750us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	166.750us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	259.861us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	45.000s	9.145ms	5	5	100.00
		aes_tl_intg_err	6.000s	483.911us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	483.911us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.017m	4.847ms	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	166.750us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	20.000s	710.551us	50	50	100.00
		aes_stress	2.650m	3.826ms	50	50	100.00
		aes_alert_reset	1.017m	4.847ms	49	50	98.00
		aes_core_fi	1.367m	10.078ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	166.750us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	2.650m	3.826ms	50	50	100.00
		aes_readability	5.000s	181.821us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	2.650m	3.826ms	50	50	100.00
		aes_sideload	40.000s	3.909ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	181.821us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	181.821us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	181.821us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	181.821us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	181.821us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.650m	3.826ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	2.650m	3.826ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	48.000s	1.683ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	48.000s	1.683ms	50	50	100.00
		aes_control_fi	41.000s	10.007ms	285	300	95.00
		aes_cipher_fi	49.000s	10.006ms	339	350	96.86
		aes_ctr_fi	5.000s	79.973us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	48.000s	1.683ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	48.000s	1.683ms	50	50	100.00
		aes_control_fi	41.000s	10.007ms	285	300	95.00
		aes_cipher_fi	49.000s	10.006ms	339	350	96.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.006ms	339	350	96.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	48.000s	1.683ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	48.000s	1.683ms	50	50	100.00
		aes_control_fi	41.000s	10.007ms	285	300	95.00
		aes_ctr_fi	5.000s	79.973us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	48.000s	1.683ms	50	50	100.00
		aes_control_fi	41.000s	10.007ms	285	300	95.00
		aes_cipher_fi	49.000s	10.006ms	339	350	96.86
		aes_ctr_fi	5.000s	79.973us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.017m	4.847ms	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	48.000s	1.683ms	50	50	100.00
		aes_control_fi	41.000s	10.007ms	285	300	95.00
		aes_cipher_fi	49.000s	10.006ms	339	350	96.86
		aes_ctr_fi	5.000s	79.973us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	48.000s	1.683ms	50	50	100.00
		aes_control_fi	41.000s	10.007ms	285	300	95.00
		aes_cipher_fi	49.000s	10.006ms	339	350	96.86
		aes_ctr_fi	5.000s	79.973us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	48.000s	1.683ms	50	50	100.00
		aes_control_fi	41.000s	10.007ms	285	300	95.00
		aes_ctr_fi	5.000s	79.973us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	48.000s	1.683ms	50	50	100.00
		aes_control_fi	41.000s	10.007ms	285	300	95.00
		aes_cipher_fi	49.000s	10.006ms	339	350	96.86
V2S		TOTAL			955	985	96.95
V3		TOTAL			0	0	--
		TOTAL			1551	1582	98.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	11	91.67
V2S	11	11	8	72.73

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.48	99.02	97.58	99.43	95.81	95.66	97.78	98.67	92.49

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
- Test aes_control_fi has 9 failures.
  - 108.aes_control_fi.1474689331
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/108.aes_control_fi/latest/run.log
```
  Job ID: smart:6a47ac11-b12a-4206-89d0-fd8f5a57677b
```
  - 127.aes_control_fi.889436585
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/127.aes_control_fi/latest/run.log
```
  Job ID: smart:a915f161-a338-415c-9513-baacdff5def0
```
  - ... and 7 more failures.
- Test aes_cipher_fi has 3 failures.
  - 133.aes_cipher_fi.3452273629
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/133.aes_cipher_fi/latest/run.log
```
  Job ID: smart:879c814b-afc8-4705-a20f-0b4e351d65d5
```
  - 141.aes_cipher_fi.4025149225
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/141.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b0d11f9b-7c8d-4a76-97a9-68744e1150fe
```
  - ... and 1 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:

Test aes_cipher_fi has 8 failures.

0.aes_cipher_fi.3538636696
Line 277, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10060847011 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10060847011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.aes_cipher_fi.22312195
Line 274, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/23.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10010289716 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010289716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:

Test aes_control_fi has 6 failures.

107.aes_control_fi.1653820838
Line 280, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/107.aes_control_fi/latest/run.log

  UVM_FATAL @ 10006910625 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006910625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

120.aes_control_fi.905870756
Line 277, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/120.aes_control_fi/latest/run.log

  UVM_FATAL @ 10033647144 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10033647144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:

Test aes_core_fi has 4 failures.

7.aes_core_fi.964892453
Line 277, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_core_fi/latest/run.log

  UVM_FATAL @ 10018256434 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018256434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.aes_core_fi.1368952115
Line 286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_core_fi/latest/run.log

  UVM_FATAL @ 10050485232 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10050485232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,984): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS)

has 1 failures:

Test aes_alert_reset has 1 failures.

29.aes_alert_reset.1050643034
Line 893, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 42631199 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 42589532 PS)
  UVM_ERROR @  42631199 ps: (aes_core.sv:984) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  42631199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---