877a77116
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | wake_up | aes_wake_up | 4.000s | 133.044us | 1 | 1 | 100.00 |
V1 | smoke | aes_smoke | 6.000s | 78.741us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | aes_csr_hw_reset | 3.000s | 112.320us | 5 | 5 | 100.00 |
V1 | csr_rw | aes_csr_rw | 5.000s | 52.046us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | aes_csr_bit_bash | 10.000s | 639.521us | 5 | 5 | 100.00 |
V1 | csr_aliasing | aes_csr_aliasing | 5.000s | 103.520us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 6.000s | 60.797us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 5.000s | 52.046us | 20 | 20 | 100.00 |
aes_csr_aliasing | 5.000s | 103.520us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 106 | 106 | 100.00 | |||
V2 | algorithm | aes_smoke | 6.000s | 78.741us | 50 | 50 | 100.00 |
aes_config_error | 44.000s | 2.519ms | 50 | 50 | 100.00 | ||
aes_stress | 2.200m | 1.553ms | 50 | 50 | 100.00 | ||
V2 | key_length | aes_smoke | 6.000s | 78.741us | 50 | 50 | 100.00 |
aes_config_error | 44.000s | 2.519ms | 50 | 50 | 100.00 | ||
aes_stress | 2.200m | 1.553ms | 50 | 50 | 100.00 | ||
V2 | back2back | aes_stress | 2.200m | 1.553ms | 50 | 50 | 100.00 |
aes_b2b | 1.550m | 1.193ms | 50 | 50 | 100.00 | ||
V2 | backpressure | aes_stress | 2.200m | 1.553ms | 50 | 50 | 100.00 |
V2 | multi_message | aes_smoke | 6.000s | 78.741us | 50 | 50 | 100.00 |
aes_config_error | 44.000s | 2.519ms | 50 | 50 | 100.00 | ||
aes_stress | 2.200m | 1.553ms | 50 | 50 | 100.00 | ||
aes_alert_reset | 2.517m | 6.383ms | 50 | 50 | 100.00 | ||
V2 | failure_test | aes_config_error | 44.000s | 2.519ms | 50 | 50 | 100.00 |
aes_alert_reset | 2.517m | 6.383ms | 50 | 50 | 100.00 | ||
aes_man_cfg_err | 11.000s | 295.385us | 50 | 50 | 100.00 | ||
V2 | trigger_clear_test | aes_clear | 23.000s | 753.166us | 50 | 50 | 100.00 |
V2 | nist_test_vectors | aes_nist_vectors | 10.000s | 496.466us | 1 | 1 | 100.00 |
V2 | reset_recovery | aes_alert_reset | 2.517m | 6.383ms | 50 | 50 | 100.00 |
V2 | stress | aes_stress | 2.200m | 1.553ms | 50 | 50 | 100.00 |
V2 | sideload | aes_stress | 2.200m | 1.553ms | 50 | 50 | 100.00 |
aes_sideload | 38.000s | 1.174ms | 50 | 50 | 100.00 | ||
V2 | deinitialization | aes_deinit | 17.000s | 691.087us | 50 | 50 | 100.00 |
V2 | alert_test | aes_alert_test | 5.000s | 55.894us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | aes_tl_errors | 6.000s | 108.109us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | aes_tl_errors | 6.000s | 108.109us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | aes_csr_hw_reset | 3.000s | 112.320us | 5 | 5 | 100.00 |
aes_csr_rw | 5.000s | 52.046us | 20 | 20 | 100.00 | ||
aes_csr_aliasing | 5.000s | 103.520us | 5 | 5 | 100.00 | ||
aes_same_csr_outstanding | 4.000s | 95.595us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | aes_csr_hw_reset | 3.000s | 112.320us | 5 | 5 | 100.00 |
aes_csr_rw | 5.000s | 52.046us | 20 | 20 | 100.00 | ||
aes_csr_aliasing | 5.000s | 103.520us | 5 | 5 | 100.00 | ||
aes_same_csr_outstanding | 4.000s | 95.595us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 491 | 491 | 100.00 | |||
V2S | reseeding | aes_reseed | 2.083m | 4.692ms | 50 | 50 | 100.00 |
V2S | fault_inject | aes_fi | 32.000s | 2.366ms | 48 | 50 | 96.00 |
aes_control_fi | 37.000s | 10.008ms | 283 | 300 | 94.33 | ||
aes_cipher_fi | 47.000s | 10.022ms | 340 | 350 | 97.14 | ||
V2S | shadow_reg_update_error | aes_shadow_reg_errors | 5.000s | 298.027us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 5.000s | 298.027us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 5.000s | 298.027us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 5.000s | 298.027us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 5.000s | 201.112us | 20 | 20 | 100.00 |
V2S | tl_intg_err | aes_sec_cm | 10.000s | 749.511us | 5 | 5 | 100.00 |
aes_tl_intg_err | 9.000s | 1.946ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | aes_tl_intg_err | 9.000s | 1.946ms | 20 | 20 | 100.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 2.517m | 6.383ms | 50 | 50 | 100.00 |
V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 5.000s | 298.027us | 20 | 20 | 100.00 |
V2S | sec_cm_main_config_sparse | aes_smoke | 6.000s | 78.741us | 50 | 50 | 100.00 |
aes_stress | 2.200m | 1.553ms | 50 | 50 | 100.00 | ||
aes_alert_reset | 2.517m | 6.383ms | 50 | 50 | 100.00 | ||
aes_core_fi | 7.000s | 233.883us | 70 | 70 | 100.00 | ||
V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 5.000s | 298.027us | 20 | 20 | 100.00 |
V2S | sec_cm_aux_config_regwen | aes_stress | 2.200m | 1.553ms | 50 | 50 | 100.00 |
aes_readability | 23.000s | 1.127ms | 50 | 50 | 100.00 | ||
V2S | sec_cm_key_sideload | aes_stress | 2.200m | 1.553ms | 50 | 50 | 100.00 |
aes_sideload | 38.000s | 1.174ms | 50 | 50 | 100.00 | ||
V2S | sec_cm_key_sw_unreadable | aes_readability | 23.000s | 1.127ms | 50 | 50 | 100.00 |
V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 23.000s | 1.127ms | 50 | 50 | 100.00 |
V2S | sec_cm_key_sec_wipe | aes_readability | 23.000s | 1.127ms | 50 | 50 | 100.00 |
V2S | sec_cm_iv_config_sec_wipe | aes_readability | 23.000s | 1.127ms | 50 | 50 | 100.00 |
V2S | sec_cm_data_reg_sec_wipe | aes_readability | 23.000s | 1.127ms | 50 | 50 | 100.00 |
V2S | sec_cm_data_reg_key_sca | aes_stress | 2.200m | 1.553ms | 50 | 50 | 100.00 |
V2S | sec_cm_key_masking | aes_stress | 2.200m | 1.553ms | 50 | 50 | 100.00 |
V2S | sec_cm_main_fsm_sparse | aes_fi | 32.000s | 2.366ms | 48 | 50 | 96.00 |
V2S | sec_cm_main_fsm_redun | aes_fi | 32.000s | 2.366ms | 48 | 50 | 96.00 |
aes_control_fi | 37.000s | 10.008ms | 283 | 300 | 94.33 | ||
aes_cipher_fi | 47.000s | 10.022ms | 340 | 350 | 97.14 | ||
aes_ctr_fi | 5.000s | 54.664us | 49 | 50 | 98.00 | ||
V2S | sec_cm_cipher_fsm_sparse | aes_fi | 32.000s | 2.366ms | 48 | 50 | 96.00 |
V2S | sec_cm_cipher_fsm_redun | aes_fi | 32.000s | 2.366ms | 48 | 50 | 96.00 |
aes_control_fi | 37.000s | 10.008ms | 283 | 300 | 94.33 | ||
aes_cipher_fi | 47.000s | 10.022ms | 340 | 350 | 97.14 | ||
V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 47.000s | 10.022ms | 340 | 350 | 97.14 |
V2S | sec_cm_ctr_fsm_sparse | aes_fi | 32.000s | 2.366ms | 48 | 50 | 96.00 |
V2S | sec_cm_ctr_fsm_redun | aes_fi | 32.000s | 2.366ms | 48 | 50 | 96.00 |
aes_control_fi | 37.000s | 10.008ms | 283 | 300 | 94.33 | ||
aes_ctr_fi | 5.000s | 54.664us | 49 | 50 | 98.00 | ||
V2S | sec_cm_ctrl_sparse | aes_fi | 32.000s | 2.366ms | 48 | 50 | 96.00 |
aes_control_fi | 37.000s | 10.008ms | 283 | 300 | 94.33 | ||
aes_cipher_fi | 47.000s | 10.022ms | 340 | 350 | 97.14 | ||
aes_ctr_fi | 5.000s | 54.664us | 49 | 50 | 98.00 | ||
V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 2.517m | 6.383ms | 50 | 50 | 100.00 |
V2S | sec_cm_main_fsm_local_esc | aes_fi | 32.000s | 2.366ms | 48 | 50 | 96.00 |
aes_control_fi | 37.000s | 10.008ms | 283 | 300 | 94.33 | ||
aes_cipher_fi | 47.000s | 10.022ms | 340 | 350 | 97.14 | ||
aes_ctr_fi | 5.000s | 54.664us | 49 | 50 | 98.00 | ||
V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 32.000s | 2.366ms | 48 | 50 | 96.00 |
aes_control_fi | 37.000s | 10.008ms | 283 | 300 | 94.33 | ||
aes_cipher_fi | 47.000s | 10.022ms | 340 | 350 | 97.14 | ||
aes_ctr_fi | 5.000s | 54.664us | 49 | 50 | 98.00 | ||
V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 32.000s | 2.366ms | 48 | 50 | 96.00 |
aes_control_fi | 37.000s | 10.008ms | 283 | 300 | 94.33 | ||
aes_ctr_fi | 5.000s | 54.664us | 49 | 50 | 98.00 | ||
V2S | sec_cm_data_reg_local_esc | aes_fi | 32.000s | 2.366ms | 48 | 50 | 96.00 |
aes_control_fi | 37.000s | 10.008ms | 283 | 300 | 94.33 | ||
aes_cipher_fi | 47.000s | 10.022ms | 340 | 350 | 97.14 | ||
V2S | TOTAL | 955 | 985 | 96.95 | |||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 1552 | 1582 | 98.10 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 12 | 12 | 12 | 100.00 |
V2S | 11 | 11 | 7 | 63.64 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.48 | 99.01 | 97.60 | 99.36 | 96.01 | 95.66 | 98.52 | 98.67 | 92.90 |
Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 19 failures:
Test aes_control_fi has 13 failures.
12.aes_control_fi.1318081252
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/12.aes_control_fi/latest/run.log
Job ID: smart:8e0a7bed-de02-41f5-8491-2ab5a38a53a0
35.aes_control_fi.3977109858
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/35.aes_control_fi/latest/run.log
Job ID: smart:29acdddf-4e68-4826-b40f-ea4fa3a8ff28
... and 11 more failures.
Test aes_ctr_fi has 1 failures.
30.aes_ctr_fi.1187931103
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/30.aes_ctr_fi/latest/run.log
Job ID: smart:599acd18-9632-492d-8fc3-cb42dcb9f393
Test aes_cipher_fi has 5 failures.
44.aes_cipher_fi.4021108731
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_cipher_fi/latest/run.log
Job ID: smart:4e515fa5-3465-469c-8ccd-eac69f30bf71
105.aes_cipher_fi.2042827302
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/105.aes_cipher_fi/latest/run.log
Job ID: smart:e605b7d6-fb3d-4414-a399-3f583986754c
... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
has 5 failures:
30.aes_cipher_fi.927063691
Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/30.aes_cipher_fi/latest/run.log
UVM_FATAL @ 10007695477 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10007695477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
134.aes_cipher_fi.2445906804
Line 280, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/134.aes_cipher_fi/latest/run.log
UVM_FATAL @ 10006899164 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10006899164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!
has 4 failures:
43.aes_control_fi.1948189379
Line 281, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/43.aes_control_fi/latest/run.log
UVM_FATAL @ 10007614444 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10007614444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
83.aes_control_fi.3207257155
Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/83.aes_control_fi/latest/run.log
UVM_FATAL @ 10024559341 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10024559341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS)
has 1 failures:
1.aes_fi.3141633799
Line 3841, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_fi/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 101111091 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 101020182 PS)
UVM_ERROR @ 101111091 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
UVM_INFO @ 101111091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset
has 1 failures:
18.aes_fi.2216366461
Line 20433, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_fi/latest/run.log
UVM_FATAL @ 268881156 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
UVM_INFO @ 268881156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---