AES/UNMASKED Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: `26b0ee226`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 844256362

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	110.839us	1	1	100.00
V1	smoke	aes_smoke	5.000s	303.715us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	52.628us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	212.022us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	3.359ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	475.993us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	133.195us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	212.022us	20	20	100.00
		aes_csr_aliasing	6.000s	475.993us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	5.000s	303.715us	50	50	100.00
		aes_config_error	20.000s	659.098us	50	50	100.00
		aes_stress	40.000s	7.062ms	50	50	100.00
V2	key_length	aes_smoke	5.000s	303.715us	50	50	100.00
		aes_config_error	20.000s	659.098us	50	50	100.00
		aes_stress	40.000s	7.062ms	50	50	100.00
V2	back2back	aes_stress	40.000s	7.062ms	50	50	100.00
		aes_b2b	12.000s	137.043us	50	50	100.00
V2	backpressure	aes_stress	40.000s	7.062ms	50	50	100.00
V2	multi_message	aes_smoke	5.000s	303.715us	50	50	100.00
		aes_config_error	20.000s	659.098us	50	50	100.00
		aes_stress	40.000s	7.062ms	50	50	100.00
		aes_alert_reset	6.000s	545.181us	48	50	96.00
V2	failure_test	aes_config_error	20.000s	659.098us	50	50	100.00
		aes_alert_reset	6.000s	545.181us	48	50	96.00
		aes_man_cfg_err	5.000s	56.889us	50	50	100.00
V2	trigger_clear_test	aes_clear	8.000s	167.376us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	245.945us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	545.181us	48	50	96.00
V2	stress	aes_stress	40.000s	7.062ms	50	50	100.00
V2	sideload	aes_stress	40.000s	7.062ms	50	50	100.00
		aes_sideload	7.000s	435.526us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	238.902us	50	50	100.00
V2	alert_test	aes_alert_test	4.000s	85.455us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	187.697us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	187.697us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	52.628us	5	5	100.00
		aes_csr_rw	5.000s	212.022us	20	20	100.00
		aes_csr_aliasing	6.000s	475.993us	5	5	100.00
		aes_same_csr_outstanding	4.000s	162.976us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	52.628us	5	5	100.00
		aes_csr_rw	5.000s	212.022us	20	20	100.00
		aes_csr_aliasing	6.000s	475.993us	5	5	100.00
		aes_same_csr_outstanding	4.000s	162.976us	20	20	100.00
V2		TOTAL			489	491	99.59
V2S	reseeding	aes_reseed	46.000s	2.776ms	49	50	98.00
V2S	fault_inject	aes_fi	6.000s	93.691us	50	50	100.00
		aes_control_fi	55.000s	63.031ms	285	300	95.00
		aes_cipher_fi	54.000s	32.836ms	323	350	92.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	119.146us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	119.146us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	119.146us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	119.146us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	371.976us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	858.586us	5	5	100.00
		aes_tl_intg_err	6.000s	189.175us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	189.175us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	545.181us	48	50	96.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	119.146us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	303.715us	50	50	100.00
		aes_stress	40.000s	7.062ms	50	50	100.00
		aes_alert_reset	6.000s	545.181us	48	50	96.00
		aes_core_fi	1.117m	10.014ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	119.146us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	40.000s	7.062ms	50	50	100.00
		aes_readability	6.000s	299.075us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	40.000s	7.062ms	50	50	100.00
		aes_sideload	7.000s	435.526us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	299.075us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	299.075us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	299.075us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	299.075us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	299.075us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	40.000s	7.062ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	40.000s	7.062ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	93.691us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	93.691us	50	50	100.00
		aes_control_fi	55.000s	63.031ms	285	300	95.00
		aes_cipher_fi	54.000s	32.836ms	323	350	92.29
		aes_ctr_fi	4.000s	69.210us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	93.691us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	93.691us	50	50	100.00
		aes_control_fi	55.000s	63.031ms	285	300	95.00
		aes_cipher_fi	54.000s	32.836ms	323	350	92.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	54.000s	32.836ms	323	350	92.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	93.691us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	93.691us	50	50	100.00
		aes_control_fi	55.000s	63.031ms	285	300	95.00
		aes_ctr_fi	4.000s	69.210us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	93.691us	50	50	100.00
		aes_control_fi	55.000s	63.031ms	285	300	95.00
		aes_cipher_fi	54.000s	32.836ms	323	350	92.29
		aes_ctr_fi	4.000s	69.210us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	545.181us	48	50	96.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	93.691us	50	50	100.00
		aes_control_fi	55.000s	63.031ms	285	300	95.00
		aes_cipher_fi	54.000s	32.836ms	323	350	92.29
		aes_ctr_fi	4.000s	69.210us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	93.691us	50	50	100.00
		aes_control_fi	55.000s	63.031ms	285	300	95.00
		aes_cipher_fi	54.000s	32.836ms	323	350	92.29
		aes_ctr_fi	4.000s	69.210us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	93.691us	50	50	100.00
		aes_control_fi	55.000s	63.031ms	285	300	95.00
		aes_ctr_fi	4.000s	69.210us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	93.691us	50	50	100.00
		aes_control_fi	55.000s	63.031ms	285	300	95.00
		aes_cipher_fi	54.000s	32.836ms	323	350	92.29
V2S		TOTAL			936	985	95.03
V3		TOTAL			0	0	--
		TOTAL			1531	1582	96.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	11	91.67
V2S	11	11	7	63.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.11	97.56	94.48	98.77	93.65	97.72	91.11	98.07	92.09

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 25 failures:
- Test aes_control_fi has 7 failures.
  - 4.aes_control_fi.3685029499
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job ID: smart:9ed9da1e-5a24-487f-b181-f007da95cd0c
```
  - 11.aes_control_fi.1192848652
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  Job ID: smart:9109fae4-d5e9-452a-bda7-cac16a24b29a
```
  - ... and 5 more failures.
- Test aes_cipher_fi has 18 failures.
  - 22.aes_cipher_fi.3910025592
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  Job ID: smart:83d91731-3762-453e-bad4-9ff15da89fab
```
  - 37.aes_cipher_fi.3626030361
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/37.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c45cf16f-35d1-44fd-ae1f-8fbb7d423190
```
  - ... and 16 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:

Test aes_cipher_fi has 9 failures.

74.aes_cipher_fi.450339498
Line 280, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/74.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10018323389 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018323389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

116.aes_cipher_fi.2845517250
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/116.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10019355823 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019355823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:

Test aes_control_fi has 8 failures.

83.aes_control_fi.285608186
Line 271, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/83.aes_control_fi/latest/run.log

  UVM_FATAL @ 10005167618 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005167618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

106.aes_control_fi.2214629510
Line 268, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/106.aes_control_fi/latest/run.log

  UVM_FATAL @ 10008063570 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008063570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:

Test aes_core_fi has 5 failures.

13.aes_core_fi.2537282588
Line 277, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_core_fi/latest/run.log

  UVM_FATAL @ 10003693991 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003693991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.aes_core_fi.315725360
Line 276, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/37.aes_core_fi/latest/run.log

  UVM_FATAL @ 10006641148 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006641148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_alert_reset has 2 failures.

0.aes_alert_reset.387469496
Line 1975, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 19814242 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 19792503 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 19814242 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 19792503 PS)
  UVM_ERROR @  19814242 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

34.aes_alert_reset.2175776345
Line 863, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 11889508 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 11849508 PS)
  UVM_ERROR @  11889508 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  11889508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 15.aes_core_fi.998473024
    Line 268, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013601578 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013601578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (aes_scoreboard.sv:621) scoreboard [scoreboard] # * has 1 failures:

Test aes_reseed has 1 failures.

31.aes_reseed.2724991345
Line 4198, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/31.aes_reseed/latest/run.log

  UVM_FATAL @  19995340 ps: (aes_scoreboard.sv:621) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
            TEST FAILED MESSAGES DID NOT MATCH
  
                 0 15      25      d8      0
                 1 00      dd      af      0