AES/UNMASKED Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: `94eb0df12`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 77475240

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	131.309us	1	1	100.00
V1	smoke	aes_smoke	7.000s	297.399us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	80.343us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	66.219us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	706.177us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	262.849us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	58.532us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	66.219us	20	20	100.00
		aes_csr_aliasing	5.000s	262.849us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	297.399us	50	50	100.00
		aes_config_error	6.000s	153.450us	50	50	100.00
		aes_stress	36.000s	881.120us	50	50	100.00
V2	key_length	aes_smoke	7.000s	297.399us	50	50	100.00
		aes_config_error	6.000s	153.450us	50	50	100.00
		aes_stress	36.000s	881.120us	50	50	100.00
V2	back2back	aes_stress	36.000s	881.120us	50	50	100.00
		aes_b2b	10.000s	528.018us	50	50	100.00
V2	backpressure	aes_stress	36.000s	881.120us	50	50	100.00
V2	multi_message	aes_smoke	7.000s	297.399us	50	50	100.00
		aes_config_error	6.000s	153.450us	50	50	100.00
		aes_stress	36.000s	881.120us	50	50	100.00
		aes_alert_reset	5.000s	66.918us	49	50	98.00
V2	failure_test	aes_config_error	6.000s	153.450us	50	50	100.00
		aes_alert_reset	5.000s	66.918us	49	50	98.00
		aes_man_cfg_err	5.000s	83.500us	50	50	100.00
V2	trigger_clear_test	aes_clear	6.000s	105.372us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	665.363us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	66.918us	49	50	98.00
V2	stress	aes_stress	36.000s	881.120us	50	50	100.00
V2	sideload	aes_stress	36.000s	881.120us	50	50	100.00
		aes_sideload	5.000s	86.148us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	675.937us	50	50	100.00
V2	alert_test	aes_alert_test	4.000s	55.773us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	173.622us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	173.622us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	80.343us	5	5	100.00
		aes_csr_rw	3.000s	66.219us	20	20	100.00
		aes_csr_aliasing	5.000s	262.849us	5	5	100.00
		aes_same_csr_outstanding	4.000s	322.830us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	80.343us	5	5	100.00
		aes_csr_rw	3.000s	66.219us	20	20	100.00
		aes_csr_aliasing	5.000s	262.849us	5	5	100.00
		aes_same_csr_outstanding	4.000s	322.830us	20	20	100.00
V2		TOTAL			490	491	99.80
V2S	reseeding	aes_reseed	39.000s	1.082ms	49	50	98.00
V2S	fault_inject	aes_fi	5.000s	68.982us	50	50	100.00
		aes_control_fi	53.000s	22.538ms	279	300	93.00
		aes_cipher_fi	43.000s	10.003ms	321	350	91.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	73.986us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	73.986us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	73.986us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	73.986us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	138.365us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.036ms	5	5	100.00
		aes_tl_intg_err	6.000s	219.362us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	219.362us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	66.918us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	73.986us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	297.399us	50	50	100.00
		aes_stress	36.000s	881.120us	50	50	100.00
		aes_alert_reset	5.000s	66.918us	49	50	98.00
		aes_core_fi	44.000s	10.003ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	73.986us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	36.000s	881.120us	50	50	100.00
		aes_readability	4.000s	106.427us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	36.000s	881.120us	50	50	100.00
		aes_sideload	5.000s	86.148us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	106.427us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	106.427us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	106.427us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	106.427us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	106.427us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	36.000s	881.120us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	36.000s	881.120us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	68.982us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	68.982us	50	50	100.00
		aes_control_fi	53.000s	22.538ms	279	300	93.00
		aes_cipher_fi	43.000s	10.003ms	321	350	91.71
		aes_ctr_fi	4.000s	89.502us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	68.982us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	68.982us	50	50	100.00
		aes_control_fi	53.000s	22.538ms	279	300	93.00
		aes_cipher_fi	43.000s	10.003ms	321	350	91.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	43.000s	10.003ms	321	350	91.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	68.982us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	68.982us	50	50	100.00
		aes_control_fi	53.000s	22.538ms	279	300	93.00
		aes_ctr_fi	4.000s	89.502us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	68.982us	50	50	100.00
		aes_control_fi	53.000s	22.538ms	279	300	93.00
		aes_cipher_fi	43.000s	10.003ms	321	350	91.71
		aes_ctr_fi	4.000s	89.502us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	66.918us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	68.982us	50	50	100.00
		aes_control_fi	53.000s	22.538ms	279	300	93.00
		aes_cipher_fi	43.000s	10.003ms	321	350	91.71
		aes_ctr_fi	4.000s	89.502us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	68.982us	50	50	100.00
		aes_control_fi	53.000s	22.538ms	279	300	93.00
		aes_cipher_fi	43.000s	10.003ms	321	350	91.71
		aes_ctr_fi	4.000s	89.502us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	68.982us	50	50	100.00
		aes_control_fi	53.000s	22.538ms	279	300	93.00
		aes_ctr_fi	4.000s	89.502us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	68.982us	50	50	100.00
		aes_control_fi	53.000s	22.538ms	279	300	93.00
		aes_cipher_fi	43.000s	10.003ms	321	350	91.71
V2S		TOTAL			930	985	94.42
V3		TOTAL			0	0	--
		TOTAL			1526	1582	96.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	11	91.67
V2S	11	11	6	54.55

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.22	97.65	94.69	98.81	93.83	97.72	91.11	98.26	93.31

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 33 failures:
- Test aes_control_fi has 11 failures.
  - 10.aes_control_fi.2713007446
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job ID: smart:3e3d85f6-4550-4b6c-9868-4f2cbbf677cb
```
  - 22.aes_control_fi.2590583575
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job ID: smart:cbe8e273-5d18-4755-9b5b-de0154d380f9
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 21 failures.
  - 13.aes_cipher_fi.2445406780
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  Job ID: smart:de6e4a6a-42a0-4250-b187-0d121b2531bf
```
  - 15.aes_cipher_fi.619706337
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  Job ID: smart:cbeda56c-8404-41ea-854d-9ff06b1dd07f
```
  - ... and 19 more failures.
- Test aes_ctr_fi has 1 failures.
  - 38.aes_ctr_fi.3457552111
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/38.aes_ctr_fi/latest/run.log
```
  Job ID: smart:69ea8451-9340-4370-a931-cdefb44afaaf
```

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:

Test aes_control_fi has 10 failures.

48.aes_control_fi.2268483673
Line 281, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/48.aes_control_fi/latest/run.log

  UVM_FATAL @ 10012505352 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012505352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

61.aes_control_fi.2717349803
Line 271, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/61.aes_control_fi/latest/run.log

  UVM_FATAL @ 10006595750 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006595750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:

Test aes_cipher_fi has 8 failures.

42.aes_cipher_fi.3420930564
Line 272, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/42.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10012346538 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012346538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

60.aes_cipher_fi.2257946990
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/60.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10031297395 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10031297395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

67.aes_core_fi.3147922307
Line 268, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/67.aes_core_fi/latest/run.log

  UVM_FATAL @ 10004863841 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004863841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

68.aes_core_fi.456693970
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/68.aes_core_fi/latest/run.log

  UVM_FATAL @ 10003236989 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003236989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

4.aes_alert_reset.1193787412
Line 2084, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 9950757 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 9940340 PS)
  UVM_ERROR @   9950757 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @   9950757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_scoreboard.sv:621) scoreboard [scoreboard] # * has 1 failures:

Test aes_reseed has 1 failures.

16.aes_reseed.1848151355
Line 1015, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_reseed/latest/run.log

  UVM_FATAL @   9064200 ps: (aes_scoreboard.sv:621) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
            TEST FAILED MESSAGES DID NOT MATCH
  
                 0 c4      7e      19      0
                 1 00      2b      b5      0

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 46.aes_core_fi.3998519116
    Line 270, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10024874130 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10024874130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```