AES/UNMASKED Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: `213e792ea`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	77.327us	1	1	100.00
V1	smoke	aes_smoke	5.000s	147.746us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	52.360us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	66.759us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	185.683us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	66.425us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	109.750us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	66.759us	20	20	100.00
		aes_csr_aliasing	5.000s	66.425us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	5.000s	147.746us	50	50	100.00
		aes_config_error	5.000s	168.682us	50	50	100.00
		aes_stress	31.000s	609.495us	50	50	100.00
V2	key_length	aes_smoke	5.000s	147.746us	50	50	100.00
		aes_config_error	5.000s	168.682us	50	50	100.00
		aes_stress	31.000s	609.495us	50	50	100.00
V2	back2back	aes_stress	31.000s	609.495us	50	50	100.00
		aes_b2b	11.000s	382.527us	50	50	100.00
V2	backpressure	aes_stress	31.000s	609.495us	50	50	100.00
V2	multi_message	aes_smoke	5.000s	147.746us	50	50	100.00
		aes_config_error	5.000s	168.682us	50	50	100.00
		aes_stress	31.000s	609.495us	50	50	100.00
		aes_alert_reset	9.000s	387.034us	49	50	98.00
V2	failure_test	aes_config_error	5.000s	168.682us	50	50	100.00
		aes_alert_reset	9.000s	387.034us	49	50	98.00
		aes_man_cfg_err	4.000s	69.000us	50	50	100.00
V2	trigger_clear_test	aes_clear	6.000s	72.733us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	416.115us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	387.034us	49	50	98.00
V2	stress	aes_stress	31.000s	609.495us	50	50	100.00
V2	sideload	aes_stress	31.000s	609.495us	50	50	100.00
		aes_sideload	7.000s	262.830us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	131.168us	50	50	100.00
V2	alert_test	aes_alert_test	5.000s	60.891us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	286.524us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	286.524us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	52.360us	5	5	100.00
		aes_csr_rw	4.000s	66.759us	20	20	100.00
		aes_csr_aliasing	5.000s	66.425us	5	5	100.00
		aes_same_csr_outstanding	5.000s	274.413us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	52.360us	5	5	100.00
		aes_csr_rw	4.000s	66.759us	20	20	100.00
		aes_csr_aliasing	5.000s	66.425us	5	5	100.00
		aes_same_csr_outstanding	5.000s	274.413us	20	20	100.00
V2		TOTAL			490	491	99.80
V2S	reseeding	aes_reseed	41.000s	7.141ms	48	50	96.00
V2S	fault_inject	aes_fi	6.000s	155.749us	50	50	100.00
		aes_control_fi	50.000s	15.788ms	270	300	90.00
		aes_cipher_fi	48.000s	32.179ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	68.850us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	68.850us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	68.850us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	68.850us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	78.229us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	2.054ms	5	5	100.00
		aes_tl_intg_err	6.000s	635.294us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	635.294us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	387.034us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	68.850us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	147.746us	50	50	100.00
		aes_stress	31.000s	609.495us	50	50	100.00
		aes_alert_reset	9.000s	387.034us	49	50	98.00
		aes_core_fi	5.883m	10.011ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	68.850us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	31.000s	609.495us	50	50	100.00
		aes_readability	5.000s	103.809us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	31.000s	609.495us	50	50	100.00
		aes_sideload	7.000s	262.830us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	103.809us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	103.809us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	103.809us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	103.809us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	103.809us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	31.000s	609.495us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	31.000s	609.495us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	155.749us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	155.749us	50	50	100.00
		aes_control_fi	50.000s	15.788ms	270	300	90.00
		aes_cipher_fi	48.000s	32.179ms	329	350	94.00
		aes_ctr_fi	4.000s	69.677us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	155.749us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	155.749us	50	50	100.00
		aes_control_fi	50.000s	15.788ms	270	300	90.00
		aes_cipher_fi	48.000s	32.179ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	32.179ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	155.749us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	155.749us	50	50	100.00
		aes_control_fi	50.000s	15.788ms	270	300	90.00
		aes_ctr_fi	4.000s	69.677us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	155.749us	50	50	100.00
		aes_control_fi	50.000s	15.788ms	270	300	90.00
		aes_cipher_fi	48.000s	32.179ms	329	350	94.00
		aes_ctr_fi	4.000s	69.677us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	387.034us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	155.749us	50	50	100.00
		aes_control_fi	50.000s	15.788ms	270	300	90.00
		aes_cipher_fi	48.000s	32.179ms	329	350	94.00
		aes_ctr_fi	4.000s	69.677us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	155.749us	50	50	100.00
		aes_control_fi	50.000s	15.788ms	270	300	90.00
		aes_cipher_fi	48.000s	32.179ms	329	350	94.00
		aes_ctr_fi	4.000s	69.677us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	155.749us	50	50	100.00
		aes_control_fi	50.000s	15.788ms	270	300	90.00
		aes_ctr_fi	4.000s	69.677us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	155.749us	50	50	100.00
		aes_control_fi	50.000s	15.788ms	270	300	90.00
		aes_cipher_fi	48.000s	32.179ms	329	350	94.00
V2S		TOTAL			931	985	94.52
V3		TOTAL			0	0	--
		TOTAL			1527	1582	96.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	11	91.67
V2S	11	11	7	63.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.19	97.65	94.73	98.79	93.65	97.64	91.11	98.07	93.31

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 41 failures:
- Test aes_control_fi has 25 failures.
  - 4.aes_control_fi.3137631418
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job ID: smart:3c615c52-ff63-40d8-9ceb-e4de7729244a
```
  - 5.aes_control_fi.1045899009
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  Job ID: smart:833c0c79-bf5a-46fe-81a3-d5937d188378
```
  - ... and 23 more failures.
- Test aes_cipher_fi has 16 failures.
  - 14.aes_cipher_fi.1536245112
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job ID: smart:2abb012f-dfd4-41d8-b42d-2a17baecde03
```
  - 35.aes_cipher_fi.960981871
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_cipher_fi/latest/run.log
```
  Job ID: smart:02a37d8a-5eb3-46fa-9858-e9118fe01fd8
```
  - ... and 14 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:

Test aes_cipher_fi has 5 failures.

41.aes_cipher_fi.3251880539
Line 270, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10006725343 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006725343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

77.aes_cipher_fi.1995265784
Line 270, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/77.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10008378803 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008378803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:

Test aes_control_fi has 5 failures.

51.aes_control_fi.847015444
Line 273, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/51.aes_control_fi/latest/run.log

  UVM_FATAL @ 10008034667 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008034667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

102.aes_control_fi.2024419116
Line 269, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/102.aes_control_fi/latest/run.log

  UVM_FATAL @ 10008193644 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008193644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_scoreboard.sv:621) scoreboard [scoreboard] # * has 2 failures:

Test aes_reseed has 2 failures.

4.aes_reseed.1164961531
Line 4228, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_reseed/latest/run.log

  UVM_FATAL @  18253430 ps: (aes_scoreboard.sv:621) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
            TEST FAILED MESSAGES DID NOT MATCH
  
                 0 cf      b5      27      0
                 1 00      47      e5      0

21.aes_reseed.316902797
Line 4618, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_reseed/latest/run.log

  UVM_FATAL @  19335406 ps: (aes_scoreboard.sv:621) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
            TEST FAILED MESSAGES DID NOT MATCH
  
                 0 f9      42      5f      0
                 1 00      7a      95      0

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 5.aes_core_fi.292359328
    Line 274, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011151941 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xd30fdb84) == 0x0
  UVM_INFO @ 10011151941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

15.aes_alert_reset.1090928502
Line 723, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 6898823 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 6871796 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 6898823 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 6871796 PS)
  UVM_ERROR @   6898823 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut