AES/UNMASKED Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2359737659

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	103.179us	1	1	100.00
V1	smoke	aes_smoke	4.000s	163.965us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	61.838us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	107.952us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.298ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	526.947us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	263.472us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	107.952us	20	20	100.00
		aes_csr_aliasing	4.000s	526.947us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	163.965us	50	50	100.00
		aes_config_error	8.000s	242.418us	50	50	100.00
		aes_stress	38.000s	5.671ms	50	50	100.00
V2	key_length	aes_smoke	4.000s	163.965us	50	50	100.00
		aes_config_error	8.000s	242.418us	50	50	100.00
		aes_stress	38.000s	5.671ms	50	50	100.00
V2	back2back	aes_stress	38.000s	5.671ms	50	50	100.00
		aes_b2b	11.000s	146.404us	50	50	100.00
V2	backpressure	aes_stress	38.000s	5.671ms	50	50	100.00
V2	multi_message	aes_smoke	4.000s	163.965us	50	50	100.00
		aes_config_error	8.000s	242.418us	50	50	100.00
		aes_stress	38.000s	5.671ms	50	50	100.00
		aes_alert_reset	7.000s	114.832us	50	50	100.00
V2	failure_test	aes_config_error	8.000s	242.418us	50	50	100.00
		aes_alert_reset	7.000s	114.832us	50	50	100.00
		aes_man_cfg_err	6.000s	128.703us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	80.061us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	707.356us	1	1	100.00
V2	reset_recovery	aes_alert_reset	7.000s	114.832us	50	50	100.00
V2	stress	aes_stress	38.000s	5.671ms	50	50	100.00
V2	sideload	aes_stress	38.000s	5.671ms	50	50	100.00
		aes_sideload	7.000s	217.684us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	142.527us	50	50	100.00
V2	alert_test	aes_alert_test	4.000s	66.715us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	123.095us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	123.095us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	61.838us	5	5	100.00
		aes_csr_rw	4.000s	107.952us	20	20	100.00
		aes_csr_aliasing	4.000s	526.947us	5	5	100.00
		aes_same_csr_outstanding	5.000s	90.677us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	61.838us	5	5	100.00
		aes_csr_rw	4.000s	107.952us	20	20	100.00
		aes_csr_aliasing	4.000s	526.947us	5	5	100.00
		aes_same_csr_outstanding	5.000s	90.677us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	42.000s	2.599ms	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	584.313us	50	50	100.00
		aes_control_fi	44.000s	20.759ms	280	300	93.33
		aes_cipher_fi	47.000s	49.247ms	322	350	92.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	86.504us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	86.504us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	86.504us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	86.504us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	376.841us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.296ms	5	5	100.00
		aes_tl_intg_err	5.000s	437.923us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	437.923us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	7.000s	114.832us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	86.504us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	163.965us	50	50	100.00
		aes_stress	38.000s	5.671ms	50	50	100.00
		aes_alert_reset	7.000s	114.832us	50	50	100.00
		aes_core_fi	6.083m	10.010ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	86.504us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	38.000s	5.671ms	50	50	100.00
		aes_readability	5.000s	192.171us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	38.000s	5.671ms	50	50	100.00
		aes_sideload	7.000s	217.684us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	192.171us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	192.171us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	192.171us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	192.171us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	192.171us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	38.000s	5.671ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	38.000s	5.671ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	584.313us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	584.313us	50	50	100.00
		aes_control_fi	44.000s	20.759ms	280	300	93.33
		aes_cipher_fi	47.000s	49.247ms	322	350	92.00
		aes_ctr_fi	4.000s	63.998us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	584.313us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	584.313us	50	50	100.00
		aes_control_fi	44.000s	20.759ms	280	300	93.33
		aes_cipher_fi	47.000s	49.247ms	322	350	92.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	49.247ms	322	350	92.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	584.313us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	584.313us	50	50	100.00
		aes_control_fi	44.000s	20.759ms	280	300	93.33
		aes_ctr_fi	4.000s	63.998us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	584.313us	50	50	100.00
		aes_control_fi	44.000s	20.759ms	280	300	93.33
		aes_cipher_fi	47.000s	49.247ms	322	350	92.00
		aes_ctr_fi	4.000s	63.998us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	7.000s	114.832us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	584.313us	50	50	100.00
		aes_control_fi	44.000s	20.759ms	280	300	93.33
		aes_cipher_fi	47.000s	49.247ms	322	350	92.00
		aes_ctr_fi	4.000s	63.998us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	584.313us	50	50	100.00
		aes_control_fi	44.000s	20.759ms	280	300	93.33
		aes_cipher_fi	47.000s	49.247ms	322	350	92.00
		aes_ctr_fi	4.000s	63.998us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	584.313us	50	50	100.00
		aes_control_fi	44.000s	20.759ms	280	300	93.33
		aes_ctr_fi	4.000s	63.998us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	584.313us	50	50	100.00
		aes_control_fi	44.000s	20.759ms	280	300	93.33
		aes_cipher_fi	47.000s	49.247ms	322	350	92.00
V2S		TOTAL			931	985	94.52
V3		TOTAL			0	0	--
		TOTAL			1528	1582	96.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	7	63.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.12	97.60	94.56	98.79	93.68	97.64	91.11	98.07	91.48

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 33 failures:
- Test aes_control_fi has 14 failures.
  - 1.aes_control_fi.2962679635
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  Job ID: smart:4ac74823-95c7-4695-8d15-e3b61d8c5ebb
```
  - 22.aes_control_fi.628588204
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job ID: smart:3d7b710b-9b56-45bc-9ada-9c5a27283339
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 18 failures.
  - 15.aes_cipher_fi.3571808254
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  Job ID: smart:945e1df8-779c-46fc-baff-b69d79c1df2a
```
  - 25.aes_cipher_fi.3493253284
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  Job ID: smart:686b96da-2ba2-49eb-a742-6ad7fbc03549
```
  - ... and 16 more failures.
- Test aes_ctr_fi has 1 failures.
  - 26.aes_ctr_fi.870095642
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/26.aes_ctr_fi/latest/run.log
```
  Job ID: smart:3f7f2017-9eee-4666-a8ee-c6eb9eb1dbcd
```

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:

Test aes_cipher_fi has 9 failures.

49.aes_cipher_fi.1563394618
Line 274, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10095760099 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10095760099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

52.aes_cipher_fi.2688060808
Line 278, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10002928919 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002928919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:

Test aes_control_fi has 6 failures.

71.aes_control_fi.155920563
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/71.aes_control_fi/latest/run.log

  UVM_FATAL @ 10008194766 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008194766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

98.aes_control_fi.3091558325
Line 273, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/98.aes_control_fi/latest/run.log

  UVM_FATAL @ 10011759820 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011759820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:

Test aes_core_fi has 2 failures.

1.aes_core_fi.2067778239
Line 271, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_core_fi/latest/run.log

  UVM_FATAL @ 10009815197 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xd20f0984) == 0x0
  UVM_INFO @ 10009815197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_core_fi.3672929995
Line 276, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_core_fi/latest/run.log

  UVM_FATAL @ 10012286961 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xdeb5dd84) == 0x0
  UVM_INFO @ 10012286961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

2.aes_core_fi.2116264498
Line 278, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_core_fi/latest/run.log

  UVM_FATAL @ 10002101280 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002101280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_core_fi.2273232408
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_core_fi/latest/run.log

  UVM_FATAL @ 10011685461 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011685461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 16.aes_core_fi.2842433278
    Line 277, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10043070963 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10043070963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 313.aes_cipher_fi.1153681764
    Line 281, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/313.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```