AES/UNMASKED Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: c06cc3921

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2869101736

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 4.000s 66.040us 1 1 100.00
V1 smoke aes_smoke 7.000s 217.099us 50 50 100.00
V1 csr_hw_reset aes_csr_hw_reset 3.000s 82.186us 5 5 100.00
V1 csr_rw aes_csr_rw 4.000s 120.319us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 9.000s 378.209us 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 5.000s 917.542us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 4.000s 92.236us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 4.000s 120.319us 20 20 100.00
aes_csr_aliasing 5.000s 917.542us 5 5 100.00
V1 TOTAL 106 106 100.00
V2 algorithm aes_smoke 7.000s 217.099us 50 50 100.00
aes_config_error 7.000s 233.137us 50 50 100.00
aes_stress 36.000s 1.826ms 50 50 100.00
V2 key_length aes_smoke 7.000s 217.099us 50 50 100.00
aes_config_error 7.000s 233.137us 50 50 100.00
aes_stress 36.000s 1.826ms 50 50 100.00
V2 back2back aes_stress 36.000s 1.826ms 50 50 100.00
aes_b2b 11.000s 195.363us 50 50 100.00
V2 backpressure aes_stress 36.000s 1.826ms 50 50 100.00
V2 multi_message aes_smoke 7.000s 217.099us 50 50 100.00
aes_config_error 7.000s 233.137us 50 50 100.00
aes_stress 36.000s 1.826ms 50 50 100.00
aes_alert_reset 6.000s 79.141us 49 50 98.00
V2 failure_test aes_config_error 7.000s 233.137us 50 50 100.00
aes_alert_reset 6.000s 79.141us 49 50 98.00
aes_man_cfg_err 5.000s 147.668us 50 50 100.00
V2 trigger_clear_test aes_clear 6.000s 1.056ms 50 50 100.00
V2 nist_test_vectors aes_nist_vectors 7.000s 297.866us 1 1 100.00
V2 reset_recovery aes_alert_reset 6.000s 79.141us 49 50 98.00
V2 stress aes_stress 36.000s 1.826ms 50 50 100.00
V2 sideload aes_stress 36.000s 1.826ms 50 50 100.00
aes_sideload 5.000s 112.544us 50 50 100.00
V2 deinitialization aes_deinit 6.000s 152.007us 50 50 100.00
V2 alert_test aes_alert_test 4.000s 84.735us 50 50 100.00
V2 tl_d_oob_addr_access aes_tl_errors 6.000s 464.465us 20 20 100.00
V2 tl_d_illegal_access aes_tl_errors 6.000s 464.465us 20 20 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 3.000s 82.186us 5 5 100.00
aes_csr_rw 4.000s 120.319us 20 20 100.00
aes_csr_aliasing 5.000s 917.542us 5 5 100.00
aes_same_csr_outstanding 5.000s 151.794us 20 20 100.00
V2 tl_d_partial_access aes_csr_hw_reset 3.000s 82.186us 5 5 100.00
aes_csr_rw 4.000s 120.319us 20 20 100.00
aes_csr_aliasing 5.000s 917.542us 5 5 100.00
aes_same_csr_outstanding 5.000s 151.794us 20 20 100.00
V2 TOTAL 490 491 99.80
V2S reseeding aes_reseed 46.000s 3.781ms 50 50 100.00
V2S fault_inject aes_fi 6.000s 171.386us 50 50 100.00
aes_control_fi 45.000s 10.002ms 265 300 88.33
aes_cipher_fi 55.000s 24.267ms 326 350 93.14
V2S shadow_reg_update_error aes_shadow_reg_errors 4.000s 91.418us 20 20 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 4.000s 91.418us 20 20 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 4.000s 91.418us 20 20 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 4.000s 91.418us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 6.000s 1.207ms 20 20 100.00
V2S tl_intg_err aes_sec_cm 10.000s 1.472ms 5 5 100.00
aes_tl_intg_err 6.000s 203.037us 20 20 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 6.000s 203.037us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 6.000s 79.141us 49 50 98.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 4.000s 91.418us 20 20 100.00
V2S sec_cm_main_config_sparse aes_smoke 7.000s 217.099us 50 50 100.00
aes_stress 36.000s 1.826ms 50 50 100.00
aes_alert_reset 6.000s 79.141us 49 50 98.00
aes_core_fi 1.433m 10.047ms 65 70 92.86
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 4.000s 91.418us 20 20 100.00
V2S sec_cm_aux_config_regwen aes_stress 36.000s 1.826ms 50 50 100.00
aes_readability 4.000s 50.162us 50 50 100.00
V2S sec_cm_key_sideload aes_stress 36.000s 1.826ms 50 50 100.00
aes_sideload 5.000s 112.544us 50 50 100.00
V2S sec_cm_key_sw_unreadable aes_readability 4.000s 50.162us 50 50 100.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 4.000s 50.162us 50 50 100.00
V2S sec_cm_key_sec_wipe aes_readability 4.000s 50.162us 50 50 100.00
V2S sec_cm_iv_config_sec_wipe aes_readability 4.000s 50.162us 50 50 100.00
V2S sec_cm_data_reg_sec_wipe aes_readability 4.000s 50.162us 50 50 100.00
V2S sec_cm_data_reg_key_sca aes_stress 36.000s 1.826ms 50 50 100.00
V2S sec_cm_key_masking aes_stress 36.000s 1.826ms 50 50 100.00
V2S sec_cm_main_fsm_sparse aes_fi 6.000s 171.386us 50 50 100.00
V2S sec_cm_main_fsm_redun aes_fi 6.000s 171.386us 50 50 100.00
aes_control_fi 45.000s 10.002ms 265 300 88.33
aes_cipher_fi 55.000s 24.267ms 326 350 93.14
aes_ctr_fi 5.000s 99.136us 50 50 100.00
V2S sec_cm_cipher_fsm_sparse aes_fi 6.000s 171.386us 50 50 100.00
V2S sec_cm_cipher_fsm_redun aes_fi 6.000s 171.386us 50 50 100.00
aes_control_fi 45.000s 10.002ms 265 300 88.33
aes_cipher_fi 55.000s 24.267ms 326 350 93.14
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 55.000s 24.267ms 326 350 93.14
V2S sec_cm_ctr_fsm_sparse aes_fi 6.000s 171.386us 50 50 100.00
V2S sec_cm_ctr_fsm_redun aes_fi 6.000s 171.386us 50 50 100.00
aes_control_fi 45.000s 10.002ms 265 300 88.33
aes_ctr_fi 5.000s 99.136us 50 50 100.00
V2S sec_cm_ctrl_sparse aes_fi 6.000s 171.386us 50 50 100.00
aes_control_fi 45.000s 10.002ms 265 300 88.33
aes_cipher_fi 55.000s 24.267ms 326 350 93.14
aes_ctr_fi 5.000s 99.136us 50 50 100.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 6.000s 79.141us 49 50 98.00
V2S sec_cm_main_fsm_local_esc aes_fi 6.000s 171.386us 50 50 100.00
aes_control_fi 45.000s 10.002ms 265 300 88.33
aes_cipher_fi 55.000s 24.267ms 326 350 93.14
aes_ctr_fi 5.000s 99.136us 50 50 100.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 6.000s 171.386us 50 50 100.00
aes_control_fi 45.000s 10.002ms 265 300 88.33
aes_cipher_fi 55.000s 24.267ms 326 350 93.14
aes_ctr_fi 5.000s 99.136us 50 50 100.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 6.000s 171.386us 50 50 100.00
aes_control_fi 45.000s 10.002ms 265 300 88.33
aes_ctr_fi 5.000s 99.136us 50 50 100.00
V2S sec_cm_data_reg_local_esc aes_fi 6.000s 171.386us 50 50 100.00
aes_control_fi 45.000s 10.002ms 265 300 88.33
aes_cipher_fi 55.000s 24.267ms 326 350 93.14
V2S TOTAL 921 985 93.50
V3 TOTAL 0 0 --
TOTAL 1517 1582 95.89

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 12 12 11 91.67
V2S 11 11 8 72.73

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.12 97.54 94.48 98.75 93.80 97.72 91.11 98.07 92.29

Failure Buckets

Past Results