AES/UNMASKED Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: `877a77116`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 88555427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	67.711us	1	1	100.00
V1	smoke	aes_smoke	6.000s	91.545us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	86.562us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	73.831us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	1.512ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	611.647us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	99.050us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	73.831us	20	20	100.00
		aes_csr_aliasing	5.000s	611.647us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	91.545us	50	50	100.00
		aes_config_error	6.000s	67.095us	50	50	100.00
		aes_stress	33.000s	431.941us	50	50	100.00
V2	key_length	aes_smoke	6.000s	91.545us	50	50	100.00
		aes_config_error	6.000s	67.095us	50	50	100.00
		aes_stress	33.000s	431.941us	50	50	100.00
V2	back2back	aes_stress	33.000s	431.941us	50	50	100.00
		aes_b2b	13.000s	317.731us	50	50	100.00
V2	backpressure	aes_stress	33.000s	431.941us	50	50	100.00
V2	multi_message	aes_smoke	6.000s	91.545us	50	50	100.00
		aes_config_error	6.000s	67.095us	50	50	100.00
		aes_stress	33.000s	431.941us	50	50	100.00
		aes_alert_reset	5.000s	523.727us	50	50	100.00
V2	failure_test	aes_config_error	6.000s	67.095us	50	50	100.00
		aes_alert_reset	5.000s	523.727us	50	50	100.00
		aes_man_cfg_err	4.000s	72.085us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	1.322ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	237.002us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	523.727us	50	50	100.00
V2	stress	aes_stress	33.000s	431.941us	50	50	100.00
V2	sideload	aes_stress	33.000s	431.941us	50	50	100.00
		aes_sideload	6.000s	159.445us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	71.280us	50	50	100.00
V2	alert_test	aes_alert_test	5.000s	63.058us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	208.399us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	208.399us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	86.562us	5	5	100.00
		aes_csr_rw	4.000s	73.831us	20	20	100.00
		aes_csr_aliasing	5.000s	611.647us	5	5	100.00
		aes_same_csr_outstanding	4.000s	239.777us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	86.562us	5	5	100.00
		aes_csr_rw	4.000s	73.831us	20	20	100.00
		aes_csr_aliasing	5.000s	611.647us	5	5	100.00
		aes_same_csr_outstanding	4.000s	239.777us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	40.000s	489.692us	49	50	98.00
V2S	fault_inject	aes_fi	6.000s	112.382us	50	50	100.00
		aes_control_fi	53.000s	32.172ms	285	300	95.00
		aes_cipher_fi	54.000s	63.027ms	325	350	92.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	185.775us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	185.775us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	185.775us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	185.775us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	433.676us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	981.531us	5	5	100.00
		aes_tl_intg_err	5.000s	209.645us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	209.645us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	523.727us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	185.775us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	91.545us	50	50	100.00
		aes_stress	33.000s	431.941us	50	50	100.00
		aes_alert_reset	5.000s	523.727us	50	50	100.00
		aes_core_fi	1.633m	10.031ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	185.775us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	33.000s	431.941us	50	50	100.00
		aes_readability	6.000s	58.291us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	33.000s	431.941us	50	50	100.00
		aes_sideload	6.000s	159.445us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	58.291us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	58.291us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	58.291us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	58.291us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	58.291us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	33.000s	431.941us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	33.000s	431.941us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	112.382us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	112.382us	50	50	100.00
		aes_control_fi	53.000s	32.172ms	285	300	95.00
		aes_cipher_fi	54.000s	63.027ms	325	350	92.86
		aes_ctr_fi	4.000s	55.680us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	112.382us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	112.382us	50	50	100.00
		aes_control_fi	53.000s	32.172ms	285	300	95.00
		aes_cipher_fi	54.000s	63.027ms	325	350	92.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	54.000s	63.027ms	325	350	92.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	112.382us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	112.382us	50	50	100.00
		aes_control_fi	53.000s	32.172ms	285	300	95.00
		aes_ctr_fi	4.000s	55.680us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	112.382us	50	50	100.00
		aes_control_fi	53.000s	32.172ms	285	300	95.00
		aes_cipher_fi	54.000s	63.027ms	325	350	92.86
		aes_ctr_fi	4.000s	55.680us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	523.727us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	112.382us	50	50	100.00
		aes_control_fi	53.000s	32.172ms	285	300	95.00
		aes_cipher_fi	54.000s	63.027ms	325	350	92.86
		aes_ctr_fi	4.000s	55.680us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	112.382us	50	50	100.00
		aes_control_fi	53.000s	32.172ms	285	300	95.00
		aes_cipher_fi	54.000s	63.027ms	325	350	92.86
		aes_ctr_fi	4.000s	55.680us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	112.382us	50	50	100.00
		aes_control_fi	53.000s	32.172ms	285	300	95.00
		aes_ctr_fi	4.000s	55.680us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	112.382us	50	50	100.00
		aes_control_fi	53.000s	32.172ms	285	300	95.00
		aes_cipher_fi	54.000s	63.027ms	325	350	92.86
V2S		TOTAL			941	985	95.53
V3		TOTAL			0	0	--
		TOTAL			1538	1582	97.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	7	63.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.16	97.63	94.65	98.79	93.65	97.72	91.11	98.26	92.09

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 24 failures:
- Test aes_cipher_fi has 16 failures.
  - 6.aes_cipher_fi.3963721661
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  Job ID: smart:880adb67-067a-433d-93c9-4053ae316a49
```
  - 23.aes_cipher_fi.2083068975
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c4ab0a06-b5f0-413c-a741-b4a14efffa0f
```
  - ... and 14 more failures.
- Test aes_control_fi has 8 failures.
  - 53.aes_control_fi.427844391
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/53.aes_control_fi/latest/run.log
```
  Job ID: smart:22b19d8a-a653-42a3-8636-754fb2cbabf7
```
  - 67.aes_control_fi.287105288
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/67.aes_control_fi/latest/run.log
```
  Job ID: smart:8c2a437b-14df-453e-9667-1b9f55688972
```
  - ... and 6 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:

Test aes_cipher_fi has 9 failures.

59.aes_cipher_fi.1264587637
Line 273, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/59.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10007661815 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007661815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

88.aes_cipher_fi.3854539961
Line 286, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/88.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10006039436 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006039436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:

Test aes_control_fi has 6 failures.

23.aes_control_fi.3902504458
Line 270, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_control_fi/latest/run.log

  UVM_FATAL @ 10030592591 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030592591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

51.aes_control_fi.1734927001
Line 274, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/51.aes_control_fi/latest/run.log

  UVM_FATAL @ 10008874477 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008874477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

3.aes_core_fi.2484837755
Line 278, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_core_fi/latest/run.log

  UVM_FATAL @ 10012484356 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012484356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.aes_core_fi.2027560823
Line 276, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_core_fi/latest/run.log

  UVM_FATAL @ 10001904203 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10001904203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_scoreboard.sv:621) scoreboard [scoreboard] # * has 1 failures:

Test aes_reseed has 1 failures.

18.aes_reseed.3780173379
Line 1327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_reseed/latest/run.log

  UVM_FATAL @   8238355 ps: (aes_scoreboard.sv:621) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
            TEST FAILED MESSAGES DID NOT MATCH
  
                 0 52      f6      ea      0
                 1 00      9d      b3      0

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 32.aes_core_fi.2396235136
    Line 269, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10030595629 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x2730f584) == 0x0
  UVM_INFO @ 10030595629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 48.aes_control_fi.85966085
    Line 279, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/48.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```