AES

Context Info:
loaded run directory /workspace/cov_merge/merged model files domain : hdl /workspace/cov_merge/merged/icc_1a0aa758_137fca6c.ucm ucds files domain : hdl /workspace/cov_merge/merged/icc_1a0aa758_137fca6c.ucd loaded refinements /workspace/mnt/repo_top/hw/ip/aes/dv/cov/refines/aes_UNR.vRefine /workspace/mnt/repo_top/hw/ip/aes/dv/cov/refines/aes_unmasked_UNR.vRefine ccf files /workspace/mnt/repo_top/hw/dv/tools/xcelium/cover_reg_top.ccf // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // Include our common coverage CCF. include_ccf ${dv_root}/tools/xcelium/common.ccf /workspace/mnt/repo_top/hw/dv/tools/xcelium/common.ccf // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // Common coverage commands that apply to all DUTs. // // This coverge config file is provided by Xcelium and is located at: // ${XCELIUM_HOME}/tools/icc/include/all_coverage.ccf // Xcelium recommends including it, since it bundles together the common set of commands that enable // coverage collection on various design elements, that are otherwise turned off by default. We // maintain it locally with minor amends. // Enables expression coverage of various Verilog operators. set_expr_coverable_operators -all -event_or // Enables expression coverage of operators in various conditions and assignments. set_expr_coverable_statements -procassign -event_control -misc // Enables scoring of Verilog modules compiled with -v/-y or -libcell option but continues to // disable the scoring of Verilog modules defined with the 'celldefine compiler directive. set_libcell_scoring // Enables scoring of SystemVerilog continuous assignments, which is by disabled by default. set_assign_scoring // Scores branches together with block coverage. set_branch_scoring // Scores statements within a block. set_statement_scoring // Enables Toggle scoring and reporting of SystemVerilog enumerations and multidimensional static // arrays , vectors, packed union, modport and generate blocks. set_toggle_scoring -sv_enum enable_mda -sv_struct_with_enum -sv_modport -sv_mda 16 -sv_mda_of_struct -sv_generate -sv_packed_union // Enable toggle coverage only on ports. set_toggle_portsonly // Enable scoring of FSM arcs (state transitions). // TODO: re-enable this setting, temp disable due to #12544 // set_fsm_arc_scoring // Include X->1\|0 for toggle coverage collection. #10332 set_toggle_includex // For ternary operator in default SOP mode set_expr_scoring -vlog_short_circuit // Only collect code coverage on the _reg_top instance. deselect_coverage -betfs -module ${DUT_TOP}... select_coverage -befs -module _reg_top... deselect_coverage -betfs -module prim_onehot_check... deselect_coverage -betfs -module prim_secded_inv_64_57_dec... deselect_coverage -betfs -module prim_secded_inv_39_32_dec... // Black-box DV CDC module. deselect_coverage -betfs -module prim_cdc_rand_delay // csr_assert_fpv is an auto-generated csr read assertion module. So only assertion coverage is // meaningful to collect. deselect_coverage -betf -module csr_assert_fpv... select_coverage -assert -module csr_assert_fpv // Only enable assertion coverage deselect_coverage -betf -module tlul_assert... select_coverage -assert -module tlul_assert // Include toggle coverage on `prim_alert_sender` because the `alert_test` task under // `cip_base_vseq` drives `alert_test_i` and verifies `alert_rx/tx` handshake in each IP. select_coverage -toggle -module prim_alert_sender select_coverage -toggle -module prim_secded_inv_64_57_dec select_coverage -toggle -module prim_secded_inv_39_32_dec // TODO: The intent below is to only enable coverage on the DUT's TL interfaces (tests using this // ccf file are meant to fully exercise the TL interfaces, but they do not verify the rest of the // functionality of the block). We enable coverage on all DUT ports but exclude ports that do not // contain tl_i or tl_o in the port name using a separate excludefile that supports regexes. select_coverage -toggle -module ${DUT_TOP} set_toggle_excludefile ${dv_root}/tools/xcelium/cover_reg_top_toggle_excl

Context Info:

loaded run directory
  /workspace/cov_merge/merged

model files
  domain : hdl
    /workspace/cov_merge/merged/icc_1a0aa758_137fca6c.ucm

ucds files
  domain : hdl
    /workspace/cov_merge/merged/icc_1a0aa758_137fca6c.ucd

loaded refinements
  /workspace/mnt/repo_top/hw/ip/aes/dv/cov/refines/aes_UNR.vRefine
  /workspace/mnt/repo_top/hw/ip/aes/dv/cov/refines/aes_unmasked_UNR.vRefine

ccf files
  /workspace/mnt/repo_top/hw/dv/tools/xcelium/cover_reg_top.ccf
    // Copyright lowRISC contributors (OpenTitan project).
    // Licensed under the Apache License, Version 2.0, see LICENSE for details.
    // SPDX-License-Identifier: Apache-2.0

    // Include our common coverage CCF.
    include_ccf ${dv_root}/tools/xcelium/common.ccf
     /workspace/mnt/repo_top/hw/dv/tools/xcelium/common.ccf
     // Copyright lowRISC contributors (OpenTitan project).
     // Licensed under the Apache License, Version 2.0, see LICENSE for details.
     // SPDX-License-Identifier: Apache-2.0

     // Common coverage commands that apply to all DUTs.
     //
     // This coverge config file is provided by Xcelium and is located at:
     // ${XCELIUM_HOME}/tools/icc/include/all_coverage.ccf
     // Xcelium recommends including it, since it bundles together the common set of commands that enable
     // coverage collection on various design elements, that are otherwise turned off by default. We
     // maintain it locally with minor amends.

     // Enables expression coverage of various Verilog operators.
     set_expr_coverable_operators -all -event_or

     // Enables expression coverage of operators in various conditions and assignments.
     set_expr_coverable_statements -procassign -event_control -misc

     // Enables scoring of Verilog modules compiled with -v/-y or -libcell option but continues to
     // disable the scoring of Verilog modules defined with the 'celldefine compiler directive.
     set_libcell_scoring

     // Enables scoring of SystemVerilog continuous assignments, which is by disabled by default.
     set_assign_scoring

     // Scores branches together with block coverage.
     set_branch_scoring

     // Scores statements within a block.
     set_statement_scoring

     // Enables Toggle scoring and reporting of SystemVerilog enumerations and multidimensional static
     // arrays , vectors, packed union, modport and generate blocks.
     set_toggle_scoring -sv_enum enable_mda -sv_struct_with_enum -sv_modport -sv_mda 16 -sv_mda_of_struct -sv_generate -sv_packed_union

     // Enable toggle coverage only on ports.
     set_toggle_portsonly

     // Enable scoring of FSM arcs (state transitions).
     // TODO: re-enable this setting, temp disable due to #12544
     // set_fsm_arc_scoring

     // Include X->1|0 for toggle coverage collection. #10332
     set_toggle_includex

     // For ternary operator in default SOP mode
     set_expr_scoring -vlog_short_circuit

    // Only collect code coverage on the *_reg_top instance.
    deselect_coverage -betfs -module ${DUT_TOP}...
    select_coverage -befs -module *_reg_top...
    deselect_coverage -betfs -module prim_onehot_check...
    deselect_coverage -betfs -module prim_secded_inv_64_57_dec...
    deselect_coverage -betfs -module prim_secded_inv_39_32_dec...

    // Black-box DV CDC module.
    deselect_coverage -betfs -module prim_cdc_rand_delay

    // csr_assert_fpv is an auto-generated csr read assertion module. So only assertion coverage is
    // meaningful to collect.
    deselect_coverage -betf -module *csr_assert_fpv...
    select_coverage -assert -module *csr_assert_fpv

    // Only enable assertion coverage
    deselect_coverage -betf -module *tlul_assert...
    select_coverage -assert -module *tlul_assert

    // Include toggle coverage on `prim_alert_sender` because the `alert_test` task under
    // `cip_base_vseq` drives `alert_test_i` and verifies `alert_rx/tx` handshake in each IP.
    select_coverage -toggle -module prim_alert_sender
    select_coverage -toggle -module prim_secded_inv_64_57_dec
    select_coverage -toggle -module prim_secded_inv_39_32_dec

    // TODO: The intent below is to only enable coverage on the DUT's TL interfaces (tests using this
    // ccf file are meant to fully exercise the TL interfaces, but they do not verify the rest of the
    // functionality of the block). We enable coverage on all DUT ports but exclude ports that do not
    // contain tl_i or tl_o in the port name using a separate excludefile that supports regexes.
    select_coverage -toggle -module ${DUT_TOP}
    set_toggle_excludefile ${dv_root}/tools/xcelium/cover_reg_top_toggle_excl

Verification Scope: default

Metrics tree View Name: All_Metrics

Block View Name: Block

Expression View Name: Expression

Toggle View Name: Toggle

Statement View Name: Statement

FSM View Name: FSM

Cover group View Name: CoverGroups

Assertion View Name: Assertions

Block
Expression
Toggle
Statement
FSM
Cover Groups
Assertions

Block

Exclusion Rule Type	UNR	Index	Block Type	Source Line	Score	Enclosing Entity	Source Code

Top Level Expressions

Exclusion Rule Type	UNR	Index	Overall Average Grade	Overall Covered	Source Line	Enclosing Entity	Source Code

Coverage Tables

Exclusion Rule Type	UNR	Index	Overall Average Grade	Overall Covered

Exclusion Rule Type	UNR	No attribute	Score	Output

Exclusion Rule Type	UNR	No attribute	Score	Output

Parity Tree

Exclusion Rule Type	UNR	Exp	Score	Odd	Even

Variables Filter by name:

Exclusion Rule Type	UNR	Name	Range	Overall Average Grade	Overall Covered	Enclosing Entity	Source Code

Signals Filter by name:

Exclusion Rule Type	UNR	Name	Score	Count Tx To One	Count Tx To Zero

Values Filter by name:

Exclusion Rule Type	UNR	Name	Score

Statement

Exclusion Rule Type	UNR	Index	Source Line	Overall Average Grade	Enclosing Entity	Source Code

FSMs Filter by name:

Exclusion Rule Type	UNR	Name	State Average Grade	Transition Average Grade	Arc Average Grade	Enclosing Entity	Source Code

States Filter by name:

Exclusion Rule Type	UNR	Name	Encoding	Score	Is Reset State	Source Code

Transitions

Exclusion Rule Type	UNR	Index	From State Name	To State Name	Score	Is Reset Trans

Arc Conditions

Exclusion Rule Type	Input Signal Names	UNR	Score

=============================

Cover Groups Filter by name:

Exclusion Rule Type	UNR	Name	Overall Average Grade	Overall Covered	Enclosing Entity	Source Code

Items Filter by name:

Exclusion Rule Type	UNR	Name	At Least	Overall Average Grade	Overall Covered	Source Code

Bins Filter by name:

Exclusion Rule Type	UNR	Name	Overall Average Grade	Overall Covered	Score	At Least	Source Code

Assertion

Exclusion Rule Type	UNR	Name	Overall Average Grade	Assertion Status Grade	Enclosing Entity	Source Code

Choose data.report file to upload from the [report directory]/report_data:

Filter by name:

Exclusion Rule Type	UNR	Name	Overall Average Grade	Overall Covered	Assertion Status Grade