ALERT_HANDLER Simulation Results

Thursday June 04 2020 01:33:53AM UTC

Testplan

Simulator: VCS

Milestone Name Tests Passing Total Pass Rate
V1 sanity alert_handler_sanity 50 50 100.00
V1 csr_hw_reset alert_handler_csr_hw_reset 50 50 100.00
V1 csr_rw alert_handler_csr_rw 50 50 100.00
V1 csr_bit_bash alert_handler_csr_bit_bash 50 50 100.00
V1 csr_aliasing alert_handler_csr_aliasing 50 50 100.00
V1 csr_mem_rw_with_rand_reset alert_handler_csr_mem_rw_with_rand_reset 50 50 100.00
V1 TOTAL 300 300 100.00
V2 esc_accum alert_handler_esc_alert_accum 50 50 100.00
V2 esc_timeout alert_handler_esc_intr_timeout 50 50 100.00
V2 entropy alert_handler_entropy 50 50 100.00
V2 sig_int_fail alert_handler_sig_int_fail 50 50 100.00
V2 ping_rsp_fail alert_handler_ping_rsp_fail 49 50 98.00
V2 clk_skew alert_handler_sanity 50 50 100.00
V2 random_alerts alert_handler_random_alerts 50 50 100.00
V2 random_classes alert_handler_random_classes 50 50 100.00
V2 stress_all alert_handler_stress_all 50 50 100.00
V2 intr_test alert_handler_intr_test 50 50 100.00
V2 enable_reg alert_handler_csr_rw 50 50 100.00
alert_handler_csr_bit_bash 50 50 100.00
alert_handler_csr_aliasing 50 50 100.00
V2 stress_all_with_rand_reset alert_handler_stress_all_with_rand_reset 99 100 99.00
V2 oob_addr_access alert_handler_tl_errors 20 20 100.00
V2 illegal_access alert_handler_tl_errors 20 20 100.00
V2 outstanding_access alert_handler_csr_hw_reset 50 50 100.00
alert_handler_csr_rw 50 50 100.00
alert_handler_csr_aliasing 50 50 100.00
alert_handler_same_csr_outstanding 50 50 100.00
V2 partial_access alert_handler_csr_hw_reset 50 50 100.00
alert_handler_csr_rw 50 50 100.00
alert_handler_csr_aliasing 50 50 100.00
V2 TOTAL 1138 1140 99.82
TOTAL 1438 1440 99.86

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.12 99.96 95.63 76.60 83.89 98.97 97.47 99.30

List of Failures

TEST: alert_handler_ping_rsp_fail, SEED: 2975680128
LOG: $scratch_path/13.alert_handler_ping_rsp_fail/out/run.log

UVM_ERROR @ 6788320433750 ps: (alert_handler_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (10 [0xa] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 6788320433750 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: alert_handler_stress_all_with_rand_reset, SEED: 226543350
LOG: $scratch_path/8.alert_handler_stress_all_with_rand_reset/out/run.log

UVM_ERROR @ 499465646513 ps: (alert_handler_scoreboard.sv:326) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (206 [0xce] vs 207 [0xcf]) reg name: ral.classc_esc_cnt
UVM_INFO @ 499465646513 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

Past Results