V1 |
sanity |
alert_handler_sanity |
50 |
50 |
100.00 |
V1 |
csr_hw_reset |
alert_handler_csr_hw_reset |
50 |
50 |
100.00 |
V1 |
csr_rw |
alert_handler_csr_rw |
50 |
50 |
100.00 |
V1 |
csr_bit_bash |
alert_handler_csr_bit_bash |
50 |
50 |
100.00 |
V1 |
csr_aliasing |
alert_handler_csr_aliasing |
50 |
50 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
alert_handler_csr_mem_rw_with_rand_reset |
50 |
50 |
100.00 |
V1 |
|
TOTAL |
300 |
300 |
100.00 |
V2 |
esc_accum |
alert_handler_esc_alert_accum |
50 |
50 |
100.00 |
V2 |
esc_timeout |
alert_handler_esc_intr_timeout |
50 |
50 |
100.00 |
V2 |
entropy |
alert_handler_entropy |
50 |
50 |
100.00 |
V2 |
sig_int_fail |
alert_handler_sig_int_fail |
50 |
50 |
100.00 |
V2 |
ping_rsp_fail |
alert_handler_ping_rsp_fail |
50 |
50 |
100.00 |
V2 |
clk_skew |
alert_handler_sanity |
50 |
50 |
100.00 |
V2 |
random_alerts |
alert_handler_random_alerts |
50 |
50 |
100.00 |
V2 |
random_classes |
alert_handler_random_classes |
50 |
50 |
100.00 |
V2 |
stress_all |
alert_handler_stress_all |
50 |
50 |
100.00 |
V2 |
intr_test |
alert_handler_intr_test |
50 |
50 |
100.00 |
V2 |
enable_reg |
alert_handler_csr_rw |
50 |
50 |
100.00 |
|
|
alert_handler_csr_bit_bash |
50 |
50 |
100.00 |
|
|
alert_handler_csr_aliasing |
50 |
50 |
100.00 |
V2 |
stress_all_with_rand_reset |
alert_handler_stress_all_with_rand_reset |
100 |
100 |
100.00 |
V2 |
oob_addr_access |
alert_handler_tl_errors |
20 |
20 |
100.00 |
V2 |
illegal_access |
alert_handler_tl_errors |
20 |
20 |
100.00 |
V2 |
outstanding_access |
alert_handler_csr_hw_reset |
50 |
50 |
100.00 |
|
|
alert_handler_csr_rw |
50 |
50 |
100.00 |
|
|
alert_handler_csr_aliasing |
50 |
50 |
100.00 |
|
|
alert_handler_same_csr_outstanding |
50 |
50 |
100.00 |
V2 |
partial_access |
alert_handler_csr_hw_reset |
50 |
50 |
100.00 |
|
|
alert_handler_csr_rw |
50 |
50 |
100.00 |
|
|
alert_handler_csr_aliasing |
50 |
50 |
100.00 |
V2 |
|
TOTAL |
1140 |
1140 |
100.00 |
|
|
TOTAL |
1440 |
1440 |
100.00 |