ALERT_HANDLER Simulation Results

Tuesday June 16 2020 02:26:34AM UTC

Testplan

Simulator: VCS

Milestone Name Tests Passing Total Pass Rate
V1 sanity alert_handler_sanity 50 50 100.00
V1 csr_hw_reset alert_handler_csr_hw_reset 50 50 100.00
V1 csr_rw alert_handler_csr_rw 50 50 100.00
V1 csr_bit_bash alert_handler_csr_bit_bash 50 50 100.00
V1 csr_aliasing alert_handler_csr_aliasing 50 50 100.00
V1 csr_mem_rw_with_rand_reset alert_handler_csr_mem_rw_with_rand_reset 50 50 100.00
V1 TOTAL 300 300 100.00
V2 esc_accum alert_handler_esc_alert_accum 50 50 100.00
V2 esc_timeout alert_handler_esc_intr_timeout 50 50 100.00
V2 entropy alert_handler_entropy 50 50 100.00
V2 sig_int_fail alert_handler_sig_int_fail 50 50 100.00
V2 ping_rsp_fail alert_handler_ping_rsp_fail 50 50 100.00
V2 clk_skew alert_handler_sanity 50 50 100.00
V2 random_alerts alert_handler_random_alerts 50 50 100.00
V2 random_classes alert_handler_random_classes 50 50 100.00
V2 stress_all alert_handler_stress_all 49 50 98.00
V2 intr_test alert_handler_intr_test 50 50 100.00
V2 enable_reg alert_handler_csr_rw 50 50 100.00
alert_handler_csr_bit_bash 50 50 100.00
alert_handler_csr_aliasing 50 50 100.00
V2 stress_all_with_rand_reset alert_handler_stress_all_with_rand_reset 100 100 100.00
V2 oob_addr_access alert_handler_tl_errors 20 20 100.00
V2 illegal_access alert_handler_tl_errors 20 20 100.00
V2 outstanding_access alert_handler_csr_hw_reset 50 50 100.00
alert_handler_csr_rw 50 50 100.00
alert_handler_csr_aliasing 50 50 100.00
alert_handler_same_csr_outstanding 50 50 100.00
V2 partial_access alert_handler_csr_hw_reset 50 50 100.00
alert_handler_csr_rw 50 50 100.00
alert_handler_csr_aliasing 50 50 100.00
V2 TOTAL 1139 1140 99.91
TOTAL 1439 1440 99.93

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.36 99.96 96.21 76.60 84.56 98.97 98.01 99.19

List of Failures

TEST: alert_handler_stress_all, SEED: 4235239873
LOG: $scratch_path/6.alert_handler_stress_all/out/run.log

UVM_ERROR @ 3439796100163 ps: (alert_handler_scoreboard.sv:324) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (10 [0xa] vs 9 [0x9]) reg name: intr_state
UVM_INFO @ 3439796100163 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

Past Results