ALERT_HANDLER Simulation Results

Wednesday June 17 2020 01:17:48AM UTC

Testplan

Simulator: VCS

Milestone Name Tests Passing Total Pass Rate
V1 sanity alert_handler_sanity 50 50 100.00
V1 csr_hw_reset alert_handler_csr_hw_reset 50 50 100.00
V1 csr_rw alert_handler_csr_rw 50 50 100.00
V1 csr_bit_bash alert_handler_csr_bit_bash 50 50 100.00
V1 csr_aliasing alert_handler_csr_aliasing 50 50 100.00
V1 csr_mem_rw_with_rand_reset alert_handler_csr_mem_rw_with_rand_reset 50 50 100.00
V1 TOTAL 300 300 100.00
V2 esc_accum alert_handler_esc_alert_accum 50 50 100.00
V2 esc_timeout alert_handler_esc_intr_timeout 50 50 100.00
V2 entropy alert_handler_entropy 50 50 100.00
V2 sig_int_fail alert_handler_sig_int_fail 50 50 100.00
V2 ping_rsp_fail alert_handler_ping_rsp_fail 46 50 92.00
V2 clk_skew alert_handler_sanity 50 50 100.00
V2 random_alerts alert_handler_random_alerts 50 50 100.00
V2 random_classes alert_handler_random_classes 50 50 100.00
V2 stress_all alert_handler_stress_all 49 50 98.00
V2 intr_test alert_handler_intr_test 50 50 100.00
V2 enable_reg alert_handler_csr_rw 50 50 100.00
alert_handler_csr_bit_bash 50 50 100.00
alert_handler_csr_aliasing 50 50 100.00
V2 stress_all_with_rand_reset alert_handler_stress_all_with_rand_reset 99 100 99.00
V2 oob_addr_access alert_handler_tl_errors 20 20 100.00
V2 illegal_access alert_handler_tl_errors 20 20 100.00
V2 outstanding_access alert_handler_csr_hw_reset 50 50 100.00
alert_handler_csr_rw 50 50 100.00
alert_handler_csr_aliasing 50 50 100.00
alert_handler_same_csr_outstanding 50 50 100.00
V2 partial_access alert_handler_csr_hw_reset 50 50 100.00
alert_handler_csr_rw 50 50 100.00
alert_handler_csr_aliasing 50 50 100.00
V2 TOTAL 1134 1140 99.47
TOTAL 1434 1440 99.58

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.09 99.96 96.06 76.46 83.22 98.97 97.47 99.46

List of Failures

TEST: alert_handler_ping_rsp_fail, SEED: 3511834845
LOG: $scratch_path/20.alert_handler_ping_rsp_fail/out/run.log

UVM_ERROR @ 2213802298512 ps: (alert_handler_scoreboard.sv:326) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (8 [0x8] vs 0 [0x0]) reg name: intr_state
UVM_INFO @ 2213802298512 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: alert_handler_stress_all, SEED: 34680238
LOG: $scratch_path/21.alert_handler_stress_all/out/run.log

UVM_ERROR @ 6728584379462 ps: (alert_handler_scoreboard.sv:326) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (1 [0x1] vs 0 [0x0]) reg name: intr_state
UVM_INFO @ 6728584379462 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: alert_handler_ping_rsp_fail, SEED: 1657330289
LOG: $scratch_path/28.alert_handler_ping_rsp_fail/out/run.log

UVM_ERROR @ 75943908937 ps: (alert_handler_scoreboard.sv:330) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: ral.classc_state
UVM_INFO @ 75943908937 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: alert_handler_ping_rsp_fail, SEED: 3945163010
LOG: $scratch_path/31.alert_handler_ping_rsp_fail/out/run.log

UVM_ERROR @ 885266396045 ps: (alert_handler_scoreboard.sv:330) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ral.classd_state
UVM_INFO @ 885266396045 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: alert_handler_ping_rsp_fail, SEED: 2884693745
LOG: $scratch_path/46.alert_handler_ping_rsp_fail/out/run.log

UVM_ERROR @ 2144319234912 ps: (alert_handler_scoreboard.sv:330) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: ral.classc_state
UVM_INFO @ 2144319234912 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: alert_handler_stress_all_with_rand_reset, SEED: 509774014
LOG: $scratch_path/55.alert_handler_stress_all_with_rand_reset/out/run.log

UVM_ERROR @ 167764445187 ps: (alert_handler_scoreboard.sv:326) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (2 [0x2] vs 3 [0x3]) reg name: intr_state
UVM_INFO @ 167764445187 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

Past Results