ALERT_HANDLER Simulation Results

Thursday June 18 2020 04:20:01PM UTC

Testplan

Simulator: VCS

Milestone	Name	Tests	Passing	Total	Pass Rate
V1	sanity	alert_handler_sanity	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	50	50	100.00
V1	csr_rw	alert_handler_csr_rw	50	50	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	50	50	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	50	50	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	49	50	98.00
V1		TOTAL	299	300	99.67
V2	esc_accum	alert_handler_esc_alert_accum	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	50	50	100.00
V2	entropy	alert_handler_entropy	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	50	50	100.00
V2	ping_rsp_fail	alert_handler_ping_rsp_fail	48	50	96.00
V2	clk_skew	alert_handler_sanity	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	50	50	100.00
V2	random_classes	alert_handler_random_classes	50	50	100.00
V2	stress_all	alert_handler_stress_all	50	50	100.00
V2	intr_test	alert_handler_intr_test	50	50	100.00
V2	enable_reg	alert_handler_csr_rw	50	50	100.00
		alert_handler_csr_bit_bash	50	50	100.00
		alert_handler_csr_aliasing	50	50	100.00
V2	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	100	100	100.00
V2	oob_addr_access	alert_handler_tl_errors	20	20	100.00
V2	illegal_access	alert_handler_tl_errors	20	20	100.00
V2	outstanding_access	alert_handler_csr_hw_reset	50	50	100.00
		alert_handler_csr_rw	50	50	100.00
		alert_handler_csr_aliasing	50	50	100.00
		alert_handler_same_csr_outstanding	50	50	100.00
V2	partial_access	alert_handler_csr_hw_reset	50	50	100.00
		alert_handler_csr_rw	50	50	100.00
		alert_handler_csr_aliasing	50	50	100.00
V2		TOTAL	1138	1140	99.82
		TOTAL	1437	1440	99.79

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.43	99.96	95.77	76.60	86.58	98.97	97.29	98.81

List of Failures

TEST: alert_handler_csr_mem_rw_with_rand_reset, SEED: 1378462616
LOG: $scratch_path/10.alert_handler_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 174221622222 ps: (cip_base_vseq.sv:349) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed data == 0 (1 [0x1] vs 0 [0x0]) 
UVM_INFO @ 174221622222 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: alert_handler_ping_rsp_fail, SEED: 4097486932
LOG: $scratch_path/39.alert_handler_ping_rsp_fail/out/run.log

UVM_ERROR @ 673950083762 ps: (alert_handler_scoreboard.sv:330) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (43 [0x2b] vs 44 [0x2c]) reg name: ral.classc_accum_cnt
UVM_INFO @ 673950083762 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: alert_handler_ping_rsp_fail, SEED: 671265959
LOG: $scratch_path/49.alert_handler_ping_rsp_fail/out/run.log

UVM_ERROR @ 575040082367 ps: (alert_handler_scoreboard.sv:330) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (39 [0x27] vs 41 [0x29]) reg name: ral.classa_esc_cnt
UVM_INFO @ 575040082367 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!