Group : intr_pins_cg::SHAPE{(num_interrupts - 1)=3}
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Summary for Group intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group intr_pins_cg::SHAPE{(num_interrupts - 1)=3}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 4 0 4 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group intr_pins_cg::SHAPE{(num_interrupts - 1)=3}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 16 0 16 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUS
all_pins_0 18432803 1
all_pins_1 18432803 1
all_pins_2 18432803 1
all_pins_3 18432803 1



Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTSTATUS
values_0 68460152 1
values_1 5271060 1
transitions:0->1 4757165 1
transitions:1->0 4757299 1



Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTSTATUS
all_pins_0 values_0 16809092 1
all_pins_0 values_1 1623711 1
all_pins_0 transitions:0->1 1610704 1
all_pins_0 transitions:1->0 1122924 1
all_pins_1 values_0 17278634 1
all_pins_1 values_1 1154169 1
all_pins_1 transitions:0->1 1012861 1
all_pins_1 transitions:1->0 1482403 1
all_pins_2 values_0 17075420 1
all_pins_2 values_1 1357383 1
all_pins_2 transitions:0->1 1185801 1
all_pins_2 transitions:1->0 982587 1
all_pins_3 values_0 17297006 1
all_pins_3 values_1 1135797 1
all_pins_3 transitions:0->1 947799 1
all_pins_3 transitions:1->0 1169385 1

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