Design subhierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

Go up
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alerts[0].i_alert_receiver 92.22 100.00 100.00 66.67 94.44 100.00
i_decode_alert 100.00 100.00 100.00 100.00 100.00
gen_alerts[1].i_alert_receiver 92.22 100.00 100.00 66.67 94.44 100.00
i_decode_alert 100.00 100.00 100.00 100.00 100.00
gen_alerts[2].i_alert_receiver 92.22 100.00 100.00 66.67 94.44 100.00
i_decode_alert 100.00 100.00 100.00 100.00 100.00
gen_alerts[3].i_alert_receiver 92.22 100.00 100.00 66.67 94.44 100.00
i_decode_alert 100.00 100.00 100.00 100.00 100.00
gen_classes[0].i_accu 100.00 100.00 100.00 100.00 100.00
gen_classes[0].i_esc_timer 95.42 100.00 80.95 100.00 96.15 100.00
gen_classes[1].i_accu 100.00 100.00 100.00 100.00 100.00
gen_classes[1].i_esc_timer 95.42 100.00 80.95 100.00 96.15 100.00
gen_classes[2].i_accu 100.00 100.00 100.00 100.00 100.00
gen_classes[2].i_esc_timer 94.47 100.00 76.19 100.00 96.15 100.00
gen_classes[3].i_accu 100.00 100.00 100.00 100.00 100.00
gen_classes[3].i_esc_timer 95.42 100.00 80.95 100.00 96.15 100.00
gen_esc_sev[0].i_esc_sender 91.56 100.00 93.33 76.47 100.00 88.00
i_decode_resp 100.00 100.00 100.00 100.00 100.00
gen_esc_sev[1].i_esc_sender 91.56 100.00 93.33 76.47 100.00 88.00
i_decode_resp 100.00 100.00 100.00 100.00 100.00
gen_esc_sev[2].i_esc_sender 91.56 100.00 93.33 76.47 100.00 88.00
i_decode_resp 100.00 100.00 100.00 100.00 100.00
gen_esc_sev[3].i_esc_sender 92.89 100.00 100.00 76.47 100.00 88.00
i_decode_resp 100.00 100.00 100.00 100.00 100.00
i_class 100.00 100.00
i_ping_timer 82.89 99.07 60.87 80.00 80.77 93.75
i_prim_lfsr 77.54 95.65 55.00 66.67 92.86
i_reg_wrap 100.00 100.00 100.00 100.00 100.00
i_irq_classa 100.00 100.00
i_irq_classb 100.00 100.00
i_irq_classc 100.00 100.00
i_irq_classd 100.00 100.00
u_reg 100.00 100.00 100.00 100.00 100.00
u_alert_cause_a0 100.00 100.00 100.00
u_alert_cause_a1 100.00 100.00 100.00
u_alert_cause_a2 100.00 100.00 100.00
u_alert_cause_a3 100.00 100.00 100.00
u_alert_class_class_a0 100.00 100.00 100.00 100.00
u_alert_class_class_a1 100.00 100.00 100.00 100.00
u_alert_class_class_a2 100.00 100.00 100.00 100.00
u_alert_class_class_a3 100.00 100.00 100.00 100.00
u_alert_en_en_a0 100.00 100.00 100.00 100.00
u_alert_en_en_a1 100.00 100.00 100.00 100.00
u_alert_en_en_a2 100.00 100.00 100.00 100.00
u_alert_en_en_a3 100.00 100.00 100.00 100.00
u_classa_accum_cnt 100.00 100.00
u_classa_accum_thresh 100.00 100.00 100.00 100.00
u_classa_clr 100.00 100.00 100.00 100.00
u_classa_clren 100.00 100.00 100.00
u_classa_ctrl_en 100.00 100.00 100.00 100.00
u_classa_ctrl_en_e0 100.00 100.00 100.00 100.00
u_classa_ctrl_en_e1 100.00 100.00 100.00 100.00
u_classa_ctrl_en_e2 100.00 100.00 100.00 100.00
u_classa_ctrl_en_e3 100.00 100.00 100.00 100.00
u_classa_ctrl_lock 100.00 100.00 100.00 100.00
u_classa_ctrl_map_e0 100.00 100.00 100.00 100.00
u_classa_ctrl_map_e1 100.00 100.00 100.00 100.00
u_classa_ctrl_map_e2 100.00 100.00 100.00 100.00
u_classa_ctrl_map_e3 100.00 100.00 100.00 100.00
u_classa_esc_cnt 100.00 100.00
u_classa_phase0_cyc 100.00 100.00 100.00 100.00
u_classa_phase1_cyc 100.00 100.00 100.00 100.00
u_classa_phase2_cyc 100.00 100.00 100.00 100.00
u_classa_phase3_cyc 100.00 100.00 100.00 100.00
u_classa_state 100.00 100.00
u_classa_timeout_cyc 100.00 100.00 100.00 100.00
u_classb_accum_cnt 100.00 100.00
u_classb_accum_thresh 100.00 100.00 100.00 100.00
u_classb_clr 100.00 100.00 100.00 100.00
u_classb_clren 100.00 100.00 100.00
u_classb_ctrl_en 100.00 100.00 100.00 100.00
u_classb_ctrl_en_e0 100.00 100.00 100.00 100.00
u_classb_ctrl_en_e1 100.00 100.00 100.00 100.00
u_classb_ctrl_en_e2 100.00 100.00 100.00 100.00
u_classb_ctrl_en_e3 100.00 100.00 100.00 100.00
u_classb_ctrl_lock 100.00 100.00 100.00 100.00
u_classb_ctrl_map_e0 100.00 100.00 100.00 100.00
u_classb_ctrl_map_e1 100.00 100.00 100.00 100.00
u_classb_ctrl_map_e2 100.00 100.00 100.00 100.00
u_classb_ctrl_map_e3 100.00 100.00 100.00 100.00
u_classb_esc_cnt 100.00 100.00
u_classb_phase0_cyc 100.00 100.00 100.00 100.00
u_classb_phase1_cyc 100.00 100.00 100.00 100.00
u_classb_phase2_cyc 100.00 100.00 100.00 100.00
u_classb_phase3_cyc 100.00 100.00 100.00 100.00
u_classb_state 100.00 100.00
u_classb_timeout_cyc 100.00 100.00 100.00 100.00
u_classc_accum_cnt 100.00 100.00
u_classc_accum_thresh 100.00 100.00 100.00 100.00
u_classc_clr 100.00 100.00 100.00 100.00
u_classc_clren 100.00 100.00 100.00
u_classc_ctrl_en 100.00 100.00 100.00 100.00
u_classc_ctrl_en_e0 100.00 100.00 100.00 100.00
u_classc_ctrl_en_e1 100.00 100.00 100.00 100.00
u_classc_ctrl_en_e2 100.00 100.00 100.00 100.00
u_classc_ctrl_en_e3 100.00 100.00 100.00 100.00
u_classc_ctrl_lock 100.00 100.00 100.00 100.00
u_classc_ctrl_map_e0 100.00 100.00 100.00 100.00
u_classc_ctrl_map_e1 100.00 100.00 100.00 100.00
u_classc_ctrl_map_e2 100.00 100.00 100.00 100.00
u_classc_ctrl_map_e3 100.00 100.00 100.00 100.00
u_classc_esc_cnt 100.00 100.00
u_classc_phase0_cyc 100.00 100.00 100.00 100.00
u_classc_phase1_cyc 100.00 100.00 100.00 100.00
u_classc_phase2_cyc 100.00 100.00 100.00 100.00
u_classc_phase3_cyc 100.00 100.00 100.00 100.00
u_classc_state 100.00 100.00
u_classc_timeout_cyc 100.00 100.00 100.00 100.00
u_classd_accum_cnt 100.00 100.00
u_classd_accum_thresh 100.00 100.00 100.00 100.00
u_classd_clr 100.00 100.00 100.00 100.00
u_classd_clren 100.00 100.00 100.00
u_classd_ctrl_en 100.00 100.00 100.00 100.00
u_classd_ctrl_en_e0 100.00 100.00 100.00 100.00
u_classd_ctrl_en_e1 100.00 100.00 100.00 100.00
u_classd_ctrl_en_e2 100.00 100.00 100.00 100.00
u_classd_ctrl_en_e3 100.00 100.00 100.00 100.00
u_classd_ctrl_lock 100.00 100.00 100.00 100.00
u_classd_ctrl_map_e0 100.00 100.00 100.00 100.00
u_classd_ctrl_map_e1 100.00 100.00 100.00 100.00
u_classd_ctrl_map_e2 100.00 100.00 100.00 100.00
u_classd_ctrl_map_e3 100.00 100.00 100.00 100.00
u_classd_esc_cnt 100.00 100.00
u_classd_phase0_cyc 100.00 100.00 100.00 100.00
u_classd_phase1_cyc 100.00 100.00 100.00 100.00
u_classd_phase2_cyc 100.00 100.00 100.00 100.00
u_classd_phase3_cyc 100.00 100.00 100.00 100.00
u_classd_state 100.00 100.00
u_classd_timeout_cyc 100.00 100.00 100.00 100.00
u_intr_enable_classa 100.00 100.00 100.00 100.00
u_intr_enable_classb 100.00 100.00 100.00 100.00
u_intr_enable_classc 100.00 100.00 100.00 100.00
u_intr_enable_classd 100.00 100.00 100.00 100.00
u_intr_state_classa 100.00 100.00 100.00
u_intr_state_classb 100.00 100.00 100.00
u_intr_state_classc 100.00 100.00 100.00
u_intr_state_classd 100.00 100.00 100.00
u_intr_test_classa 100.00 100.00
u_intr_test_classb 100.00 100.00
u_intr_test_classc 100.00 100.00
u_intr_test_classd 100.00 100.00
u_loc_alert_cause_la0 100.00 100.00 100.00
u_loc_alert_cause_la1 100.00 100.00 100.00
u_loc_alert_cause_la2 100.00 100.00 100.00
u_loc_alert_cause_la3 100.00 100.00 100.00
u_loc_alert_class_class_la0 100.00 100.00 100.00 100.00
u_loc_alert_class_class_la1 100.00 100.00 100.00 100.00
u_loc_alert_class_class_la2 100.00 100.00 100.00 100.00
u_loc_alert_class_class_la3 100.00 100.00 100.00 100.00
u_loc_alert_en_en_la0 100.00 100.00 100.00 100.00
u_loc_alert_en_en_la1 100.00 100.00 100.00 100.00
u_loc_alert_en_en_la2 100.00 100.00 100.00 100.00
u_loc_alert_en_en_la3 100.00 100.00 100.00 100.00
u_ping_timeout_cyc 100.00 100.00 100.00 100.00
u_reg_if 100.00 100.00 100.00 100.00 100.00
u_err 100.00 100.00 100.00 100.00 100.00
u_regen 100.00 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%