Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : tlul_assert
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/edascratch/chencindy-opentitan/nightly_openTitan/alert_handler.sim.vcs/master/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.tlul_assert_device 100.00 100.00 100.00 100.00



Module Instance : tb.dut.tlul_assert_device

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 100.00 76.60 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_assert
Line No.TotalCoveredPercent
TOTAL1515100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS641111100.00
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300
INITIAL26300

52 logic [63:0] a_data, d_data; 53 1/1 assign a_mask = 8'(h2d.a_mask); 54 1/1 assign a_data = 64'(h2d.a_data); 55 1/1 assign d_mask = 8'(pend_req[d2h.d_source].mask); 56 1/1 assign d_data = 64'(d2h.d_data); 57 58 //////////////////////////////////// 59 // keep track of pending requests // 60 //////////////////////////////////// 61 62 // use negedge clk to avoid possible race conditions 63 always_ff @(negedge clk_i or negedge rst_ni) begin 64 1/1 if (!rst_ni) begin 65 1/1 pend_req <= '0; 66 end else begin 67 1/1 if (h2d.a_valid) begin 68 // store each request in pend_req array (we use blocking statements below so 69 // that we can handle the case where request and response for the same 70 // source-ID happen in the same cycle) 71 1/1 if (d2h.a_ready) begin 72 1/1 pend_req[h2d.a_source].pend <= 1; 73 1/1 pend_req[h2d.a_source].opcode <= h2d.a_opcode; 74 1/1 pend_req[h2d.a_source].size <= h2d.a_size; 75 1/1 pend_req[h2d.a_source].mask <= h2d.a_mask; 76 end MISSING_ELSE 77 end // h2d.a_valid MISSING_ELSE 78 79 1/1 if (d2h.d_valid) begin 80 // update pend_req array 81 1/1 if (h2d.d_ready) begin 82 1/1 pend_req[d2h.d_source].pend <= 0; 83 end MISSING_ELSE 84 end //d2h.d_valid MISSING_ELSE

Branch Coverage for Module : tlul_assert
Line No.TotalCoveredPercent
Branches 7 7 100.00
IF 64 7 7 100.00


64 if (!rst_ni) begin -1- 65 pend_req <= '0; ==> 66 end else begin 67 if (h2d.a_valid) begin -2- 68 // store each request in pend_req array (we use blocking statements below so 69 // that we can handle the case where request and response for the same 70 // source-ID happen in the same cycle) 71 if (d2h.a_ready) begin -3- 72 pend_req[h2d.a_source].pend <= 1; ==> 73 pend_req[h2d.a_source].opcode <= h2d.a_opcode; 74 pend_req[h2d.a_source].size <= h2d.a_size; 75 pend_req[h2d.a_source].mask <= h2d.a_mask; 76 end MISSING_ELSE ==> 77 end // h2d.a_valid MISSING_ELSE ==> 78 79 if (d2h.d_valid) begin -4- 80 // update pend_req array 81 if (h2d.d_ready) begin -5- 82 pend_req[d2h.d_source].pend <= 0; ==> 83 end MISSING_ELSE ==> 84 end //d2h.d_valid MISSING_ELSE ==>

Branches:
-1--2--3--4--5-Status
1 - - - - Covered
0 1 1 - - Covered
0 1 0 - - Covered
0 0 - - - Covered
0 - - 1 1 Covered
0 - - 1 0 Covered
0 - - 0 - Covered


Assert Coverage for Module : tlul_assert
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 276 276 100.00 276 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 276 276 100.00 276 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
aKnown_A 2147483647 613492857 0 0
aKnown_AKnownEnable 2147483647 2147483647 0 0
aReadyKnown_A 2147483647 2147483647 0 0
dKnown_A 2147483647 586278877 0 0
dKnown_AKnownEnable 2147483647 2147483647 0 0
dReadyKnown_A 2147483647 2147483647 0 0
gen_assert_final[0].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[100].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[101].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[102].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[103].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[104].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[105].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[106].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[107].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[108].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[109].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[10].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[110].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[111].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[112].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[113].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[114].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[115].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[116].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[117].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[118].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[119].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[11].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[120].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[121].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[122].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[123].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[124].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[125].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[126].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[127].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[128].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[129].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[12].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[130].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[131].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[132].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[133].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[134].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[135].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[136].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[137].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[138].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[139].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[13].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[140].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[141].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[142].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[143].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[144].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[145].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[146].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[147].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[148].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[149].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[14].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[150].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[151].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[152].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[153].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[154].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[155].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[156].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[157].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[158].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[159].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[15].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[160].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[161].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[162].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[163].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[164].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[165].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[166].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[167].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[168].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[169].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[16].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[170].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[171].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[172].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[173].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[174].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[175].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[176].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[177].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[178].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[179].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[17].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[180].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[181].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[182].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[183].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[184].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[185].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[186].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[187].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[188].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[189].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[18].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[190].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[191].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[192].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[193].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[194].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[195].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[196].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[197].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[198].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[199].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[19].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[1].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[200].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[201].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[202].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[203].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[204].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[205].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[206].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[207].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[208].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[209].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[20].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[210].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[211].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[212].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[213].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[214].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[215].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[216].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[217].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[218].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[219].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[21].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[220].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[221].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[222].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[223].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[224].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[225].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[226].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[227].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[228].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[229].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[22].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[230].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[231].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[232].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[233].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[234].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[235].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[236].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[237].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[238].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[239].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[23].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[240].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[241].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[242].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[243].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[244].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[245].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[246].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[247].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[248].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[249].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[24].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[250].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[251].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[252].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[253].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[254].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[255].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[25].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[26].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[27].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[28].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[29].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[2].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[30].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[31].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[32].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[33].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[34].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[35].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[36].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[37].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[38].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[39].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[3].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[40].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[41].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[42].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[43].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[44].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[45].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[46].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 919 919 0 0
gen_device.aDataKnown_M 2147483647 395071265 0 0
gen_device.addrSizeAligned_M 2147483647 434917201 0 0
gen_device.contigMask_M 2147483647 307259111 0 0
gen_device.dDataKnown_A 2147483647 180836878 0 0
gen_device.legalAOpcode_M 2147483647 434917201 0 0
gen_device.legalAParam_M 2147483647 613492910 0 0
gen_device.legalDParam_A 2147483647 586278919 0 0
gen_device.pendingReqPerSrc_M 2147483647 613492910 0 0
gen_device.respMustHaveReq_A 2147483647 586278919 0 0
gen_device.respOpcode_A 2147483647 586278919 0 0
gen_device.respSzEqReqSz_A 2147483647 586278919 0 0
gen_device.sizeGTEMask_M 2147483647 434917201 0 0
gen_device.sizeMatchesMask_M 2147483647 434917201 0 0
p_dbw.TlDbw_A 919 919 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%