Module Definition
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Module : prim_subreg
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/edascratch/chencindy-opentitan/nightly_openTitan/alert_handler.sim.vcs/master/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_subreg.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.i_reg_wrap.u_reg.u_intr_state_classa 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_state_classb 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_state_classc 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_state_classd 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_enable_classa 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_enable_classb 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_enable_classc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_enable_classd 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_regen 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_ping_timeout_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_en_en_a0 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_en_en_a1 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_en_en_a2 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_en_en_a3 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_class_class_a0 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_class_class_a1 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_class_class_a2 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_class_class_a3 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_cause_a0 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_cause_a1 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_cause_a2 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_cause_a3 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_en_en_la0 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_en_en_la1 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_en_en_la2 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_en_en_la3 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_class_class_la0 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_class_class_la1 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_class_class_la2 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_class_class_la3 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_cause_la0 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_cause_la1 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_cause_la2 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_cause_la3 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_lock 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en_e0 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en_e1 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en_e2 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en_e3 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_map_e0 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_map_e1 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_map_e2 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_map_e3 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_clren 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_clr 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_accum_thresh 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_timeout_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_phase0_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_phase1_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_phase2_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_phase3_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_lock 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en_e0 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en_e1 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en_e2 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en_e3 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_map_e0 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_map_e1 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_map_e2 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_map_e3 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_clren 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_clr 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_accum_thresh 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_timeout_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_phase0_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_phase1_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_phase2_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_phase3_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_lock 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en_e0 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en_e1 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en_e2 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en_e3 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_map_e0 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_map_e1 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_map_e2 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_map_e3 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_clren 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_clr 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_accum_thresh 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_timeout_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_phase0_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_phase1_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_phase2_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_phase3_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_lock 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en_e0 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en_e1 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en_e2 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en_e3 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_map_e0 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_map_e1 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_map_e2 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_map_e3 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_clren 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_clr 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_accum_thresh 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_timeout_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_phase0_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_phase1_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_phase2_cyc 100.00 100.00 100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_phase3_cyc 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg ( parameter DW=1,SWACCESS="W1C",RESVAL )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_state_classa

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_state_classb

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_state_classc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_state_classd

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_regen

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_cause_a0

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_cause_a1

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_cause_a2

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_cause_a3

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_cause_la0

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_cause_la1

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_cause_la2

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_cause_la3

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_clren

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_clren

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_clren

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_clren

Line No.TotalCoveredPercent
TOTAL1010100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5111100.00
ALWAYS6633100.00
ALWAYS7144100.00
CONT_ASSIGN7411100.00

49 // If both try to set/clr at the same bit pos, SW wins. 50 1/1 assign wr_en = we | de ; 51 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1); 52 end else if (SWACCESS == "W0C") begin : gen_w0c 53 assign wr_en = we | de ; 54 assign wr_data = (de ? d : q) & (we ? wd : '1); 55 end else if (SWACCESS == "RC") begin : gen_rc 56 // This swtype is not recommended but exists for compatibility. 57 // WARN: we signal is actually read signal not write enable. 58 assign wr_en = we | de ; 59 assign wr_data = (de ? d : q) & (we ? '0 : '1); 60 end else begin : gen_hw 61 assign wr_en = de ; 62 assign wr_data = d ; 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 2/2 if (!rst_ni) qe <= 1'b0; 67 1/1 else qe <= we ; 68 end 69 70 always_ff @(posedge clk_i or negedge rst_ni) begin 71 2/2 if (!rst_ni) q <= RESVAL ; 72 2/2 else if (wr_en) q <= wr_data; MISSING_ELSE 73 end 74 1/1 assign qs = q;

Line Coverage for Module : prim_subreg ( parameter DW=1,SWACCESS,RESVAL + DW=24,SWACCESS="RW",RESVAL=32 + DW=2,SWACCESS="RW",RESVAL + DW=16,SWACCESS="RW",RESVAL=0 + DW=32,SWACCESS="RW",RESVAL=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_enable_classa

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_enable_classb

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_enable_classc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_enable_classd

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_ping_timeout_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_en_en_a0

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_en_en_a1

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_en_en_a2

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_en_en_a3

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_class_class_a0

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_class_class_a1

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_class_class_a2

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_class_class_a3

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_en_en_la0

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_en_en_la1

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_en_en_la2

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_en_en_la3

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_class_class_la0

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_class_class_la1

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_class_class_la2

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_class_class_la3

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_lock

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en_e0

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en_e1

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en_e2

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en_e3

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_map_e0

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_map_e1

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_map_e2

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_map_e3

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_clr

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_accum_thresh

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_timeout_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_phase0_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_phase1_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_phase2_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_phase3_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_lock

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en_e0

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en_e1

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en_e2

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en_e3

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_map_e0

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_map_e1

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_map_e2

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_map_e3

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_clr

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_accum_thresh

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_timeout_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_phase0_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_phase1_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_phase2_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_phase3_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_lock

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en_e0

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en_e1

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en_e2

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en_e3

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_map_e0

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_map_e1

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_map_e2

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_map_e3

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_clr

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_accum_thresh

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_timeout_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_phase0_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_phase1_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_phase2_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_phase3_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_lock

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en_e0

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en_e1

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en_e2

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en_e3

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_map_e0

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_map_e1

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_map_e2

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_map_e3

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_clr

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_accum_thresh

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_timeout_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_phase0_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_phase1_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_phase2_cyc

SCORELINE
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_phase3_cyc

Line No.TotalCoveredPercent
TOTAL1010100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
ALWAYS6633100.00
ALWAYS7144100.00
CONT_ASSIGN7411100.00

33 if ((SWACCESS == "RW") || (SWACCESS == "WO")) begin : gen_w 34 1/1 assign wr_en = we | de ; 35 1/1 assign wr_data = (we == 1'b1) ? wd : d ; // SW higher priority 36 end else if (SWACCESS == "RO") begin : gen_ro 37 // Unused we, wd 38 assign wr_en = de ; 39 assign wr_data = d ; 40 end else if (SWACCESS == "W1S") begin : gen_w1s 41 // If SWACCESS is W1S, then assume hw tries to clear. 42 // So, give a chance HW to clear when SW tries to set. 43 // If both try to set/clr at the same bit pos, SW wins. 44 assign wr_en = we | de ; 45 assign wr_data = (de ? d : q) | (we ? wd : '0); 46 end else if (SWACCESS == "W1C") begin : gen_w1c 47 // If SWACCESS is W1C, then assume hw tries to set. 48 // So, give a chance HW to set when SW tries to clear. 49 // If both try to set/clr at the same bit pos, SW wins. 50 assign wr_en = we | de ; 51 assign wr_data = (de ? d : q) & (we ? ~wd : '1); 52 end else if (SWACCESS == "W0C") begin : gen_w0c 53 assign wr_en = we | de ; 54 assign wr_data = (de ? d : q) & (we ? wd : '1); 55 end else if (SWACCESS == "RC") begin : gen_rc 56 // This swtype is not recommended but exists for compatibility. 57 // WARN: we signal is actually read signal not write enable. 58 assign wr_en = we | de ; 59 assign wr_data = (de ? d : q) & (we ? '0 : '1); 60 end else begin : gen_hw 61 assign wr_en = de ; 62 assign wr_data = d ; 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 2/2 if (!rst_ni) qe <= 1'b0; 67 1/1 else qe <= we ; 68 end 69 70 always_ff @(posedge clk_i or negedge rst_ni) begin 71 2/2 if (!rst_ni) q <= RESVAL ; 72 2/2 else if (wr_en) q <= wr_data; MISSING_ELSE 73 end 74 1/1 assign qs = q;

Cond Coverage for Module : prim_subreg ( parameter DW=1,SWACCESS,RESVAL )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_enable_classa

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_enable_classb

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_enable_classc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_enable_classd

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_en_en_a0

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_en_en_a1

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_en_en_a2

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_en_en_a3

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_en_en_la0

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_en_en_la1

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_en_en_la2

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_en_en_la3

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_lock

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en_e0

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en_e1

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en_e2

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en_e3

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_clr

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_lock

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en_e0

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en_e1

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en_e2

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en_e3

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_clr

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_lock

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en_e0

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en_e1

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en_e2

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en_e3

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_clr

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_lock

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en_e0

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en_e1

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en_e2

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en_e3

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_clr

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       35
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-Status
0Covered
1Covered

Cond Coverage for Module : prim_subreg ( parameter DW=32,SWACCESS="RW",RESVAL=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_timeout_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_phase0_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_phase1_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_phase2_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_phase3_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_timeout_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_phase0_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_phase1_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_phase2_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_phase3_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_timeout_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_phase0_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_phase1_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_phase2_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_phase3_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_timeout_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_phase0_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_phase1_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_phase2_cyc

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_phase3_cyc

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       35
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-Status
0Covered
1Covered

Cond Coverage for Module : prim_subreg ( parameter DW=24,SWACCESS="RW",RESVAL=32 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_ping_timeout_cyc

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       35
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-Status
0Covered
1Covered

Cond Coverage for Module : prim_subreg ( parameter DW=2,SWACCESS="RW",RESVAL )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_class_class_a0

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_class_class_a1

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_class_class_a2

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_class_class_a3

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_class_class_la0

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_class_class_la1

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_class_class_la2

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_class_class_la3

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_map_e0

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_map_e1

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_map_e2

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_map_e3

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_map_e0

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_map_e1

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_map_e2

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_map_e3

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_map_e0

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_map_e1

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_map_e2

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_map_e3

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_map_e0

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_map_e1

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_map_e2

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_map_e3

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       35
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-Status
0Covered
1Covered

Cond Coverage for Module : prim_subreg ( parameter DW=16,SWACCESS="RW",RESVAL=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_accum_thresh

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_accum_thresh

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_accum_thresh

SCORECOND
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_accum_thresh

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       35
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-Status
0Covered
1Covered

Branch Coverage for Module : prim_subreg ( parameter DW=1,SWACCESS="W1C",RESVAL )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_state_classa

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_state_classb

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_state_classc

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_state_classd

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_regen

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_cause_a0

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_cause_a1

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_cause_a2

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_cause_a3

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_cause_la0

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_cause_la1

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_cause_la2

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_cause_la3

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_clren

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_clren

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_clren

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_clren

Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 66 2 2 100.00
IF 71 3 3 100.00


66 if (!rst_ni) qe <= 1'b0; -1- ==> 67 else qe <= we ; ==>

Branches:
-1-Status
1 Covered
0 Covered


71 if (!rst_ni) q <= RESVAL ; -1- ==> 72 else if (wr_en) q <= wr_data; -2- ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Covered
0 0 Covered


Branch Coverage for Module : prim_subreg ( parameter DW=1,SWACCESS,RESVAL + DW=24,SWACCESS="RW",RESVAL=32 + DW=2,SWACCESS="RW",RESVAL + DW=16,SWACCESS="RW",RESVAL=0 + DW=32,SWACCESS="RW",RESVAL=0 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_enable_classa

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_enable_classb

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_enable_classc

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_intr_enable_classd

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_en_en_a0

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_en_en_a1

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_en_en_a2

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_en_en_a3

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_en_en_la0

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_en_en_la1

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_en_en_la2

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_en_en_la3

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_lock

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en_e0

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en_e1

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en_e2

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_en_e3

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_clr

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_lock

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en_e0

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en_e1

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en_e2

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_en_e3

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_clr

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_lock

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en_e0

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en_e1

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en_e2

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_en_e3

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_clr

SCOREBRANCH
100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_lock

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tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en_e0

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tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en_e1

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tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en_e2

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_en_e3

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_clr

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_ping_timeout_cyc

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_alert_class_class_a0

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tb.dut.i_reg_wrap.u_reg.u_alert_class_class_a1

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tb.dut.i_reg_wrap.u_reg.u_alert_class_class_a2

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tb.dut.i_reg_wrap.u_reg.u_alert_class_class_a3

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_class_class_la0

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_class_class_la1

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tb.dut.i_reg_wrap.u_reg.u_loc_alert_class_class_la2

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_loc_alert_class_class_la3

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tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_map_e0

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tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_map_e1

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tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_map_e2

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tb.dut.i_reg_wrap.u_reg.u_classa_ctrl_map_e3

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tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_map_e0

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tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_map_e1

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tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_map_e2

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_ctrl_map_e3

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_map_e0

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tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_map_e1

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tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_map_e2

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_ctrl_map_e3

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tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_map_e0

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_map_e1

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_map_e2

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tb.dut.i_reg_wrap.u_reg.u_classd_ctrl_map_e3

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tb.dut.i_reg_wrap.u_reg.u_classa_accum_thresh

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tb.dut.i_reg_wrap.u_reg.u_classb_accum_thresh

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tb.dut.i_reg_wrap.u_reg.u_classc_accum_thresh

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tb.dut.i_reg_wrap.u_reg.u_classd_accum_thresh

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_timeout_cyc

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_phase0_cyc

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tb.dut.i_reg_wrap.u_reg.u_classa_phase1_cyc

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tb.dut.i_reg_wrap.u_reg.u_classa_phase2_cyc

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classa_phase3_cyc

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_timeout_cyc

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_phase0_cyc

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_phase1_cyc

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classb_phase2_cyc

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tb.dut.i_reg_wrap.u_reg.u_classb_phase3_cyc

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tb.dut.i_reg_wrap.u_reg.u_classc_timeout_cyc

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_phase0_cyc

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classc_phase1_cyc

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tb.dut.i_reg_wrap.u_reg.u_classc_phase2_cyc

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tb.dut.i_reg_wrap.u_reg.u_classc_phase3_cyc

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tb.dut.i_reg_wrap.u_reg.u_classd_timeout_cyc

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tb.dut.i_reg_wrap.u_reg.u_classd_phase0_cyc

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tb.dut.i_reg_wrap.u_reg.u_classd_phase1_cyc

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tb.dut.i_reg_wrap.u_reg.u_classd_phase2_cyc

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100.00 100.00
tb.dut.i_reg_wrap.u_reg.u_classd_phase3_cyc

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 35 2 2 100.00
IF 66 2 2 100.00
IF 71 3 3 100.00


35 assign wr_data = (we == 1'b1) ? wd : d ; // SW higher priority -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


66 if (!rst_ni) qe <= 1'b0; -1- ==> 67 else qe <= we ; ==>

Branches:
-1-Status
1 Covered
0 Covered


71 if (!rst_ni) q <= RESVAL ; -1- ==> 72 else if (wr_en) q <= wr_data; -2- ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Covered
0 0 Covered

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