Module Definition
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Module Instance : tb.dut.i_reg_wrap.i_irq_classa

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 i_reg_wrap


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_reg_wrap.i_irq_classb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 i_reg_wrap


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_reg_wrap.i_irq_classc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 i_reg_wrap


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_reg_wrap.i_irq_classd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 i_reg_wrap


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_intr_hw
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3311100.00

26 logic [Width-1:0] new_event; 27 1/1 assign new_event = 28 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 29 1/1 assign hw2reg_intr_state_de_o = |new_event; 30 // for scalar interrupts, this resolves to '1' with new event 31 // for vector interrupts, new events are OR'd in to existing interrupt state 32 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; 33 1/1 assign intr_o = reg2hw_intr_state_q_i & reg2hw_intr_enable_q_i;
Line Coverage for Instance : tb.dut.i_reg_wrap.i_irq_classa
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3311100.00

26 logic [Width-1:0] new_event; 27 1/1 assign new_event = 28 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 29 1/1 assign hw2reg_intr_state_de_o = |new_event; 30 // for scalar interrupts, this resolves to '1' with new event 31 // for vector interrupts, new events are OR'd in to existing interrupt state 32 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; 33 1/1 assign intr_o = reg2hw_intr_state_q_i & reg2hw_intr_enable_q_i;
Line Coverage for Instance : tb.dut.i_reg_wrap.i_irq_classb
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3311100.00

26 logic [Width-1:0] new_event; 27 1/1 assign new_event = 28 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 29 1/1 assign hw2reg_intr_state_de_o = |new_event; 30 // for scalar interrupts, this resolves to '1' with new event 31 // for vector interrupts, new events are OR'd in to existing interrupt state 32 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; 33 1/1 assign intr_o = reg2hw_intr_state_q_i & reg2hw_intr_enable_q_i;
Line Coverage for Instance : tb.dut.i_reg_wrap.i_irq_classc
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3311100.00

26 logic [Width-1:0] new_event; 27 1/1 assign new_event = 28 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 29 1/1 assign hw2reg_intr_state_de_o = |new_event; 30 // for scalar interrupts, this resolves to '1' with new event 31 // for vector interrupts, new events are OR'd in to existing interrupt state 32 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; 33 1/1 assign intr_o = reg2hw_intr_state_q_i & reg2hw_intr_enable_q_i;
Line Coverage for Instance : tb.dut.i_reg_wrap.i_irq_classd
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3311100.00

26 logic [Width-1:0] new_event; 27 1/1 assign new_event = 28 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 29 1/1 assign hw2reg_intr_state_de_o = |new_event; 30 // for scalar interrupts, this resolves to '1' with new event 31 // for vector interrupts, new events are OR'd in to existing interrupt state 32 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; 33 1/1 assign intr_o = reg2hw_intr_state_q_i & reg2hw_intr_enable_q_i;
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